small-signal response of inversion layers in high-mobility...

742 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 4, APRIL 2010

Small-Signal Response of Inversion Layers inHigh-Mobility In0.53Ga0.47As MOSFETs

Made With Thin High-κ DielectricsAshkar Ali, Student Member, IEEE, Himanshu Madan, Student Member, IEEE,

Sergei Koveshnikov, Serge Oktyabrsky, Senior Member, IEEE, Rama Kambhampati,Tassilo Heeg, Darrell Schlom, and Suman Datta, Senior Member, IEEE

Abstract—Ultrahigh-mobility compound semiconductor-basedMOSFETs and quantum-well field-effect transistors could enablethe next generation of logic transistors operating at low supplyvoltages since these materials exhibit excellent electron transportproperties. While the long-channel In0.53Ga0.47As MOSFETsexhibit promising characteristics with unpinned Fermi level atthe InGaAs–dielectric interface, the high-field channel mobility aswell as subthreshold characteristics needs further improvement.In this paper, we present a comprehensive equivalent circuit modelthat accurately evaluates the experimental small-signal responseof inversion layers in In0.53Ga0.47As MOSFETs fabricated withLaAlO3 gate dielectric and enables accurate extraction of theinterface state profile, the trap dynamics, and the effective channelmobility.

Index Terms—High-κ dielectric, InGaAs, interface states,small-signal admittance modeling, split capacitance–voltage.

I. INTRODUCTION

U LTRAHIGH-MOBILITY compound semiconductor-based (e.g., indium antimonide, indium arsenide, and

InxGa1−xAs) MOSFETs and quantum-well field-effect transis-tors could enable the next generation of logic transistors oper-ating at low supply voltages since these materials exhibitexcellent low-field and high-field electron transport properties[1]–[3]. Effective channel mobility as a function of the trans-verse effective electric field or inversion carrier density is animportant metric for characterizing the performance of

Manuscript received July 15, 2009; revised December 18, 2009. Currentversion published April 2, 2010. This work was supported in part by the IntelCorporation and in part by the Nanoelectronics Research Initiative through theMidwest Institute for Nanoelectronics Discovery. The review of this paper wasarranged by Editor M. Anwar.

A. Ali, H. Madan, and S. Datta are with the Department of Elec-trical Engineering, Pennsylvania State University, University Park, PA16802 USA (e-mail: [email protected]; [email protected]; [email protected];[email protected]).

S. Koveshnikov is with Intel Corporation, Santa Clara, CA 95052 USA(e-mail: [email protected]).

S. Oktyabrsky and R. Kambhampati are with the University at Albany,The State University of New York, Albany, NY 12203 USA (e-mail:[email protected]; [email protected]).

T. Heeg is with the Department of Materials Science and Engineering,Pennsylvania State University, University Park, PA 16802 USA (e-mail:[email protected]).

D. Schlom is with Cornell University, Ithaca, NY 14853 USA (e-mail:[email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2010.2041855

In0.53Ga0.47As-based MOSFETs since it not only affectsthe long-channel MOSFET performance directly but alsodetermines the short-channel MOSFET performance in thenonballistic regime indirectly by influencing the source-sideinjection velocity [4]. The split capacitance–voltage (C–V )measurement of the MOSFET inversion capacitance is thestandard technique of extracting the effective channel mobilityof MOSFETs, which involves direct estimation of the mobileinversion charge density (Ninv) through the gate to channelcapacitance (Cgc) as a function of the gate-to-source voltage(Vg) as given by

Qinv =

Vg∫

−∞

Cgc(V ) dV. (1)

While this method is reliable and highly accurate for mostsilicon-based MOSFETs, including the high-κ/metal-gateSi MOSFETs, it is less straightforward in the case ofIn0.53Ga0.47As MOSFETs. In InGaAs-based MOSFETs, thecomplex nature of the semiconductor–dielectric interface witha relatively high density of interface states Dit can exhibit acapacitance Cit that contributes significantly to the measuredCgc, even in inversion leading to an overestimation of extractedNinv. This can lead to incorrect evaluation of the effectivechannel mobility. In0.53Ga0.47As and high-κ dielectric inter-faces are known to possess interface defects. Although the exactorigin of the defects is still under debate, there is evidence thatcompound semiconductors exhibit interface states that arisefrom the native defects, such as Ga or As dangling bonds aswell as Ga–Ga -or As–As-like atom bonds created by unwantedoxidation during the process of gate dielectric formation. It hasbeen proposed that the As–As antibonding states due to localexcess arsenic created during the gate oxide deposition can leadto a distribution of states that extend into the conduction band[5], [6]. The presence of interface states near the conductionband leads to a fast trap response as the Fermi level approachesand enters the conduction band in the inversion regime. Manyrecent publications of III–V MOSFETs have reported splitC–V measurements and the resultant mobility calculated fromthose measurements [7]–[9]. Frequency dispersion due to Cit

as well as lumped and distributed resistance effects in theinversion regime has strongly influenced the Cgc versus Vg (orC–V ) curves resulting in incorrect mobility calculations.

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ALI et al.: SMALL-SIGNAL RESPONSE OF INVERSION LAYERS IN HIGH-MOBILITY MOSFETs 743

In this paper, we will outline a novel technique that self-consistently solves the C–V and conductance–voltage (G–V )measurement data as a function of gate bias and small-signalac frequency to uniquely determine the Dit response as well asthe true inversion carrier response for a given voltage. This tech-nique enables us to extract the true inversion capacitance (Cinv)as a function of temperature and gate bias in the inversionregime. The impact of parameters such as oxide capacitance,tunnel conductance, fixed series resistance, distributed channelresistance, and interface state capacitance and conductance onthe extraction of true inversion carrier density is systematicallystudied using the experimental data. Various methods havebeen reported in the literature to correct for interface statedensity. The method proposed by Hinkle et al. [10] requires thelow-temperature C–V to be free from dispersion due to Dit.The method proposed by Zhu et al. [11] compares the measuredC–V data with the simulated ideal C–V to account for thestretch out in the C–V and the output conductance (gds)characteristics. This method also assumes that the experimentalinversion response of the carriers is free from frequency dis-persion due to interface states, which may be applicable forsilicon- and germanium-based materials where the inversioncarrier densities are high due to high density of states (DOS)but not for III–V systems. Martens et al. [12] proposed thefull conductance technique that is suitable for extracting theinterface state density across the entire band gap for any ma-terial system. However, Martens’ approach requires detectingthe exact location of the conductance peak due to interfacestates, which depends on the measurement ac frequency andthe temperature. In addition, the technique does not allow directextraction of the inversion carrier density. Unlike the first twoapproaches [11], [12], our work does not assume a priori thatlow-temperature and high-frequency C–V data are necessarilyfree from Dit effect. Instead, our technique directly extracts theinterface state density, trap time constant, and the frequency-independent inversion channel capacitance by directly solvingan equivalent circuit model from the measured admittancevalues. Another key difference in our proposed method fromthe commonly used full conductance technique [12], [13] isthat, we do not need information about the peak position inthe measured conductance (Git/ω) versus frequency; we rathersolve the conductance and the capacitance contributions ofDit in a self-consistent manner over the entire frequency andvoltage range. This allows us to extract the Dit distribution overa wider range of energy than the one given by the peak conduc-tance method for a given frequency range of the impedance-measuring instrument at a given temperature. This also allowsextraction of the true Cinv free from any frequency dispersion.Extracting the true inversion charge as a function of gate voltagealso enables us to link the gate voltage directly to the surfacepotential in the presence of a “frequency-dependent thresholdvoltage (Vt) and flatband voltage (Vfb) shift,” whereas in [12],it is not possible to obtain the surface potential to gate volt-age relationship unless Vt or Vfb is known precisely. Anothercommon approach in the literature to obtain energy location ofthe traps is from the interface trap time constant by assuminga particular capture cross section [16]. However, capture crosssection values discussed in the literature vary by orders of

Fig. 1. Effect of distributed channel resistance on the (a) C–V and(b) G–V characteristics. (c) Equivalent circuit of a MOSFET in strong inver-sion incorporating the channel resistance and ignoring the effects of interfacestates and gate leakage.

magnitude (1 × 10−12 to 1 × 10−19 cm2), and assuming a par-ticular capture cross-section for energy estimation is susceptibleto errors. Further, in our model, we also consider the effectsof series resistance (distributed channel resistance and lumpedcontact resistance) and gate leakage in addition to the Dit

response while solving the equivalent circuit model. Solvingthe capacitance data together with the conductance data givesmore accuracy in extracting the Dit and Ninv as the capacitancedata are relatively less sensitive to parasitic resistance and gateleakage effects than the conductance data.

II. FACTORS AFFECTING SPLIT C–V MEASUREMENTS

In this section, we systematically explain the impact of dis-tributed channel resistance, gate leakage and interface states onthe admittance behavior of an In0.53Ga0.47As MOS transistorbiased in weak and strong inversion.

A. Effect of Distributed Channel Resistance

Since the interface states in the upper half of the semicon-ductor band gap can respond to small-signal ac frequenciesin the split capacitance measurement, one minimizes the erroreither 1) by increasing the small-signal measurement frequencyor 2) by lowering the temperature of measurement so thatthe interface traps cannot follow the fast changing ac signal.However, the distributed nature of the channel resistance comesinto play at higher frequencies, which causes the measuredcapacitance to be lower than the true capacitance, resulting in anunderestimation of Ninv. This is illustrated in Fig. 1(a), wherethe frequency dispersion in both C–V and G–V data is causedsolely by the channel resistance. Physically, the distributedchannel resistance accounts for the energy loss during theminority carrier transport between the source/drain at any givenposition in the channel. As the channel length increases, the


Fig. 2. Effect of tunnel conductance due to gate to channel leakage on the(a) C–V and (b) G–V characteristics. (c) Equivalent circuit of a MOSFETin strong inversion incorporating the tunnel conductance and the distributedchannel resistance.

dispersion in C–V and G–V also increases due to the increasedchannel resistance.

B. Effect of Gate Leakage

In the case of an ultrathin gate dielectric with a significantgate leakage, we need to consider the effect of the tunnelconductance that shunts the oxide capacitance as well as theinterface state capacitance. A direct impact of this increasedtunnel conductance, which appears in series with the channeland series resistance, is shown in Fig. 2(a), where an increasingpercentage of the ac test voltage appears across the channelresistance as gate leakage increases with higher Vg, leadingto a droop in the C–V characteristics. In Fig. 2(b), we showthe effect of increased tunnel conductance on the G–V datawhere there is a linear monotonic increase in the measuredconductance as the gate voltage is increased.

C. Effect of Interface States

Here, we analyze the effect of interface states on the splitC–V characteristics. The frequency dispersion in the C–V datacaused by the Dit effect is shown in Fig. 3(a). A constantDit distribution (1 × 1013/cm2/eV) across the upper half ofthe bandgap is assumed as an illustrative example in this caseto calculate the frequency dispersion in the C–V and G–V .The presence of Dit causes a frequency-dependent “thresholdvoltage shift” in the C–V characteristics. At lower frequencies,the capacitance rises at lower Vg due to strong contribution fromthe midgap states, while at higher frequencies, the midgap statescannot respond, and the contribution comes primarily from theband edge states that are active at higher Vg. The conductancepeak will also shift to higher Vg’s with higher frequencies as theband edge states get activated.

Fig. 3. Effect of interface states Dit on the (a) C–V characteristics and(b) G–V characteristics. The equivalent circuit model in inversion incorporat-ing the effect of Dit is shown in the inset of (a).

Fig. 4. Effect of interface states, series resistance (contact and channel), andtunnel conductance on the (a) C–V characteristics and (b) G–V characteristics.

D. Effect of Channel Resistance, Gate Leakage, andInterface States

Finally, we show the combined effects of series contact resis-tance, distributed channel resistance, gate leakage, and interfacestates on the C–V and G–V characteristics in the inversionregime in Fig. 4(a) and (b). We identify the various regimesmarked as A, B, C, and D in the G–V –f characteristics. Inregion A, at high gate voltage and low frequency, the mea-sured conductance values are directly related to the tunnelingconductance estimated from the direct current gate leakagemeasurements. In region B, at high gate voltage and highfrequency, the series resistance (from contact resistance anddistributed channel resistance) effect markedly increases thefrequency dispersion of the measured conductance. It shouldbe noted that in the high-gate-voltage regime, as the Fermi levelmoves deep inside the conduction band, the interface state con-ductance is negligible, and the measured conductance is onlythe tunneling conductance modified by the series resistanceand the measurement frequency. In region C, at lower gatevoltage and lower frequency, the conductance peak exhibits astrong frequency dependence due to contribution from the nearmidgap states. In region D, at intermediate gate voltage andhigher measurement frequency, the conductance contributioncomes from the band edge states. The equivalent circuit modelis described comprehensively in Section III.


Fig. 5. Equivalent circuit model of MOSFET in weak and strong inversion:Cox = oxide capacitance; Gtunnel = tunnel conductance; Cit = interfacetrap capacitance; Git = interface trap conductance; Cinv = semiconductor in-version capacitance; Rch = gate bias-dependent inversion channel resistance;and Rcontact = series resistance associated with implanted source/drain re-gions, contacts, and metal pads.

III. EQUIVALENT SMALL-SIGNAL MODEL

A standard LCR meter (HP4285A) was used to measurethe capacitance (split C–V ) and conductance of In0.53G0.47Asn-MOSFETs with LaAlO3 gate dielectric, as a function offrequency and voltage for a range of temperature from 300to 35 K. Measurements were made in parallel mode with asmall-signal ac amplitude of 25 mV. The equivalent model ininversion including all the effects is shown in Fig. 5.

The model incorporates several features that are currentlyabsent in recent publications while extracting the true Ninv

and Dit, particularly when the channel is close to inversionor is inverted. For example, the first step in the formulationof the model is the inclusion of the fixed series resistanceRcontact at the two ends of the channel. In addition, due tothe distributed nature of the inversion channel resistance Rch,we create a transmission line model to accurately reflect theeffect of Rch as well as the tunnel conductance of the oxideGtunnel arising from gate leakage. The gate oxide or insulatorcapacitance Cox is estimated from the maximum capacitancemeasured in accumulation on a MOS capacitor. We verify thevalidity of our Cox estimation by comparing with physicalmeasurements (cross section transmission electron microscopy)as well as from minimizing the error between the calculated andmeasured C–V /G–V data points across the frequency rangeduring the extraction process. A closed-form equation wasderived to model the admittance of the circuit shown in Fig. 5.

The measured admittance between the gate and source/drainfor the circuit shown in Fig. 5 is given by

Ym = Gm + jωCm (2)

where Gm and Cm are the measured conductance and capaci-tance, respectively. Cm and Gm are given by

Cm = Re [C ′ tanh(λ)/λ] + (Git/CIω)Im [C ′ tanh(λ)/λ]+ (Gtunnel/ω)Im [tanh(λ)/λ]

(in farads/square centimeter) (3)Gm

ω= − Im [C ′ tanh(λ)/λ] + (Git/CIω)Re [C ′ tanh(λ)/λ]

+ (Gtunnel/ω)Re [tanh(λ)/λ](in farads/square centimeter) (4)

respectively. Here, C ′ = [CoxCI ]/[Cox + CI + Git/jω], Cox

is the oxide capacitance in (in farads/square centimeter), CI =

Cinv + Cit (in farads/square centimeter), λ = γL/2, γ2 =r1[jωC ′ + C ′Git/CI + Gtunnel], r1 = (W/L)/gds (in ohms),Gtunnel = [∂Ig/∂Vg]/[WL] (in siemens/square centimeter),and gds = [∂Ids/∂Vds] (in ohms). The above model is derivedbased on [15] after including the effects of Cit and Git.

The admittance due to a distribution of interface traps isgiven by the capacitance Cit and the conductance Git, whichis given by [13]

Cit = q

∞∫

−∞

Dit

ωτtan−1(ωτ)P (σs, E) dE

(in farads/square centimeter) (5)

Git

ω=

q

2

∞∫

−∞

Dit

ωτln(1 + ω2τ2)P (σs, E) dE

(in farads/square centimeter). (6)

A random spatial distribution of interface defects causes aspatial distribution in the band bending, which is accounted forby the integrand in (5) and (6), where τ is the interface traptime constant, σs is the surface potential fluctuation, and P is aGaussian distribution with a variance of σ2

s .The effect of surface potential fluctuation was not considered

in our analysis of Cit and Git. The transmission line equiva-lent circuit model was solved for τ , Dit, and Cinv using thealgorithm explained below. The measured conductance and ca-pacitance data from the split C–V measurement are convertedto measured admittance data Ymeasured. These admittance dataare further corrected for contact resistance (obtained from trans-fer length method), as given by 1/Ycorrected = 1/Ymeasured −Rcontact/2. The factor 2 in the above expression is due tothe symmetry between source and drain in the split C–Vmeasurement. These corrected data are now solved to obtainDit, τ , and Cinv over the entire frequency range as given by (7)at a particular bias point, i.e.,∑

frequency

[Ycorrected − Ym(Dit, τ, Cinv)] = 0. (7)

Here, Ym(Dit, τ, Cinv) is the set of all possible solutions asper (2) for the range of Dit, τ , and Cinv considered. Thechannel conductance gds and the tunnel conductance Gtunnel

used in (2) are obtained from Id–Vd and Ig–Vg measurements,respectively. This process is repeated over the entire bias pointsto obtain Dit, τ , and Cinv as a function of voltage. Obtainingtrue inversion charge as a function of Vg enables a naturaltranslation from gate bias to surface potential even in the pres-ence of frequency-dependent Vt and Vfb shift. This allows us toaccurately express Dit as a function of energy. Fig. 6(a) and (b)shows the 300-K experimental C–V and G–V data comparedto the solution obtained from our model, which shows excellentagreement.

IV. EXTRACTING Dit , τ , AND Ninv

Having confirmed the validity of the proposed equivalent cir-cuit model, we proceed to extract the interface state density, itsresponse time, and the true inversion carrier density as a func-tion of gate voltage. We apply our technique to a wide range


Fig. 6. (a) Experimental C–V and (b) experimental G–V data at 300 Kcompared to the modeled data using the proposed equivalent circuit model.

Fig. 7. Equivalent parallel conductance of the traps (Git/ω) as a function ofgate bias and frequency. The trace of the conductance peaks (shown in dottedred line) reflects the Fermi level movement.

of operating temperatures of the In0.53Ga0.47As MOSFET toextract the Dit, τ , and true Ninv from 300 K down to 35 K.

Unlike the full conductance method, we can quantitativelyextract the Dit over a wide range of energy at room temperatureeven though the precise location of the conductance peak(Git/ω)peak is outside the measurement frequency range. Fig. 7shows the equivalent parallel conductance of the interface trapsas a function of gate bias and frequency. It can be seen thata subset of conductance peaks, particularly at low gate bias,which corresponds to midgap trap response, is outside the mea-surement frequency range. However, on solving the equivalentcircuit model, the Dit data are precisely extracted for low gatebias. The extracted Dit and τ are shown in Fig. 8(a) and (b).Fig. 8(b) also reveals the typical Λ-shaped characteristic ofthe interface trap time constant τ(E). It is noteworthy that theDit profile extracted independently from the measured C–Vand G–V data at three different temperatures are consistentwith each other. The Dit profile could be interpreted as a sumof two Gaussian distributions with high and low peak values.The Gaussian with the high peak spans across the midgap ofthe In0.53Ga0.47As semiconductor and is responsible for thesubthreshold slope (SS) degradation commonly observed inIn0.53Ga0.47As-based MOSFETs [14]. The second Gaussiandistribution with lower peak extends toward and into the

Fig. 8. (a) Extracted interface state density versus energy and (b) extractedtrap response time versus energy.

Fig. 9. (a) Extracted trap response time versus energy compared to thetheoretical response time. (b) Experimental and theoretical (without Dit) sub-threshold slope and the interface state density extracted from the experimentalsubthreshold slope as a function of temperature.

conduction band. Since this peak is much reduced, high oncurrent in inversion is expected and has been experimentallyreported for In0.53Ga0.47As MOSFETs [7]. In Fig. 9(a), wecompare the extracted time constant at three different tempera-tures with the theoretical value calculated using the expressionτe = (Ncσvt)−1 exp(ΔE/kT ) [13], where Nc is the effectiveconduction band DOS, σ is the capture cross section, vt isthe thermal velocity of electrons, and ΔE = Ec − E is theenergy location of the trap with respect to the conduction band.Since we are analyzing the device in inversion, we need to onlyaccount for the exchange of carriers with the minority band(i.e., conduction band for the p-type substrate). We get a strongagreement between the measured time constant and its theoret-ical estimate over a large range of energy and temperature, fur-ther validating our extraction approach. Fig. 9(b) compares thesubthreshold slope (SS) obtained from the measured transfercharacteristics of In0.53Ga0.47As MOSFETs and the theoreticalSS without Dit as a function of temperature. The expressionfor the SS is given by SS = [2.3kT/q][1 + (Cd + Cit)/Cox],where Cox is the oxide capacitance, Cd is the semiconductor


Fig. 10. Measured C–V and extracted true C–V characteristics ofIn0.53Ga0.47As MOSFETs at 300, 200, and 77 K.

Fig. 11. (a) Extracted Ninv from the C–V and G–V measurements and(b) measured effective mobility as a function of inversion charge density.

depletion layer capacitance, and Cit is the capacitance dueto interface states. The interface state density obtained fromthe experimental SS, plotted in Fig. 9(b), is around 1.5 ×1013 cm−2 · eV−1. This is consistent with the range of themidgap Dit concentration profile that we extracted from thesmall-signal admittance modeling [Fig. 8(a)] where the Dit

ranges from 1 × 1013 to 3 × 1013 cm−2 · eV−1.Fig. 10 shows the measured C–V characteristics exhibiting

the effects described above and the extracted true inversioncapacitance characteristics for three different temperatures. Thetrue mobile inversion charge density as a function of gatevoltage Vg is plotted in Fig. 11(a). The slope of each of thecurves is roughly equal to 0.49 μF/cm2, which is equivalent tothe series combination of the In0.53Ga0.47As inversion chan-nel capacitance (limited by DOS) and the insulator capaci-tance, which is 0.65 μF/cm2 (equivalent oxide thickness is5.45 nm). Finally, the effective inversion channel mobility ofIn0.53Ga0.47As MOSFETs is extracted [Fig. 11(b)] using thelow-field drain conductance and the inversion charge extractedusing the model.

V. CONCLUSION

In summary, we have presented here a comprehensive equiv-alent circuit model to analyze the true small-signal response

of inversion carriers in In0.53Ga0.47As MOSFETs with high-κgate dielectric. Our approach attributes the frequency dispersioncommonly observed in the C–V and the G–V measurementdata of In0.53Ga0.47As MOSFETs quantitatively to various con-tributing factors such as the interface states, contact resistance,distributed channel resistance, and the tunnel conductance. Thisallows us to self consistently solve for the frequency-dependentinterface state response and the frequency-independent trueinversion carrier density for a range of gate bias.

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Ashkar Ali (S’09) received the B.S. degree in ma-terials science and engineering from the Indian In-stitute of Technology, Madras, India, in 2007 andthe M.S. degree in engineering science from thePennsylvania State University, University Park, in2009, where he is currently working toward the Ph.D.degree in electrical engineering in the Department ofElectrical Engineering.

His research interests include oxide and III–Vinterface characterization, and simulation, fabrica-tion and characterization of narrow-gap quantum-

well FETs for beyond silicon technology nodes.

Himanshu Madan (S’09) received the B.S. degreein electronics and telecommunications engineeringfrom the College of Engineering, Pune, India, in2008. He is currently working toward the M.S. de-gree in electrical engineering in the Department ofElectrical Engineering, Pennsylvania State Univer-sity, University Park.

His research interests include small-signal re-sponse of minority and majority carriers in III–Vchannel FETs with high-κ gate stacks up togigahertz-frequency domain.

Sergei Koveshnikov received the M.S. degree insemiconductor device and technology engineer-ing from the Moscow Power Engineering Institute(Technical University), Moscow, Russia, in 1981 andthe Ph.D. degree in solid state physics from theRussian Academy of Science, Moscow, in 1992.

From 1992 to 1995, he was a Postdoctoral Re-search Associate with the Department of MaterialsScience and Engineering, North Carolina State Uni-versity, Raleigh. In 1995, he joined S.E.H. America,Vancouver, WA, where he worked for seven years as

a Senior Scientist and Manager of the Materials Characterization Group. He iscurrently a Senior Engineer at Intel Corporation, Santa Clara, CA. For the pastfive years, he has been with Intel External Programs as a Research-in-Residenceat the University of Texas, Austin, and at the University at Albany, The StateUniversity of New York, Albany, working on the research and development ofhigh-κ dielectrics gated MOS devices on Si and compound semiconductors forfuture logic applications.

Serge Oktyabrsky (SM’08) was born in Moscow,Russia, in 1956. He received the M.S. degree (withhonors) in physics and engineering from MoscowInstitute of Physics and Technology, Moscow, in1980 and the Ph.D. degree in solid state physics fromthe Lebedev Physics Institute, Moscow, in 1988.

From 1978 to 1993, he was with the LebedevPhysics Institute as a Senior Scientist and Head ofthe Electron Microscopy Group from 1988. From1993 to 1998, he was a Visiting Scientist at NorthCarolina State University, Raleigh. He is currently a

Professor and the Leader of a photonics team at the College of Nanosciencesand Nanoengineering, University at Albany, The State University ofNew York, Albany, specializing in the research and development of materialsand structures for novel optoelectronic devices. He has more than 25 yearsof experience in electronic materials, design, fabrication, and characterizationof semiconductor electronic and photonic devices. He is the author of over180 papers in these fields. His recent research activities focus on physics andtechnology of quantum confined structures, microcavity photonic devices, andgroup III–V-based MOSFETs.

Prof. Oktyabrsky is a member of the International Society for OpticalEngineering (SPIE), the Materials Research Society, the American VacuumSociety, and the Microscopy Society of America.

Rama Kambhampati received the B.E. degree inelectronics and communication engineering from theUniversity of Madras, Chennai, India and the M.S.degree in nanoscale science and engineering fromthe University at Albany, The State University ofNew York, Albany, in 2007, where he is currentlyworking toward the Ph.D. degree in the College ofNanoscale Science and Engineering.

His research interests include integration ofhigh-κ dielectrics with group III–V-based channelmaterials for high-performance low-power digital

logic applications.

Tassilo Heeg received the Diploma in physics fromthe Jülich Research Centre, Jülich, Germany, andthe Ph.D. (Dr.rer.nat.) degree from the University ofCologne, Cologne, Germany.

He is currently doing postdoctoral studies in theDepartment of Materials Science and Engineering,Pennsylvania State University, University Park. Hisresearch interests include high-dielectric-constantmaterials for microelectronic applications.

Darrell Schlom received the B.S. degree from theCalifornia Institute of Technology, Pasadena, and theM.S. and Ph.D. degrees from Stanford University,Stanford, CA.

After a postdoctoral research at IBM’s ResearchLaboratory, Zurich, Switzerland, he spent 16 yearson the faculty at Pennsylvania State University, Uni-versity Park. He is currently a Professor with theDepartment of Materials Science and Engineering,Cornell University, Ithaca, NY. His research inter-ests include alternative gate dielectrics and the het-

eroepitaxial growth and characterization of oxide thin films, including theirepitaxial integration with semiconductors using MBE. He is the author of over300 published papers. He is the holder of eight patents.

Dr. Schlom is a Fellow of the American Physical Society. He received theMRS Medal from the Materials Research Society for his work on high-κdielectrics. He received the Invention Achievement Awards from IBM and SRC,Young Investigator Awards from the Office of Naval Research, the NationalScience Foundation, and the American Association for Crystal Growth, anAlexander von Humboldt Research Fellowship, and the American Society forMetals International Bradley Stoughton Award for Young Teachers.

Suman Datta (SM’06) received the B.S. degree inelectrical engineering from the Indian Institute ofTechnology, Kanpur, India, in 1995 and the Ph.D. de-gree in electrical and computer engineering from theUniversity of Cincinnati, Cincinnati, OH, in 1999.

From 1999 to 2007, as a member of the LogicTechnology Development and Components ResearchGroup, Intel Corporation, he was instrumental inthe demonstration of the world’s first indium-antimonide-based quantum-well transistors operat-ing at room temperature with a record power-delay

product, the first experimental demonstration of metal-gate plasmon screeningand channel strain engineering in high-κ/metal-gate CMOS transistors, andthe investigation of the transport properties and the electrostatic robustness innonplanar “trigate transistors” for extreme scalability. Since 2007, he has beenwith Pennsylvania State University, University Park, as the Joseph MonkowskyProfessor for Early Faculty Career Development, exploring new materials,novel nanofabrication techniques, and nonclassical device structures for CMOS“enhancement” as well as “replacement” for future energy-efficient computingapplications. He is currently an Associate Professor with the Department ofElectrical Engineering, Pennsylvania State University. He is the author of over65 archival refereed journal and conference papers. He is the holder of 91 U.S.patents.

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