soc development and dft strategy in nano-scale erasoc.yonsei.ac.kr/test/lectures/lg.pdf ·...

LG Electronics Inc.5th Korea Test Conference

June 4 2004

SoC Development and DFTStrategy in nano-scale Era

Woo-Hyun Paik (白佑鉉)[email protected]

System IC DivisionLG Electronics


June 4 2004

Outline

•• System and SoC TrendsSystem and SoC Trends•• Role of SoCRole of SoC•• SoC Design ChallengesSoC Design Challenges

•• DFT IssuesDFT Issues• DFT Methodologies• Variables to choose DFT Methods• Preparation for Next Big Wave


June 4 2004

System and SoC Trends

Requirement for ChipsSystem Trends

Variety, Rapid Changes

Small, Lite, Multi-function, Network

Multimedia Convergence

Standardization of core technology

Digital

Hardware & Software Integration

One Chip solution forCore Function

Integration for convergence&

Various Interface

System On Chip (SoC)with Embedded CPU & DRAM


June 4 2004

• PC• Mobile Handset• PDA• Smart Phone

• PDP• LCD• OLED

• Control Network• Data Network• A/V(Entertainment) Network

DTVDTV

SoC

SmartSmartCardCard

PortablePortableStorageStorage

FPDFPD

HomeHomeNetworkNetwork

InformationInformationTerminalTerminal

EmbeddedSW

DigitalContents

NewNew

MaterialsMaterials

Microprocessor,Microcontroller

Microprocessor,Microprocessor,MicrocontrollerMicrocontroller

GPS3D accelerator,Virtual Reality

GPSGPS3D accelerator,3D accelerator,Virtual RealityVirtual Reality

ATM,WLAN,

Bluetooth

ATM,ATM,WLAN,WLAN,

BluetoothBluetooth

HDTV, DVDMP3, DigitalCamcorder

/Camera

HDTV, DVDHDTV, DVDMP3, DigitalMP3, DigitalCamcorderCamcorder

/Camera/Camera

CDMA, IMT2000,4G, OFDM

CDMA, IMT2000,CDMA, IMT2000,4G, OFDM4G, OFDM

ApplicationApplicationAreaArea

ComputerComputer

Tele-communications

Tele-communications

3D graphics3D graphics

MultimediaMultimedia

NetworkNetwork

Role of SoC

• Memory Stick• SD Card• Compact Flash• USB*


June 4 2004

SoC Design Challenges

Complexity, Difficulty, Design Cycle, Cost

IBS Jan 2002, ITRS 2001 Report


June 4 2004



June 4 2004


Concentration & Cooperation is veryimportant for successful SoC development

System CompanySystem CompanyDesign / IP PartnerDesign / IP Partner

EDAEDA

FoundryFoundry

“Partnership”

Outsourcing

“Partnership”

SoC Design Methodology


June 4 2004

SoC Design Challenges SoC at LGE

1. A/V decoder solutions 1. A/V decoder solutions

• ATSC/DVB HD/OpenCable/ ARIB/ DirecTV• Dual HDTV signal Decoding• DVD Decoding, MPEG4, H.264• Dolby AC-3/DTS decoder• Embedded CPU(ARM)• USB2.0,IEE1394 interfaces


June 4 2004

SoC Design Challenges SoC at LGE

2. VSB/QAM demodulation IC 2. VSB/QAM demodulation IC

• Digital Terrestrial/ Cable Ready TV/ Open Cable• ATSC compliant 8/16 VSB receiver• ITU-T J.83 Annex B compliant 64/256 QAM receiver • Long Ghost Cancellation Range : 55us• Embedded memory• 10 bit ADC

Integrates LGDT3302(VSB/QAM)Adopted at major companies DTVsUsed at LGE products also

VSB NIM moduleVSB NIM module


June 4 2004

Outline

•• System and SoC TrendsSystem and SoC Trends•• Role of SoCRole of SoC•• SoC Design ChallengesSoC Design Challenges

•• DFT IssuesDFT Issues• DFT Methodologies at LGE• Variables to choose DFT Methods• Preparation for Next Big Wave


June 4 2004

DFT Issues Process Issue : Test Escapes

• Single stuck-at faults(SSF) model– Cover many physical defects

– Does not verify circuit timing

– In recent study, fully two-thirds of defects found

were missed by a SSF simulation that had 100% fault coverage

• In DSM environments– Open and shorts tend to be resistive rather than “hard”

– Speed related failures are increasing• Transition/gate delay/path delay fault model

• IEEE DELTA’02, “Delay faults have been identified as the cause of

most test escapes in LGE’s 4 million gates, 108MHz multimedia ICs”

– Soft defects are increasing• Tight noise margin and low stability

– Open faults will be dominant fault model in the nano-era


June 4 2004

DFT Issues Process Issue : Stuck-open Faults in DSM

• Timing failure– About 5.6 % of the passed– Circuit delays in the DSM domain

cannot be modeled discrete values– Frequency of bridging faults and

open vias is increasing due toCu process (Dual damascene*/SI/Noise)

– Resistive short/open, resistive bridgingdefects require “at-speed” test

Because Copper does not form a volatile by-product, it is very difficult to etch, and therefore Copper metallization schemes cannot be realized using the traditional subtractive etching approach used to form Aluminum metal lines. The Dual Damascene technique overcomes this problem by etching a columnar hole, followed by a trench etch into the inter-layer dielectric (ILD), and then filling both structures with Copper which is subsequently polished back (using Chemical Mechanical Polishing (CMP)) to the surface of the ILD. The result is a vertical Copper via connection and an inlaid copper metal line.


June 4 2004

DFT Issues SoC Issue : Test Difficult Challenges


June 4 2004

DFT Issues Cost Issues I

• Die area– Rule of thumb

• Spend 5% - 10% die area on DFT

– Larger dies imply less revenue/profit• Lower yield for a given defect density• Fewer die per wafer = less revenue/profit from a given FAB.

• Power & di/dt– In mission mode, portions of chip are powered down

• Large clock sub-trees & blocks of logic don’t toggle

– Test modes may consume more power• In scan mode, more state toggles during shifting• At-speed BIST even worse• Burn-in tests accelerate infant mortality failures

– More expensive power supplies & cooling solutions required


June 4 2004

DFT Issues Cost Issues II

• Application Time– Scan shifting takes a long time

• 100K scan cells shifted at 100MHz takes 1 ms• 5000 shifts (ATPG output for stuck-at faults) takes 5 seconds

– Memory testing takes a long time• Combination of memory test patterns takes time 30n• Applied to a 32K cache takes ~1M cycles• Apply patterns at 10MHz, test time is 100 ms• Repeat for 20 embedded memories, total time is 2 seconds

– Add I/O tests, boundary scan tests, functional tests, delay tests…

• ATE– NRE (Nonrecurring expenditure) cost

• ITRS (International Technology Roadmap for Semiconductor)– ATE cost per pin will be constant : Design cost per pin will decline– Chip speeds have improved at 30% per year,

ATE accuracy has improved at 12% per year

– ATE is most expensive piece of equipment in the FAB


June 4 2004

DFT Methodologies at LGE

• “Big Iron” functional testers– Not used in LG since it is useful for CPU/MCU developing companies.

• Digital test– Scan is mandatory– Logic BIST/At-speed scan/Test compress/ATE

• I/O test– Boundary scan(STD.IEEE1149.1) is Mandatory– ATE– Board tester supporting JTAG is used at system level

• Memory test– Memory Built-In Self Test– Mandatory for embedded SRAMs (ASIC, MCM)– External MBIST is being prepared

• Mixed signal test– ATE


June 4 2004

DFT Methodologies at LGE

At-speed ScanTraditional Scan

• Easy to implement• Designers can not feel a

burden• Simple coverage matrix

– Single stuck-at fault coverage

• Disadvantages– High test cost– Yield is not quality of chip

• High defect level (test escape): thousand ppm

• Designers/managers may welcome– “They don’t have to change their

DFT scheme dramatically”

• Disadvantages– High test cost

• High-end ATE is essential

– Not easy for multi-clock designs• What is test clock?

• At-speed scan test flow wascompletely setup– Being used for mass product chip


June 4 2004

DFT Methodologies at LGE Test Compress

• Test data volume and test time reduction

–Test pattern reduction using lossless coding such as run-length code• It is not considered

–Test pattern reduction using scan chain splitting internally• It is applicable now


June 4 2004

DFT Methodologies at LGE Logic BIST

• At-speed test becomes inevitable

• Gap between Chip tech. & ATE tech.– It takes years to bring a new tester to market

using yesterday’s architectures and pin electronics tech.

– Tester will be obsolete before it comes to the marketplace

– Lots of focus on DFT testers (or DFT-focused on test system)

• The only place to control the eventual cost of test– During chip design phase

– New breed of guys called DFT engineers

– Foundries will dictate the cost of test based on

the testability of the design

• LG already has know-how to implement hierarchical LBIST

for over 5M gates chip


June 4 2004

DFT Methodologies at LGE Logic BIST

Arguments against the LBIST

• Memory BIST is mature and well accepted– At-speed, external memory testing, scheduling, DRAM testing

• Logic BIST is still in the early stages– There are a few flow and technology issues to resolve

• Investments– The person, skill, methodology and flow changes required

to deploy logic BIST– Logic BIST eliminates external stored patterns, opens the door

to system test, board component diagnosis and IC manufacturing test– And partner BIST technology with the new generation of low-cost ATE

• Silicon area– Silicon is money– BUT, IO and ATE is more expensive– Area overhead argument is specious today


June 4 2004

Variable to choose DFT Methods Quality vs. Speed

• Low-speed scan : 1260 PPM• At-speed scan : 540PPM

Center for Reliable ComputingStanford Univ.


June 4 2004

Variable to choose DFT Methods

• Chip 1 : # of FFs is 92,550 – Max. scan chain length : 14,102– # of deterministic vector : 641– WGL : 196 Mbytes @ 5M cycles

• Chip 2 : # of FFs is about 176,103– WGL : 0.377 + 1.575 Mbytes @ 61.6 M cycles

• ATPG requires more ATE memory to support at-speed test– Transition fault model– Double-capture

• Need for sequential ATPG, which is not only much more CPU intensivethan combinational ATPG, but typically results in an unacceptablylarge number of test patterns

• Test compress– EDA vendor said it is possible to decrease the volume by 10X ~ 100X– In our experience, 5X ~ 20X is possible for multi-clock design

Test Vector Volume


June 4 2004

Variable to choose DFT Methods Test Time

• Test Time = # of vector * Max. scan chain * Operation frequency

• Scan testing– Max. scan chain length is dependent on the available ATE

• Test compress– The length of max. scan chain length is configurable

• LBIST– # of vector may be 32K or 64K (configurable)– Operation frequency is same as that of functional mode– The length of max. scan chain length is configurable


June 4 2004

Preparation for Next Big Wave

• High Speed Device Interface– High frequency and high pin count test socket– High speed serial interface requires high speed source/capture

and jitter analysis. FDT/DFM techniques must be developed.

• Highly Integrated Design– Structure and specific DFT for embedded specialized cores.– Analog DFT and BIST techniques to simplify test interface.– RF and audio circuit embedded in large noisy digital blocks.– Test reuse for reusable cores in complex designs.

• Reliability Screens– Limited existing methodologies: burn-in vs. thermal runaway,

IDDq vs. large background current.– Identify novel infant mortality defect stress conditions.

• Manufacturing Test Cost– Cost reduction: massively parallel, wafer level test, wafer level burn in.– Through DFT to reduce test pin count and time and equipment reuse.– Test standards to enable test content reuse and manufacturing agility.


June 4 2004

Conclusion

• What are the key factors for successful SoC?– Concrete design methodologies

– Right strategies for development target

– Proper development and business model

• What is the best DFT solution?– Priority is the most important criterion

– 1st priority is the test quality for the chips using DSM process at LGE

– Proper DFT method is selected according to the in-house DFT policy

– There is no best DFT solution, but we have to preparevarious methodologies to cope with the future

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