soc & embedding system group
DESCRIPTION
SOC & Embedding System Group. Embedding System Embedded OS – 曾建超 Multimedia – 蔡淳仁 , 蔡文錦 Low power mobile – 曹孝櫟 Storage – 張立平 SOC Design & CAD Network – 林盈達 Architecture and Systems – 鍾崇斌、單智君 Wireless base-band Processor – 許騰尹 Multimedia SOC Design – 蔡淳仁 , 彭文孝 - PowerPoint PPT PresentationTRANSCRIPT
SOC & Embedding System Group Embedding System
Embedded OS – 曾建超 Multimedia – 蔡淳仁 , 蔡文錦 Low power mobile – 曹孝櫟 Storage – 張立平
SOC Design & CAD Network – 林盈達 Architecture and Systems – 鍾崇斌、單智君 Wireless base-band Processor – 許騰尹 Multimedia SOC Design – 蔡淳仁 , 彭文孝 Electrical Design Automation – 李毅郎
Wireless Access to InternetGPRS/3G/PHS/
WiMax/...
Internet WLAN/Bluetooth/PAN/...
Ad hocAd hoc
Mesh
Mobile NW
•3G/GPRS/PHS•WiMax/WLAN/Bluetooth/PAN
Heterogeneous Wireless Overlay Networks– Multi-interface Handheld Devices
Roaming and
HandoffsMy Interests :-)
Embedded WLAN
PHS3G/GPRS
Embedded OS for Multi-interface Handheld Devices Cross-layer design for Real-time Applications
Linux/Windows XP/CE Driver, Network, and Application Layers (VoIP)
Heterogeneous Wireless Networks WLAN/WiMax/3G/GPRS/PHS Roaming and Handovers
Multi-tier Wireless Network WPAN, WLAN and Mobile Router Roaming and Routing
Wireless Mesh and Sensor Networks Address Assignment and Routing
Secured and Fast Accesses to Wireless Network
Embedded Systems ( 曹孝櫟助理教授 )Research Directions
Embedded Software for B3G/4G Mobile Devices Protocol Stacks for 4G access Embedded Operating System and Device Drive
rs, and their Optimization for Mobile Devices Cooperate with international and local vendors
and institutes to development 4G/multimode radio SOC
Establish the reference embedded software for next generation mobile devices/Radio SoCs
Embedded Systems ( 曹孝櫟助理教授 ) R&D Results - Low Power and Fast Handover Low Power and Fast Handover
Cellular/WLAN Dual Model MobilesCellular/WLAN Dual Model Mobiles
Awarded by 2005 Mobile Communications Contest of Industrial Development Bureau, MOEA2005 Software Contest of National Center of High-Performance Computing2006 Embedded Software Contest of MOE
Power Consumption Evaluation
Handover Latencies Evaluation
PDA/Smartphone H/W Platform
Cellular/VoWLAN integrated UA
WinCE/Smartphone 2003
TAPI
GSM interfaceWLAN interface
NDIS driver
WinSock
TCP/IP
device driver
Mobility management
Power management
SIP/SIMPLEUA/Stack
Cellular call control
System Architecture and Prototype of Cellular/WLAN
Dual Mode Mobile
Prof. Li-Pin Chang 張立平
Recent research directions Embedded storage systems Real-time systems and scheduling algorithms Hardware-software co-design
Embedded Storage: Efficient wear-leveling algorithm for flash memory
To capture uneven usages from millions of blocks and to level them
Result: the most fast, effective, economic approach available!!
0
5,000,000
10,000,000
15,000,000
20,000,000
25,000,000
30,000,000
35,000,000
40,000,000
0 500 1,000 1,500 2,000 2,500 3,000 3,500
Time
LB A
Access pattern
0
20000
40000
60000
80000
100000
120000
140000
160000
1 18 35 52 69 86 103 120 137 154 171 188 205 222 239 256 273 290 307 324 341
Block #
Era
se c
ycl
e
#
Block usage
Worn-out quickly!
Real-Time Systems:Overload Management for Real-Time Object Tracking
Firm-real-time: (c,4)((4,7),c,4)
Proportional Adjustment: (c,4)(c,7)
Average RMS error Average RMS error
Inter-arrival time of frames : 4ms. Workload-scaling factor: 4/7 (57%)
i
"j
FE
((4,7),2,4)
(1,4)
drop drop
i
'j
PP
(2,7)
(1,4)
Hardware-Software Co-designReconfigurable computing for overload management
Reconfigurable computing for overload management Past achievement:
Overload management for event-driven real-time embedded systems
Working-in-progress: To deal with transient workload bursts wit
h hardware acceleration Move critical tasks onto FPGA
• Computing resource reclamation• On-line floor planning• On-line topology reconfiguration for network-
on-chip (NoC)
Embedded Systems ( 蔡文錦 ) - Research Directions
Low-power embedded systems Video compression/decompression
Plan in the near future
Low-power AVC/H.264 video CODEC algorithm and system design
Multimedia Embedded Systems Lab ( 蔡淳仁 ) – Research Directions
SoC Design for Advanced Video Codecs DVB/MHP middleware & Java Runtime Java Processor for DVB/MHP Flexible Multimedia Codec SoC Platforms OS Kernel Scheduler for Tightly-coupled Hete
rogeneous Multi-core Platforms
Multimedia Embedded Systems LabR&D Results
H.264 Codec Accelerators on ARM Integrator Java Processor Accelerating Technologies on
Spartan 3 and ML-310 Platforms (based on the open source JOP project)
Video Rate Control for HW/SW Co-designed SoCs (patent application)
Tightly-coupled H.264 encoder on TI-OMAP 5912
Tightly-coupled kernel scheduler module for ARM-Linux on TI-OMAP 5912
Future Plans
Implementation a flexible multimedia codec SoC platform
Design of a new Java Processor for DVB/MHP
Design of Hardware-Friendly Psychovisual-models for Video Codec
Clean Design of a Multi-core OS kernel suitable for Tightly-Coupled Task Scheduling
Architecture and SystemsResearch Directions ( 單智君 鍾崇斌 )
Embedded processor and SoC Java processor, JIT compilation &VM DSP designs and compilation Low-power systems Graphic processor Superscalar ARM processor Reconfigurable computing
Architecture and SystemsR&D Results ARM9-compatible processor with
video/audio capabilities Java stack operations folding Memory Constrained Java Just-in-time
Compiler DSP– instruction set extensions Low-power Branch-Target-Buffer Low-power bus encodings Low-power cache memory Graphic processor design techniques Superscalar ARM Reconfigurable computing
ARM9-compatible Processor with Audio/Video Capabilities
ARMAVP (ARM Audio Video Processor) 為 32位元微處理器，採用負載平衡良好的五階管線設計，分別為 Fetch Unit 、 Decoder Unit 、Execution Unit 、 Memory access Unit 以及 Write Back Unit 。對各階的設計進行效能的最佳化，以提高時脈頻率，並提供有效率的機制，降低了因為記憶體速度太慢對微處理機效能上的影響
特性 支援 Conditional Execution ABP 緩衝器設計 改良指令抓取所需時間 精確中斷控制結構 非同步的記憶體存取 動態暫存器組的映射 分支指令的快速處理 多功能有效率的執行路徑 分散式指令控制編碼
功能驗證與評估 所有功能已在 Altera EP20K600EBC652-1 上完
成驗證。根據 Decode Stage 之模擬結果，在 FPGA 上可工作於 45MHz ，預期實做為晶片時可達210MHz
DSP– Instruction Set Extensions
Current research topics Multiple-issue architecture
Exploring ISE in a multiple-issue architecture, such as superscalar or Very Long Instruction Word (VLIW)
Hardware reusebility Reuse same or similar hardware resources in differe
nt ASFUs while keep same performance Overcome register file read/write port constraint
Try to schedule the input and output of ASFU at different time slots
Low-power Bus Encodings
在此我們針對不同的匯流排架構的特性，提出了不同的低電耗匯流排編碼系統。我們的編碼系統利用了各種編碼方法，將藉由匯流排傳輸的資料，以最具有電耗效率的方式來傳送，達到省電的效果。
低電耗匯流排編碼系統
處理器指令位址匯流排
T0 + Discontinuous Address Table指令匯流排
BIBITS with Register Relabling
指令記憶體
資料記憶體
資料位址匯流排T0_BI_1,Variable-Stride,SRWEC
資料匯流排Leading-bytes encoding
處理器指令、位址混和之位址匯流排
I/D Selector,T0 DAT+Stride-Table指令、位址混和之匯流排
I/D Selector,BIBITS_RR+Leading-bytes
記憶體
匯流排編碼架構傳送端
編碼器原始資料
接收端
解碼器 編碼過的資料
額外控制線路原始資料
Low-power Cache Memory
快取記憶體佔有整體處理器超過 50% 之功耗
低功耗快取記憶體設計 Loop Buffer: 將 loop co
de 置入低耗電存取之 loop buffer 中以節省指令擷取之功耗
Power Manager: 將不常使用之快取記憶體區塊置入低耗電模式以節省快取記憶體之靜態功號。
Low-power mode
Loop Buffer
CPU
70%
30%
Power Manager
Normal mode
Low-power mode
Low-power mode
Normal mode
low-power accesses
normal accesses
Graphic Processor
Pixel ShaderColor
ShaderVertex
Processing
Texture Shader
Pixel Processing
Triangle Setup
Vertex Shader Clip
Vertex
V.S. Prog.
P.S. Prog.
Rendering
Depth Processing
Final Pixel
Pixel ShaderColor
ShaderVertex
Processing
Texture Shader
Pixel Processing
Triangle Setup
Vertex Shader Clip
Vertex
V.S. Prog.
P.S. Prog.
Rendering
Depth Processing
Final Pixel
1
23 4
5
研究目的︰進行新一代繪圖處理器架構研究，於像素著色器 (Pixel Shader) 、材質 (Texture) 及深度處理 (Depth Processing) 等三大方向提出硬體架構及軟體驗證環境。目前成果分項說明如下︰
1. A dynamically reconfigurable graphics hardware for resource reallocatable rendering pipeline
2. A Reconfigurable Texture Mapping Architecture 3. Implementation of texture Compression by GPU Driver 4. Register Renaming for Pixel Shaders data/value management5. Instruction scheduling mechanism for 3D GPU pixel shader6. An Efficient Texture Memory System Designs7. Alpha Blending without Z Sort
6
Superscalar ARM Goal: a superscalar embedded processor featuring
800MHz clock rate @ 0.13um 1.8DMIPS / MHz – superscalar performance under tough pipeline late
ncy 800K gate count – cost-effective design
Directions and achievements Micro-architecture
A 12-stage dual-issue superscalar processor with good instruction fetch rate, issue rate, and efficient forwarding
Simulator A cycle-accurate simulator modeling more details than the well-know
n simplescalar simulator Compiler
Working on GCC machine description to optimize performance
Reconfigurable Computing
Motivations:Motivations: Improving the Design Improving the Design
Methodology of Methodology of Embedded System Embedded System HardwareHardware
Providing a Better Providing a Better Performance with Low Performance with Low Development Cost Development Cost
Shorting the Time-to-Shorting the Time-to-Market of SoC ProductsMarket of SoC Products
Research Issues:Research Issues: Hardware/Software Hardware/Software
PartitionPartition Synthesize TechnologySynthesize Technology Reconfigurable Processing Reconfigurable Processing
Element DesignElement DesignReconfigurable Architecture
Processor(ARM7 / MIPS)
On-Chip Mem /Cache Mem
Data Engine
ReconfigurableLogic
ConfigurationControllor
Main busData bus
Memory Management Unit
External bus
Off-ChipMemory
Memory-mappedIO
( 1 / 2 )
Research overview in SOC and Embedded Systems ( 林盈達 ) Research theme:
Content networking with deep packet inspection by software and hardware solutions; with applications in Internet security (intrusion detection, anti-virus, anti-spam, content filtering, MSN/P2P management)
Embedded software Embedded Linux solutions: 7-in-1 10-in-1 A startup company, L7 Networks (L7-Networks.com), 2002, f
or all-in-one security gateways SoC
Key component in content networking: string matching hardware acceleration needed!
FPGA-based development to accelerate Aho Crosaic and Bloom Filtering algorithms
Embedded and SoC GroupSelected R&D Results (2/2)
7-in-1 integrated security gateway String Matching Engine to Accelerate Aho Corasic Machi
ne Unified Content Filtering Hardware Platform String Matching Hardware with Bloom Filters
LAN/DMZ
Redirect RouteMAC Filter
In-LAN Filter
Out-WAN Filter NAT
IPsecVPN
BandwidthMgt.
LAN/DMZ to WAN Outbound Traffic
Policy Route
sniff
Y Y
Y
Y
RedirectBandwidth
Mgt.IPsec
deVPNIn-WAN
Filter
Out-LAN Filter deNAT
Y
Intrusion Detection
AlertingSystem
Route
FTP/POP3/SMTP/Web/URL Filter with Many-to-One NAT
WAN
WAN to DMZ/LAN Inbound Traffic
7-in-1 Integrated Security Gateway
• 7-in-1: VPN, Firewall, NAT, Routing, Content Filtering, Intrusion Detection, Bandwidth Management
• Launched a startup in 2002: L7 Networks Inc.
Next stateof AC
Bus
Text
Processor
… …… …Text
…… ……
H1 H2
Bit vectors
PossiblyMatched?
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Loadbit
vector
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....
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. Root index tables
Rootnext table
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Index
Next state of Root-Indexing .
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State table
Loadstate
Compute next state1 0
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Next state address
Next state
Root-Indexingmatching
Pre-Hashingmatching
ACmatching
Root indextable
Root nexttable
Bit vectortable
Next state
address
Statetable
String MatchingCoprocessor
Currentstate
String Matching Engine to Accelerate Aho Corasic Machine New Parallel Architecture with Pre-Hashing and Root-
Indexing
Unified Content Filtering Hardware Platform
Resolve content filtering issues
Match without interrupt CPU
Multiple connections management
On-fly match non -fixed payload
Multiple patterns and multiple matched outputs
Length Text Pointer
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Text Descriptors in DRAM
StatusTextID
First Matched Offset
Last MatchOffset
Length Text PointerStatusTextID
First MatchedOffset
Last MatchOffset
Length Text PointerStatusTextID
First MatchOffset
Last MatchOffset
FA State
FA State
FA State
Str
ing
Ma
tchi
ng S
peci
fic D
MA
Str
ing
Ma
tchi
ng E
ngin
e
DM
A/S
MD
ual P
ort
SR
AM Address2
Data2
Matched_Interrupt
Matched_Pattern_ID
Matched_Text_ID
Finished_Interrupt
Start
Read
Address1
Data1
Write
Matched_Text_OffsetText_Start_Address
Text_End_Address
Matched_Address
Status
Start
Start
CPURegister
File
Content Filtering Hardware
String Matching Hardware with Bloom Filters
Leavingbyte
Enteringbyte
Blo
om
filte
r(1)
Blo
om
filte
r(2)
Blo
om
filte
r(3)
shift controller
Feature Set:1. Allow maximum shift distance if possible.2. Reconfigure rules easily.3. Keep constant hardware complexity.
detect prefix(p,1)detect prefix(p,2)detect factorin p
Platform:Xilinx ML310 Embedded Development Platformwith embedded PowerPC 405 processorXilinx Virtex-II Pro XC2VP30 FPGAMontaVista Linux Professional Edition 3.0
Embedded and SoC GroupMajor Projects
Excellence Project: Next Generation Information Communication Networks ( 卓越後續計劃 , 國科會 2004~2008): 林盈達，曾文貴 (with 24 faculty members)
Network Benchmarking Lab ( 工研院交大網路測試中心 , www.nbl.org.tw, 經濟部工業局 , 2003~2007) 林盈達
Attack Session Extraction and Comparison with Nessus (Cisco San Jose, 2005~2006) 林盈達
Content-based Network Security - Content Classification: Design, Implementation, and Evaluation ( 整合型計劃 , 國科會 , 2004~2006) 林盈達 (with 李程輝 , 孫雅麗 )
Open Source Product Testing Tools: In-Lab Live Testing ( 國科會 , 2005~2006) 林盈達
Biography of Ying-Dar Lin 林盈達 Areas of research interests
Design, implementation, analysis, benchmarking of Internet gateway devices (10-in-1: routing, NAT, firewall, VPN, IDP, CF, anti-virus, anti-spam, IM, P2P, bandwidth management, link load balance, etc.)
Internet security and QoS Content networking Test technologies of switch, router, WL
AN, security, and VoIP Publications
International journal: 39 International conference: 33 IETF Internet Draft: 1 Industrial articles: 124 Books: 2 Patents: 16 Tech transfers: 8
B.S., NTU-CSIE, 1988 Ph.D., UCLA-CS, 1993 Professor, NCTU-CS, 1999~ Founder and Director, ITRI-NCTU Net
work Benchmarking Lab (NBL; www.nbl.org.tw), 2002~
Co-Founder, L7 Networks Inc. (www.L7.com.tw), co-invested by D-Link, ZyXEL, and Advantech, 2002
Consultant, CCL/ITRI, 2002~ Well-cited paper: Multihop Cellular: A N
ew Architecture for Wireless Communications, INFOCOM 2000, YD Lin and YC Hsu; # of citations: 150
Wireless Baseband Processor ( 許騰尹 )
MIMO OFDM PHY Ultra Low-power PHY Generic PHY architecture Chip Implementations
PAM Match Filter
Sp
readin
g
CT
RL
Clock Generator
Clock Recovery
Divider
SpreadingGate Count :500Max. Freq : 80MHz
SpreadingGate Count :500Max. Freq : 80MHz
Clock GeneratorGate Count :2600Max. Freq : 165MHz
Clock GeneratorGate Count :2600Max. Freq : 165MHz
PAM Match FilterGate Count :4800Max. Freq : 80MHz
PAM Match FilterGate Count :4800Max. Freq : 80MHz
Digital DividerGate Count :900Max. Freq : 60MHz
Digital DividerGate Count :900Max. Freq : 60MHz
CTRLGate Count :1500Max. Freq : 80MHz
CTRLGate Count :1500Max. Freq : 80MHz
Clock RecoveryGate Count :1500Max. Freq : 178MHz
Clock RecoveryGate Count :1500Max. Freq : 178MHz
Data Rate 4/2/1 Mbps
PN Length 11 Chips
Freq. (MHz) 44(outer)/132(inner)
Max. IF 22MHz
Core Size 3700X3700um2
Power 420mW @4Mbps
Data Rate 4/2/1 Mbps
PN Length 11 Chips
Freq. (MHz) 44(outer)/132(inner)
Max. IF 22MHz
Core Size 3700X3700um2
Power 420mW @4Mbps
Wireless Baseband Processor
Proto-type 802.11b Baseband+MAC chip
Item Specification
Technology 0.25um CMOS 1P5M
VLSI Type Cell-Based Design
Function 802.11b Baseband+MAC
System Frequency
44MHz
Package 208 QFP
Gate Count Not available
Chip Size Not available
Power supply 2.5V (digital)3.3V (analog)
Power Dissipation
650mW
PLL
A/D (I)
A/D (Q)D/A
Architecture and SystemsR&D Results
ARM9-compatible processor with video/audio capabilities (technology transferring)
Java stack operations folding (patents) Asynchronous 8051 on FPGA Low-power Branch-Target-Buffer (patent
application) Low-power bus encodings (patent
applications) Graphic processor design techniques
SOC Electrical Design Automation ( 李毅郎 ) – Research Directions
Reliable Interconnect Design Crosstalk-driven Interconnect Design Design-for-Manufacture (DFM)
Interconnect Design Layout Migration
VLSI Cell Migration with Topology Preservation
Post-Layout Platform for Verification and Optimization
SOC Electrical Design Automation– RD Results
Tile-based Gridless ECO Router with Graph Reduction Two times faster than existing tile-based routers.
NEMO: A New Full-Chip Gridless Router Faster than all academic gridless routers
Crosstalk-driven Track Assignment Pre-Detailed Routing Design Flow Considering C
apacitive- and Inductive-Noise Constraints
SOC EDA Group RD Results - New ECO Routing Design Flow
SOC EDA Group RD Results – Full-Chip Gridless Router
Electronic System Level Design ( 彭文孝 )
R e quire m e nt D e f ini t io n
Spe c if ic at io nD e ve lo pm e nt
S pe c if ic a tionM ode l
H ardwareR TL D e ve lo pm e nt
F P G AP roto type
Synthe s is
Sys te m Arc hi te c tureM o de l D e ve lo pm e nt
So f tware D e ve lo pm e nt
S ys te m In te gra tiona nd V e rif ic a tion w ith R T L
P lac e m e nt and R o ute
C hip Fabrac t io n
D es ig n reg res s ion
R e quire m e nt D e f ini t io n
Spe c if ic at io nD e ve lo pm e nt
S pe c if ic a tionM ode l
Sys te m Arc hi te c ture andTL M D e ve lo pm e nt
TL M
R TL
H W R e f ine m e nt
SWD e s ign
andD e ve lo pm e nt
H WVe r if ic at io nE nviro nm e ntD e ve lo pm e nt
Traditional Design Flow Design Flow
with ESL
http://mapl.nctu.edu.tw
System Level Verification
and Integration
System Level Verification
and Integration
First Time Silicon Success
Design Practice: Transaction Level Modeling for H.264 Decoder ( 彭文孝 )
32-b it AH B C ontro l Bus
External Mem ory InterfaceS
SD R AM 0
C ABACC AVLC
S
128-b it AH B D ata Bus
B it-streamFIFO
AR M 9C PU
M
InstructionM emory
D ataM emory
IQ /ID C TS
MBTextureBuffer
MBMotionBuffer
D ata FetchS
Intra /InterP rediction
S
SubblockR econstruct
Buffer
D eB lock ingS ,M
IIPFIFO
D B FIFO
D eInterlacerS ,M
D I F IFO
SD R AM 1 SD R AM 2 SD R AM 3
H arddware Input InterfaceM, M
Sync F IFO
H D MIInterface
Subblock Processing Unit
N ALParsing
http://mapl.nctu.edu.tw
Bus Arbitratio
n
Control Bus Output
Interface
Data Transactio
n
Bank0
Bank1
Bank2
Bank3
Bank0
Bank1
Bank2
Bank3
Bank0
Bank1
Bank2
Bank3
Bank0
Bank1
Bank2
Bank3
Bank0
Bank1
Bank2
Bank3
Bank0
Bank1
Bank2
Bank3
Bank0
Bank1
Bank2
Bank3
Bank0
Bank1
Bank2
Bank3
Bank0
Bank1
Bank2
Bank3
Bank0
Bank1
Bank2
Bank3
Bank0
Bank1
Bank2
Bank3
Bank0
Bank1
Bank2
Bank3
Bank0
Bank1
Bank2
Bank3
Bank0
Bank1
Bank2
Bank3
Bank0
Bank1
Bank2
Bank3
Bank0
Bank1
Bank2
Bank3
0 0
0 0
1 1
1 1
0 0
0 0
1 1
1 1
0 0
0 0
1 1
1 1
0 0
0 0
1 1
1 1
0 0
0 0
1 1
1 1
0 0
0 0
1 1
1 1
0 0
0 0
1 1
1 1
0 0
0 0
1 1
1 1
0 0
0 0
1 1
1 1
0 0
0 0
1 1
1 1
0 0
0 0
1 1
1 1
0 0
0 0
1 1
1 1
0 0
0 0
1 1
1 1
0 0
0 0
1 1
1 1
0 0
0 0
1 1
1 1
0 0
0 0
1 1
1 1
0 0
0 0
1 1
1 1
0 0
0 0
1 1
1 1
6 4
6 4
SDRAM Controlle
r
Video Pipe
CPU
M em ory
1B
2B
1B
NB
2B
MB
1
2
N
1
2
N
n(1 -n )
1nP2nP
NPn
1n)1( q
Mqn)1(
2n)1( q
Cache
SoC for Multi-Standard Video Codec ( 彭文孝 )
HD Capturin
g
Color Transfor
m
System on Chip
ARM-9 CPU
3-A Functionaliti
es
Networking
Architecture C Model
Video Codec
http://mapl.nctu.edu.tw
Embedded SRAM and Ob-Chip Bus
Bus Arbitratio
n
VLSI/SOC Research for Graphics SysteVLSI/SOC Research for Graphics System m (( 范倫達老師范倫達老師 ))
3-D Graphics Demo Here!
VLSI Information Processing LABAdvisor: Lan-Da Van (
VLSI/SOC Research for Adaptive CommVLSI/SOC Research for Adaptive Communications unications (( 范倫達老師范倫達老師 ))
虛擬系統單晶片平台 (Virtual SOC Platform) 建置 – 使用 CoWare Platform Architect 提供虛擬系統平台供軟體人員程式開發 提升系統模擬之層級以提高系統驗證效率 發展效能評估指標 : 根據效能評估指標的模擬結果進而得到系統架構的最佳配置，以供系
統開發時有所依據 在不同的軟硬體組態，模擬各功能函數所花費的時間 在不同的軟硬體組態，計算模組對 bus 之進行存取次數
ROM
ARM926
Instruction
din
Display
stub RAM
APB
SW
AHB
Data
clock
resetdTCMiTCM
Block diagram of platform
0x0(0x100000)
0x400 0000(0x100000)
0xc000 0000(0x1)
20 / 32
20 / 32
1 / 8
32 / 32
32 / 32
AddrBits / DataBits
Memory location (size)
FFT HW 0x1000 0000(0x4)
Virtual SOC Verification Platform
IU CU
MULTR8-FFT
DFMRAM
FFT/IFFT Chip Design
IP Implement
ation