Software Defined Radio

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OutlineDigital Hardware Choices Hardware Elements DSP Processor Field Programmable Gate ArraysTrade-Offs in DSP, FPGA and ASIC

Digital Hardware ChoicesFlexibility-Overall system clock rate be adjustable in different data rateModularity-allow easy replacement or upgrading of subsystemScalability allow the radio to be enhance to improve capability (increase channels)PerformancePower consumption, cost ,computational capability metrics

Hardware ElementsDSPs: microprocessor-based, support high level languages like C, offer the most flexibilityASICs :circuit in fixed silicon ,optimized speed and power consumption, requires sophisticated circuit design and layout software tools.FPGAs: provide much hardware-level reconfigu-rability, flexibility: DSP>FPGA>ASIC. Tools for FPGA are similar to those for ASIC

Trade: flexibility, processing speed and power consumption

DSP ProcessorDigital Signal ProcessorsDSPs are designed to include special functional units in the hardware as well as special instruction in the microcode FFT or Viterbi decodingConsists arithmetic logic unit (ALU), accumulator MAC unit and data and address busesFor wireline and wireless communication ,or general control application

Categories of general available DSPs

Categories of general available DSPs

DSP ArchitectureHarvard ArchitectureProgram memory and data memoryOn-chip or off-chip memoryUniscalar ArchitectureMore than one multiplier and ALUExecution of one instruction per cycleSingle Instruction Multiple Data (SIMD)Very Long Instruction Word ArchitectureSuperscalar ArchitectureHybrid Architectures

Harvard Architecture

Numeric RepresentationFixed PointLess power and costFloating PointEasy to program than fixed point DSP

PipeliningPipelining is setting up and executing in parallel the various stages of instruction processing

Field Programmable Gate ArraysOptimized for multilevel circuitStatic random access memory (SRAM)SRAM-based FPGA can be reprogrammed and on-the-fly during the operation of the sys.

Xilinx 4000 Series FPGA Structure

Application of FPGA to software RadiosSystem with high sample rateSystem with very-high-order FIR filters because the algorithm can be implemented in parallelSystem with fast correlators because the LUT architecture of FPGA provides a fast and efficient way to build correlators

Trade-Offs in DSP, FPGA and ASICLow complexity can be solved with DSPFPGA and ASIC tend to be more useful when the complexity of the problem increasesUsing a combination of DSP, FPGA and ASIC.

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Asic ,FPGA and DSPs Each exhibits a certain level of reprogammabilityA custom computing machine (CCM)() is an example CPUASICCPUCPUASIC

Single Instruction Multiple Data (SIMD) - vector processing Motorola MPC7455, 2280 MIPS at 1Ghz PowerPC architecture with SIMD instruction extension called AltiVecVLIW architecture is more recent attempt at increasing DSP performance provides more processing elements that be used in parallel typically four to eight instructions are executed per clock cycle Texas Instruction TMS320C62x with eight processing (two multipliers and six ALU) in 300MHz ->2400MIPS easily programming in an HLL such as CSuperscalar Architecture the difference is the parallelism (scheduling) is set up mostly in hardware making the superscalar DSP easier to program than VLIW In practice, the pipeline can be stalled (),