sram (2)

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    Static RAM (SRAM)

    Latch.

    + .

    + refreshing.+ .

    - DRAM.

    Dynamic RAM (DRAM)

    dynamic node.

    + .

    -! refreshing "leakage. # SRAM.

    -# (noise).

    data

    write/read

    data

    write/read

    C

    storage cellstorage cell

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    RowDeco

    der

    Row Address

    Storage cell

    Word line

    Bit line

    Sense amplifiers(read)/Drivers (write)

    Column decoderColumn Address

    Data I/O

    Read: select desired bitsWrite: do not write unwanted bi

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    Inside the RAM Device

    Address inputs gointo decoder

    Only one

    output activeWord line selects a

    row of bits (word)

    Data passes

    through OR gateEach binary cell

    (BC) stores one bit

    Input data stored if

    Read/Write is 0

    Output data drivenif Read/Write is 1

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    Inside the SRAM Device

    Note: delay primarilydepends on the numberof words

    Delay not effected bysize of words

    How many addressbits would I need for16 words?

    Word

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    Array Architecture

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    Six transistor CMOS SRAM cell.Six transistor CMOS SRAM cell.

    word

    line

    bit bit

    $ word line (VDD) Latch bit bit Latch bit bit .

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    SRAM BanksSRAM Banks

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    Read OperationRead Operation

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    Write Operation

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    Example 1 : Combination of Read/Write

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    Summary

    Memories provide storage for computers

    Memories are organized in words

    Selected by addresses

    SRAMs store data in latches

    Accessed by surrounding circuitry

    RAM waveforms indicate the control signals needed for

    access

    Words in SRAMs are accessed with decoders

    Only one word selected at a time