sync sram1 tr

8/12/2019 Sync Sram1 tr

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S nchronousSRAMs


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What is an Synchronous SRAM?

Async SRAM

Control

Data In/OutReg

Clock

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Register

A Register is an element which is capable of storing binary data.

A clock is a stream of ositive and ne ative ulses occurrin at re ular intervals.

Positive pulse is always preceded or succeeded by a negative pulse.

A register can be activated only at the edges of the clock.Rising Falling

Clock

pulse Negative

pulse

e ge e ge

Re ister

Data In Data Out

Data Inclock

Data Out

A combinatorial signal doesnt pass through registersA combinatorial signal doesnt pass through registers.

A combinatorial logic responds to any change in the inputsA combinatorial logic responds to any change in the inputs.It is notIt is not

controlled b a clock.controlled b a clock.

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S nc. SRAM OverviewSync SRAM

FT

.

QDR

B2

DDR

B2FT

,

ZBT

PL(DCD)

PL(SCD)

B4

QDR-II &+

B4

DDR-II &+

PL(DCD)

QDR-II

& II+B4

DDR-II

&II+ B4

-II&II+

SIO (B2)

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Sync. SRAM Overview

Each Family has numerous options as well:

1 Mb 72 Mb X18, X36 (X8, X9, X32, X72)

400MHz,300MHz,250MHz, 167MHz, etc.

Timing Options-> eg Read Latency . , , .

Burst Options Interleaved, Linear,Burst 2,Burst4

ore o tage 3.3V, 2.5V, 1.8V

I/O Volta e

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LVTTL: 3.3V, 2.5V, 1.8V,1.5V

HSTL, Variable impedance


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Sync. SRAM Overview

Each Family has even more options:

Packages

100 TQFP, 165 fBGA, 119 BGA, 209 BGA

Tem erature Ran es Commercial, Industrial,Automotive

Chip Enables Address Locations

JTAG ,

Names NoBL = ZBT = NtRAM = ZBL = ZERO SB = Etc.

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,


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Sync SRAM Family

Sync SRAMsSync SRAMs

Standard SyncStandard Sync NoBLNoBL QDR/QDRII/QDRII+QDR/QDRII/QDRII+ DDR/DDRII/DDRII+DDR/DDRII/DDRII+

Standard Sync SRAMsStandard Sync SRAMs NoBL SRAMsNoBL SRAMs

QDR /QDR II/QDRII+QDR /QDR II/QDRII+

DDR /DDR II/DDRII+DDR /DDR II/DDRII+

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Standard Sync SRAM

Sync SRAMs

Standard Sync NoBL QDR/QDRII/QDRII+QDR/QDRII/QDRII+ DDR/DDRII/DDRII+DDR/DDRII/DDRII+

Flowthrough Pipelined

SCD DCD

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Synchronous SRAM

Standard Sync SRAMStandard Sync SRAM

Common I/OCommon I/O

Offered in both Pi eline and Flowthrou hOffered in both Pi eline and Flowthrou h

Single cycle deselectSingle cycle deselect SCDSCD ( Flowthrough and Pipeline)( Flowthrough and Pipeline)

Double Cycle DeselectDouble Cycle Deselect DCDDCD ( Pipeline Only!)( Pipeline Only!)Best for either dominated ReadsBest for either dominated Reads ororWritesWrites

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Flowthrough Timing Diagram A

dd.Deco

Write

Reg.

Address

I/OMemory

Core

e

Logic

Control

Flowthrough SRAM = Sync SRAM with only a register on I/P

Clk

Clock

ress

WE#

23

OUT1 IN2Data


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Pipelined Timing Diagram

Address

Add.Decod

Write

Reg.

Out

Control I/OCore

e

Logic

putReg.

Read Write

Pipelined SRAM = Flowthrough SRAM + Output register

Clock

R1 W3Address

WE#

24

OUT1 IN3Data

Data is pushed out one cycle due to theoutput register


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SCD v/s DCD

SCDSCD SingleSingle--Cycle DeselectCycle Deselect One clock cycle until chip deselectsOne clock cycle until chip deselects Available in Pi elined and Flowthrou hAvailable in Pi elined and Flowthrou h

DCDDCD DoubleDouble--Cycle DeselectCycle Deselect Two clock cycles until chip deselectsTwo clock cycles until chip deselects Available in Pipelined onlyAvailable in Pipelined only

ClockClock

CE#CE#

p ese ec ep ese ec e

I/O Disabled within one clock

OUT1 OUT2 OUT3SCD Data

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DCD Data OUT1 OUT2 OUT3 OUT4

I/O Disabled within two clockcycle after deselect


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Flowthrough vs. Pipeline

Pipeline operates at higher frequency than FlowthroughPipeline operates at higher frequency than Flowthrough

Flowthrou h is used where the initial latenc is a criticalFlowthrou h is used where the initial latenc is a critical

issue and a Pipeline SRAM is used where the speed is aissue and a Pipeline SRAM is used where the speed is acritical issue.critical issue.

r e opera ons can a e a s ng e c oc cyc e o comp e er e opera ons can a e a s ng e c oc cyc e o comp e e

for both Flowthrough and Pipeline.for both Flowthrough and Pipeline.

Read operations take 2 clock cycles in flowthrough and 3Read operations take 2 clock cycles in flowthrough and 3clock cycles in Pipeline.clock cycles in Pipeline.

In networking applications where read/write is balancedIn networking applications where read/write is balanced

,,as efficient.as efficient.

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NoBL SRAMs

Sync SRAMs

Std Sync NoBL QDR/QDRII/QDRII+QDR/QDRII/QDRII+ DDR/DDRII/DDRII+DDR/DDRII/DDRII+

Pipelined Flowthough

No Bus Latency (NoBLNo Bus Latency (NoBLTMTM))

No dead cycles between reads and writesNo dead cycles between reads and writes

pt m ze or rea s an wr tespt m ze or rea s an wr tes

Best for Networking ApplicationsBest for Networking Applications

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Offered in both Pipelined and Flowthrough modesOffered in both Pipelined and Flowthrough modes


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NoBL SRAMs

Read BWrite A

Now a write is possible here

Write C

No Operation. (Dead Cycles!)

Standard Pipelined SRAM

Clock

Data I O A B C

Write A Read B Write C Read Write

NoBL Pipelined SRAM = Read and Write on Every Cycle!

Data I/O A B C

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What is NOBL ?

NoBL SRAMs = Stand Sync SRAMs(FL or PL) + NoBL logicNoBL SRAMs = Stand Sync SRAMs(FL or PL) + NoBL logic

Add.De

WriteReg.

/OE

Address

Add.Dec

WriteReg.

/OE

I/OMemory

Core

code

No

Log Control

I/O

Memory

Core

ode

NoB

Logi

utputReg.

Clk

Lic

Clk

Flow Through oPipeline

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Flowthrough NoBL Operation

No Dead Cycles between Reads and WritesNo Dead Cycles between Reads and Writes

ClockClockWriteWrite Read Read WriteWrite WriteWriteReadRead

/WE/WE

CECE

AddressAddress AA BB CC DD EE

F/T Data I/OF/T Data I/O AA BB CC DD

Data inData in Data outData out Data inData in Data outData out

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Pipelined NoBL Operation

ClockClockWriteWrite ReaRea r ter te r ter teReadRead

/CE/CE

AddressAddress AA BB CC DD EE

Data inData in

AA BB CC DD

Data outData out Data inData in

P/L Data I/OP/L Data I/O

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Standard Sync Vs NoBL

STANDARD SYNCSTANDARD SYNC NOBL

MOST EFFECTIVE FOR BURSTMOST EFFECTIVE FOR BURST

READS OR WRITES FOR L2 CACHEREADS OR WRITES FOR L2 CACHE

IDEAL FOR NETWORK APPLICATIONSIDEAL FOR NETWORK APPLICATIONS

IDEAL FOR READ/WRITE RATIO OF 1IDEAL FOR READ/WRITE RATIO OF 1

IDEAL FOR DOMINANT READ ORIDEAL FOR DOMINANT READ OR

WRITEWRITE

LATENCY OCCURS WHENLATENCY OCCURS WHEN

ENABLES FASTER MEMORYENABLES FASTER MEMORY

PERFORMANCEPERFORMANCE -- ELIMINATES THEELIMINATES THE

LATENCY CYCLELATENCY CYCLE

APPLICATIONSAPPLICATIONS

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QDRSync SRAMsSync SRAMs

Std SyncStd Sync NoBLNoBL QDR/QDRII/QDRII+QDR/QDRII/QDRII+ DDR/DDRII/DDRII+DDR/DDRII/DDRII+

QDR IQDR I QDR II/II+QDR II/II+

QDR = Quad Data RateQDR = Quad Data Rate

Optimum for balanced Read/ Write ApplicationsOptimum for balanced Read/ Write Applications

==

Double Data Rate on Separate Ports = 4X BandwidthDouble Data Rate on Separate Ports = 4X Bandwidth

HSTL(High Speed Transceiver Logic) I/O LevelsHSTL(High Speed Transceiver Logic) I/O Levels

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Programmable output Impedance using ZQ pinProgrammable output Impedance using ZQ pin


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QDRI Burst of 2BLOCK DIAGRAM

2 Word Burst QDR SRAM2 Word Burst QDR SRAM

Separate Read and Write control signalsSeparate Read and Write control signals

Vref signal due to HSTL I/OVref signal due to HSTL I/O

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QDRI Burst of 2Read Operation

ReadRead Read Read Read Read

K

/K

/RPS

A BAdd. C D E GF H

Data Out Q(A) Q(A)+1 Q(C) Q(C)+1

C

Q(E)

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/C


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QDRI Burst of 2Write Operation

WriteWrite

Address BAddress B

WriteWrite

Address DAddress D

WriteWrite

Address FAddress F

K

/K

/RPS

BAdd.

Data In D(B) D(B)+1 D(D) D(D)+1 D(F) D(F)+1

D F

D(H) D(H)+1

H

C

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/C


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QDRI Burst of 4

BLOCK DIAGRAM4 Word Burst QDR SRAM4 Word Burst QDR SRAMBurst of 2 and 4 are two different partsBurst of 2 and 4 are two different parts

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Data Flows in one directionData Flows in one direction


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QDRI Burst of 4

Read O erationReadRead Read Read

K

/K

/RPS

AAdd. B C D

Data Out

C

Q(A) Q(A)+1 Q(A)+2 Q(A)+3 Q(C)

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/C


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QDRI Burst of 4

Write O erationWriteWrite

Address BAddress B

K

/K

/RPS

AAdd.

Data In

B C D

D(B) D(B)+1 D(B)+2 D(B)+3

C

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/C


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QDR Advantages

4x Network Performance

FeaturesFeatures BenefitsBenefits

* Simultaneous Accesses* Simultaneous Accesses * Improved* Improved~~

* DDR Interface on Both Ports* DDR Interface on Both Ports * Improved* ImprovedBandwidth(~2x)Bandwidth(~2x)

* Pipeline Output* Pipeline Output * Low Initial Latency* Low Init ial Latency

* Se arate In ut/Out ut Ports* Se arate In ut/Out ut Ports * No Bus* No Bus

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ContentionContention

* 165 FBGA Package* 165 FBGA Package * Reduced Board Area* Reduced Board Area


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QDR to QDR-II Transition

Address

D

/RPS

/WPS CQ

/BWSCQb

K Kb C Cb

ene sene s

Provides Echo Clock

Allows higher speed operationDoff

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QDR-II Features

QDR II Purpose:QDR II Purpose:

QDRQDR--II Has Internal DLL (Delay Lock Loop)II Has Internal DLL (Delay Lock Loop)-- ,,

Source Synchronous Clocks (Echo Clock) AddedSource Synchronous Clocks (Echo Clock) Added Echo Clock OutputsEcho Clock Outputs FromFrom SRAMSRAM

Guaranteed Relationshi to Valid DataGuaranteed Relationshi to Valid Data

Additional 1/2 Clock of LatencyAdditional 1/2 Clock of Latency

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QDR-II Block Diagram

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Data Flows in one directionData Flows in one direction

QDRII B t f 2


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QDRII Burst of 2Operation

Read/Write Access

ReadRead Read Read Read ReadWriteWrite WriteWrite WriteWrite

K

/K

/RPS

Address A C EDB F G

DataIn (D)

DataOut (Q)

D(B) D(B+1) D(D) D(D+1) D(F) D(F+1) D(G) D(G+1)

Q(A) Q(A+1) Q(C) Q(C+1) Q(E) Q(E+1)

/C

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Extra cycle of latency


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QDRII Burst of 4

O eration Read/Write Access

K

/K

eaea eaear er e r er e

/WPS

/RPS

Address

DataIn (D)

A B C D

D(B) D(B+1) D(B+2) D(B+3) D(D) D(D+1) D(D+2) D(D+3)

C

/C

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QDR-II Advantages

The 2nd Generation

* 300Mhz Fmax* 300Mhz Fmax * Hi her Bandwidth* Hi her Bandwidth

* 1.5 Clock cycle Pipeline* 1.5 Clock cycle Pipeline * Low Initial Latency* Low Initial Latency

* 18Mb / 36Mb / 72Mb* 18Mb / 36Mb / 72Mb * Hi her Densit* Hi her Densit

* Echo clocks* Echo clocks * Source* Source--Sync. Output DataSync. Output Data

** **

* 1.8V Power Supply* 1.8V Power Supply * Lower Power * Lower Power

** **

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QDR QDR II


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QDR vs QDR-IISummary of Differences

QDR QDR-II

Maximum Frequency

Burst of 2: 167MHz

Burst of 4: 200 MHz

Burst of 2: 167 MHz

Burst of 4: 300 MHz

Fre uenc Minimum

(DLL Constraint) z

Data Valid Window 1.4ns @ 167MHz

1.9ns @ 167MHz

1.4ns 250MHz

Initial Latency 1 clock cycles* 1.5 clock cycles*

Echo Clocks No echo clocks Echo clocks

Density 9Mb / 18Mb / 36Mb 18Mb / 36Mb / 72Mb+

Power Supply 2.5V 1.8V

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* By adding an clock cycle of latency to QDR-II, the access time is reduced to 0.45ns from QDRs 2.5 ns.


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DDR

Std Sync NoBL QDR/QDRII/QDRII+QDR/QDRII/QDRII+ DDR/DDRII/DDRII+DDR/DDRII/DDRII+

DDR I DDR II/II+ DDR II/II+ SIO

DDR = Double Data RateDDR = Double Data Rate

Optimized for Dominant Reads OR WritesOptimized for Dominant Reads OR Writes

Double Data Rate InterfaceDouble Data Rate Interface

Commonly referred to as Networking DDR and DDRCommonly referred to as Networking DDR and DDR--IIIIData transferred on both edges of the clockData transferred on both edges of the clock

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wo an our or urs ev ceswo an our or urs ev ces


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QDR vs. DDR

Address

DQ

BW

RPSWPS

DDR Characterist ics

Double Data RateCommon I/O

K Kb C Cb

QDR Characteristics

Address

D/QDDR

Double Data RateSimultaneous R/W Access

possible

Separate Input and Output ports

BW

R/W

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K Kb C Cb


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DDR Block Diagram

Address/

Input Data

Address Decode /

Control Logic

Memory Arrayegister

Output Data

egister

NOP No Opp Cycle to

Clock

R

Clock

WriteRead

prevent bus contention

R1

OUT1

W2

OUT2 OUT3

Address

DataOUT4 IN1

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DDR II

Changes from DDR

Internal DLL Higher clock frequency

Latency increased by half a cycle Increase Data Valid Window

Clock

WriteRead

R1

OUT1

W2

OUT2

Address

DataIN1

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by half cycle


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DDR-II Block Diagram

Input Data

Address/

Control

ress eco e

Control Logic

gister

Memory Array ster Output Data

Re

Reg

Input Clock

Output Clock

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DDR & DDR II


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DDR & DDR-II

2 Reads OR 2 Writes / Clock Cycle = DDR & DDR-II

I/O Bus is the Only Major Difference From QDR & QDR-II

Feature Benefit

Bandwidth

DDR Interfaces Higher Mb/s

DDR: 200MHz Hi her Mb/s- : z

Package Pin/Ball Shared I/O bus

(DDR & DDR-II CIO)Reduces ball count

Bus ContentionSplit I/O buses

(DDR-II SIO)

Eliminates bus

contention

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z

clock cycle

relative to QDR


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DDR II SIO

Address/

Control

ress eco e

Control Logic

gister

Memory Array ister Output Data

Input Data

Re

Reg

Input Clock

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DDR II SIO

DDR-Separate I/O (SIO)

Separate Input and Output Buses

n y ne pera on er oc

Can Not Perform Data Forwarding FeatureEliminates Bus Contention

Two Word Burst Only

WriteRead

R1 W2Address

OUT1

IN2

Port

OUT2Read

Data

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QDR & DDR SRAM


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QDR & DDR SRAM

Architectures QDRQDRTMTM // QDRIIQDRIITMTM Separate Input and Output BusesSeparate Input and Output Buses

4X Increase in Bandwidth From NoBL4X Increase in Bandwidth From NoBL

TMTM

TMTM TMTM Single I/O BusSingle I/O Bus

Double Data Rate InterfaceDouble Data Rate Interface

2X Increase in Bandwidth Reduces ASIC/FPGA Pin Count2X Increase in Bandwidth Reduces ASIC/FPGA Pin Count

DDRII Separate I/ODDRII Separate I/O O erates like a DRIIO erates like a DRII--burst of 2 device with access on onlburst of 2 device with access on onl

one port per clock cycleone port per clock cycle Separate Input and Output BusesSeparate Input and Output Buses

Double Data Rate Interface on Both BusesDouble Data Rate Interface on Both Buses

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2X Increase in Bandwidth From NoBL2X Increase in Bandwidth From NoBLTMTM


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QDR - DDR Summary

QDR and QDRII are optimized for systems with BalancedQDR and QDRII are optimized for systems with Balanced

READ and WRITE operationsREAD and WRITE operations

Packet memoryPacket memory

Linked-list

oo up a e

Statistics Storage

DDR and DDRII are optimized for data streaming operationsDDR and DDRII are optimized for data streaming operationsor READ/WRITE unbalanced systemsor READ/WRITE unbalanced systems

L2 CacheL2 Cache

Micro rocessor network rocessor DSP memorMicro rocessor network rocessor DSP memor

DDR Separate I/O optimized for 1 address/clock 2-word burstDDR Separate I/O optimized for 1 address/clock 2-word burstsystemssystems

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n m ze us a ency, max m ze requencyn m ze us a ency, max m ze requency


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QDRII+/DDRII+ Overview

What is it?

Latest QDR Consortium Defined QDR SRAM

Why do you care?

Frequency Support up to 500MHz

Sim lif Board Desi n

What are the Main Differences to QDRII?

Read Latency of 2.0 Offered for Latency Critical Applications

ea a ency o . ere or requency r ca pp ca ons

Data Valid Pin

What Densities? Speeds?

18M, 36M, 72M, 144M Maximum CY Frequency

Technology 2.0 Cycle Latency 2.5 Cycle Latency

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90-nm 375MHz 400MHz

65-nm 400MHz 500MHz


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QDRII+/DDRII+ Overview

QDRII+/DDRII+ Differences to QDRII/DDRII

QDR II / DDRII QDRII+ / DDRII+ Remark

Frequency (DLL ON) 119MHz~333MHz 300MHz~500MHz

Organization x8, x9, x18, x36 x9, x18, x36

VDD 1.8V +/-0.1V 1.8V +/-0.1VVDDQ 1.8V+/-0.1V or 1.5V+/-0.1V 1.5V +/-0.1V

Read Latency 1.5 clocks 2.0 & 2.5 clocks QDRII+ read latency is not user

.

devices.

Input Clocks Single Ended (K,K#) Single Ended (K,K#)

Output Clocks(C,C#) Yes No

A0 DDR B2 Yes No

Echo Clock Number 1 Pair 1 Pair Echo Clocks are Single Ended.

PKG 165 ball FBGA 165 ball FBGA

Individual Byte Write

(BWa#,BWb#)

Yes Yes

QVLD No Yes Edge Aligned with Echo Clocks

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Guide to Support QDRII/DDRII &


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Guide to Support QDRII/DDRII &QDRII+/DDRII+

QDR & DDR Pinout

P6 Design to use as C Clock or QVLD

es gn o use as oc or o onnec

DDR B2 Specific Pinout Design Controller to Always Start the Access/Burst with A0 = 0

A0 Becomes a No Connect with DDRII+

I/O Voltage

Use 1.5V HSTL I/OHost Design

Design to Support 1.5, 2.0 and 2.5 Cycles for Read Latencies

Write Latency Remains 1.0 Cycle for QDRII & QDRII+

Recommend to use Echo Clocks to Latch Read Data

Board Design

Design to Take Advantage of QValid Output

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Analyze Timing up to 400MHz

QDRII ( 18) Pi t Diff


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QDRII+ (x18) Pinout Differences

QDRII - B4

QDRII+ - B4

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DDRII ( 18) Pi t Diff


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DDRII+ (x18) Pinout Differences

DDRII - B2

DDRII+ - B2

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Architecture Comparison


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p

Parameter Std. Sync NoBLTM,DDR / DDR-

II/DDRII+

QDRTM / QDRTM-II/

QDRTM-II+

ata ate ng e ng e ou e ou e

Data Bus Common I/O Common I/O Common I/O* &Separate I/O**

Separate I/O

Data Bus

Utilization

NOP between

reads & writes100%***

reads* / 50% of

Separate I/Os**

100% reading &

100% writing

VDD 3.3V / 2.5V 3.3V / 2.5V 2.5V / 1.8V 2.5V / 1.8V

VDDQLVTTL

3.3V / 2.5V

LVTTL

3.3V / 2.5V / 1.8V

HSTL

(1.5V / 1.8V)

HSTL

(1.5V / 1.8V)

Clock

Fre uenc250 MHz 250 MHz

200 MHz /

300 MHz/400MHz

200 MHz /

300 MHz/400MHz

* DDR & DDR-II CIO have a common bus and require 1-2 NOP(s) between reads and writes.

** DDR-II SIO has separate input and output buses. Because only one bus can be used at a time, bus

utilization is exactl 50%.

63

*** Applies to clock frequency < 166 MHz. Clock frequencies above this typically requires an NOP.

sync sram1 tr

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