synopsys synthesis overview -...

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Graduate Institute of Electronics Engineering, NTU

SynopsysSynopsys Synthesis OverviewSynthesis Overview

Lecturer: 沈文中Date: 2005.05.06


pp. 2Synopsys Synthesis 2005.05.06

OutlineOutlinevIntroductionvSynopsys Graphical EnvironmentvSetting Design EnvironmentvSetting Design ConstraintsvDesign OptimizationvFinite State Machine OptimizationvSynthesis Report and Analysis



What is SynthesisWhat is SynthesisvSynthesis = translation + optimization



vSynthesis is Constraint DrivenvTechnology Independent



Logic Synthesis OverviewLogic Synthesis Overview



Tools We will UseTools We will Use

Enable synthesis using DesignWare libraryDesign Ware

Design for TestingDfT Compiler

Static Timing Analysis (STA) engineDesign Time

Constraint driven logic optimizerDesign Compiler

Translate Verilog descriptions into Design CompilerHDL Compiler

User Graphical Interface of synopsyssynthesis toolDesign Vision

PurposeTool



Design VisionDesign Vision



HDL CompilerHDL Compiler

always @(reset or set)begin : direct_set_resetif (reset)

y=1'b0;else if (set)

y=1'b1;endalways @(gate or reset)if (reset)t=1'b0;

else if (gate)t=d;

HDL Comipler

HDL Compiler translatesVerilog HDL descriptionsinto Design Compiler asSynopsys design block



HDL CompilerHDL Compilerv In schematic view, we can see the Verilog file is translated with

a GTECH library (the synopsys default)



Design CompilerDesign Compilerv Design Compiler maps Synopsys design block to gate level

design with a user specified library

TechnologyLibrary



Design Compiler InteractionDesign Compiler Interactionv Three ways to interface

DesignCompiler

(DC)

dc_shell(Legacy Interface)

dc_shell –t(TCL Interface)

Design Vision(GUI)

dv –dcsh_mode

dv

dc_shell

Command line



SynopsysSynopsys Related FilesRelated Files

v Notev These 3 files are always read in the same order.v Any repeated command can override the previous one.

Set path and environment variables and license check.cshrc

Three distinct files are read and executed when DC is invoked1. system-wide (do not modify):

(e.g. $SYNOPSYS/admin/setup/)2. User’s home directory (e.g. ~think/)3. User’s current working directory (e.g. ~think/dv/)

.synopsys_dc.setup

Set X terminal display variables.Xdefault

PurposeFiles



SynopsysSynopsys OnOn--Line Documentation (SOLD)Line Documentation (SOLD)v Invoke Synopsys On-Line Document using the commandv unix%> acroread /usr/synopsys/sold/cur/top.pdf

v Note: whenever you find a question, check SOLD first



What .What .synopsys_dc.setupsynopsys_dc.setup defineddefinedv link_library: the library used for interpreting input

descriptionv Any cells instantiated in your HDL codevWire Load or Operating Condition models used during

synthesisv target_library: the ASIC technology that the design is

mapped tov symbol_library: used during schematic generationv search_path: the path to search for unsolved

reference library or designv synthetic_library: designware library to be usedv Other variables



..synopsys_dc.setupsynopsys_dc.setup filefilev In CIC cell_based flow, we support compass 0.35um

cell library, the .synopsys_dc.setup file is as follows

search_path ={. /your_path/CIC_CBDK35_V3/Synopsys}+search_path;link_library = {“*”, “cb35os142.db”, “dw_foundation.sldb”} ;target_library = {cb35os142.db};symbol_library ={generic.sdb} ;synthetic_library ={“dw_foundation.sldb”};

hdlin_translate_off_skip_text = "TRUE"edifout_netlist_only = "TRUE"verilogout_no_tri = true ;plot_command = "lpr -Plp" ;\view_script_submenu_items = \{"Avoid assign statement", "set_fix_multiple_port_nets -all -buffer_constant",\"Change Naming Rule", "change_names -rule verilog -hierarchy", \"Write SDF", "write_sdf -version 1.0 -context verilog chip.sdf"}



Synthesis Design FlowSynthesis Design FlowSpecification

RTL Coding Prepare

Setting Design Environment

Setting Design Constraint

Compile Design

Analysis

CellLibrary

Gate-level Netlist

v Develop the HDL design description and simulate the design description to verify that it is correct.

v Set up the .synopsys_dc.setup file.v Set the appropriate technology,

synthetic, and symbol libraries, target libraries, and link libraries.

v Set the necessary compilation options, including options to read in the input files and specify the output formats.

v Read the HDL design description.v Define the design.

v Set design attributesv Define environmental conditionsv Set design rulesv Set realistic constraints (timing and

area goals)v Determine a compile methodology

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SynopsysSynopsys Graphical EnvironmentGraphical Environment



Invoke Design VisionInvoke Design Visionv Unix%> dv &

dc_shellcommand



Optimization Using the Design VisionOptimization Using the Design VisionvFile/Analyze & File/Elaborate - Verilog &VHDL,

or File/Read - all other formatsvAttributes - set up Design Environment &

GoalsvAnalysis/Report - check if set up is OKvAnalysis/Check DesignvTools/Design OptimizationvAnalysis/ReportvFile/Save



Analyze & ElaborateAnalyze & ElaboratevUse analyze and elaborate to bring Verilog or

VHDL files into design compiler memoryvAnalyze does syntax checking and produces

an intermediate .syn .mra files to be stored in a design libraryvElaborate looks in the design library for

the .syn file and builds the design up into design compiler memory (as design block)



AnalyzeAnalyzev Check VHDL & Verilog for

syntax and synthesizabilityv Create intermediate .syn

and .mra files and places them in library specified –design library

v Equivalent to dc_shell command

File/Analyze

analyze -format verilog –library WORK counter.v



ElaborateElaboratev Elaborate after analyze to

bring design into Design Compiler memory using generic components (GTECH)

v Look in the design library for intermediate .syn file for design specified

v Equivalent dc_shell commandelaborate counter -architecture verilog -library WORK -update

File/Elaborate



Read FileRead Filev Read netlists or other design

descriptions into Design Compiler

v File/Readv Support many different formats:

v synopsys internal formatsDB(binary): .dbequation: .eqn

v state table: .stv Verilog: .vv VHDL: .vhdv PLA(Berkeley Espresso): .plav EDIF



Four Types of IconFour Types of Icon

v EQUATIONv Equation, or non-netlist VHDL or Verilog format

v PLAv Programmable logic array format

v FSMv Finite-state-machine design represented as a state table

v NETLISTv Design was read in as a netlist (including structural VHDL

and Verilog ), or it has been optimized



Describe the Design EnvironmentDescribe the Design Environmentv You can use Design Vision to constrain your design



Compile the DesignCompile the Designv The compile command optimizes and maps the current_design



Report the DesignReport the Designv From report and analysis, you can find the set attributes and the

results after optimization



Save the DesignSave the Designv Write out the design netlist after synthesis



Link DesignLink DesignvAnalysis/Link DesignvExecute link -all before you optimize your

designvTo ensure all sub-elements of your

hierarchical design are available



Check DesignCheck DesignvAnalysis/Check DesignvExecute check_design before you optimize

your designvTwo types of messages are issuedverrorvError: In design ‘bcd7segs’, cell ‘decoder’ has

more pins than it’s reference ‘d1’ has portsvwarningsvWarning: In design ‘converter’, port ‘A’ is not

connected to any nets



Different View Different View -- Design ViewDesign View

HierarchySchematicSymbol

ViewIndicator

CurrentDesignIndicator

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Design Constraints SettingsDesign Constraints Settings

vSetting Design EnvironmentvSetting Design Constraint

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Setting Design EnvironmentSetting Design Environment



Design ObjectsDesign Objectsv Seven Types of Design Objects:

v Design: A circuit that performs one or more logical functions

v Cell: An instance of a design or library primitive within a design

v Reference: The name of the original design that a cell instance “points to”

v Port: The input or output of a designv Pin: The input or output of a cellv Net: The wire that connects ports to pins and/or pins to

each otherv Clock: A timing reference object in DC memory which

describes a waveform for timing analysis



Design Objects Design Objects (Schematic Perspective)(Schematic Perspective)



Design Objects Design Objects (Verilog Perspective)(Verilog Perspective)



Design Objects ExerciseDesign Objects Exercise

v Make a list of all the ports in the design?{ A, B, CLK, SUM }v Make a list of all the cells that have the letter “U” in their name?

{ADDER/U1, DFF/U2 }v Make a list of all the nets ending with “CLK”? {CLK }v Make a list of all the “Q” pins in the design? {U2/Q}v Make a list of all the references? {ADDER,DFF }



Partitioning for SynthesisPartitioning for Synthesisv Register at hierarchical output, keep related

combinational logic together at the same modulev Separate modules having different design goalsv Avoid asynchronous logic, false path, and multi-cycle

pathv Avoid the glue logicv Keep major blocks separatev Additional Issues



Register at Hierarchical OutputRegister at Hierarchical OutputvKeep related combination logic in a single

module.vRegister all at output make input data arrival

time and output drive strength predictable.



Partition by Design GoalsPartition by Design GoalsvOptimize the critical path logic for speedvOptimize non-critical path logic for area.



Avoid NonAvoid Non--normal Pathsnormal Pathsv Asynchronous logic is more difficult to design

correctly and verify.v Isolating the asynchronous logic in a separate

module.v False path and multi-cycle paths easily cause the

human error.v If false and multi-cycle paths required, use

set_false_path and set_multicycle_path command to identify.



Avoid Glue LogicAvoid Glue LogicvNo Cells except at leaf levels of hierarchyvAny extra gates should be grouped into a

sub-design



Why Describes the Real World Why Describes the Real World EnvironmentEnvironment

v Beware that the defaults are not realistic conditions.v Input drive is not infinitev Capacitive loading is usually not zerov Consider process, temperature, and voltage variation

v The operating environment affects the components selected from target library and timing through your design.

v The real world environment you define describes the conditions that the circuit will operate within.



Describing Design EnvironmentDescribing Design Environment



Setting Operating EnvironmentSetting Operating Environmentv Attributes/Operating Environment



Setting Operating ConditionSetting Operating Conditionv Attributes/Operating Environment/Operating Condition

v dc_shell> set_operating_conditions “slow”



Operating ConditionOperating Conditionv Operating condition model scales components delay,

directs the optimizer to simulate variations in process, temperature, and voltage.



Input Drive ImpedanceInput Drive ImpedancevTdelay = T0 + Ac *CloadvT0 : cell pin to pin intrinsic delayvAc : drive impedance (unit: ns/pf)



Setting Input Drive ImpedanceSetting Input Drive Impedancev Attribute/Operating

Environment/Drive Strength



Setting Input Drive ImpedanceSetting Input Drive Impedancev Also can be set using

“drive_of” commandv Example: (P2A cell output)



Setting Output LoadingSetting Output Loadingv Attribute/Operating Environment/Load



Setting Output LoadingSetting Output Loadingv Also can be set using load_of:v Example: (bufferd1 cell input)



Port ReportPort Reportv dc_shell command

v dc_shell> report_port -verbose {port_list }

v or in the option menu set verbose



Drive Strength & Load for PadsDrive Strength & Load for Padsv How do you specify the Drive Strength & Output Load for the

pins which connect to pads ?v Example:

v In CIC’s cell_based design flow, we use the Avant! 0.35um cell library. In this library we can find a file named “ds_cb35io122.pdf” , andin this file we can find the information for the pads you want to use.

1. Based on the information, set the input drive strength & output load.

2. Or extract the pad boundary condition by using characterize command, we’ll introduce it later.



Drive Strength & Load for PadsDrive Strength & Load for Padsv Input Drive Strength for Pads

v Output Load for Pads

“ds_cb35io122.pdf”



Setting the Setting the FanoutFanout LoadLoadv Use fanout_load to regulate max_fanoutv Syntax: set_fanout_load fanout portlist (for listed output ports)v Design Rule: external fanout_load + internal fanout_load must

be smaller than max_fanout_loadv “OUT”has external fanout_load 4.5 (1.5 x 3)v “OUT”has external capacitance 6 (2 x 3)v “OUT”has the number of fanout 3 (3 buffers)



Setting Wire Load ModelSetting Wire Load Modelv Wire load model estimates wire capacitance based on chip area & cell

fanoutv Setting this information during compile in order to model the design

more accuratelyv Attributes/Operating Environment/Wire Load



Setting Wire Load Model (cont.)Setting Wire Load Model (cont.)

v Syntax: set_wire_load wire_load_name –mode modev Use –mode option, you can specify which wire load model

to use for nets that cross hierarchical boundaries.

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Setting Design ConstraintsSetting Design Constraints



Delay ConstraintsDelay Constraintsv For combinational circuits

primarilyv Select the start & end points

of the timing pathv Attributes/Optimization

Constraints/Timing Constraints

set_max_delay 10 -from clock -to counter



Specify Clock Constrains Specify Clock Constrains v Select clock portv Attributes/Clocks/Specify v creat_clock : define your clock’s

waveform & respect the set-up time requirements of all clocked flip-flopsv creat_clock “clk”-period 50 -

waveform {0 25}v set_fix_hold : respect the hold time

requirement of all clocked flip-flopsv set_fix_hold clk

v set_dont_touch_network : do not re-buffer the clock networkv set_dont_touch_network clk



Sequential CircuitSequential Circuitv Sequential circuits are usually constrained by clock specifyv clock cycle >= DFFclk-Qdelay + combinational delay + DFFsetup



Input Delay ModelInput Delay Modelv Clock cycle >= DFFclk-Qdelay + a + b + DFFsetupv Input delay = DFFclk-Qdelay + a



Setting Input DelaySetting Input Delayv Select input portsv Attributes/Operating Environment/Input Delay



Output Delay ModelOutput Delay Modelv clock cycle >= DFFclk-Qdelay + d + e + DFFsetupv Output delay = e + DFFsetup



Setting Output DelaySetting Output Delayv Select output portsv Attributes/Operating Environment/Output Delay



What Have We Modeled ?What Have We Modeled ?



Design Rule ConstraintsDesign Rule ConstraintsvDesign rules can’t be violated at any cost,

even if it will violate the timing and area goal.vThree kinds of design rule constraint are set:vset_max_transitionvset_max_fanoutvset_max_capacitance



Setting Area ConstraintSetting Area Constraintv Attributes/OptimizationConstraints/Design Constraintsv Area Unit : gates



False PathFalse Pathv A false path is a timing path that cannot propagate a signal, or a path

we wish to ignore timing constraints.v The set_false_path can be used to disable timing-based synthesis on a

path-by-path basisv It is useful for:

v Constraining asynchronous pathsv Constraining logically false paths



MulticycleMulticycle PathPath

v To define setup multiplier 2 for the path from FF1 to FF2 but maintain a hold multiplier 0, use command:

set_multicycle_path 2 -from FF1 -to FF2



Constraints PriorityConstraints PriorityvDuring the optimization, there exists a

constraint priority relationship.vDesign Rule Constraint (max_transition,

max_fanout, max_capacitance)vTiming constraint (max_delay, min_delay)vPower constraintvArea constraint

vUse set_cost_priority command to modify the ordervset_cost_priority [ -default] [-delay] [cost_list]



Check DesignCheck DesignvAfter you set up the deign attributes & design

constraints, we recommend the next step is to check designvAnalysis/Check DesignvHow to handle ?vdont_touchvungroupvuniquify



dont_touchdont_touchv Proceduresv Constrain the blockv Compile the blockv Select the multiple

design instances blockv Attributes/Optimization

Directives/Design & set the Don’t Touch button

v Compile the whole design using hierarchy compile



UngroupUngroupv Proceduresv Select the multiple design

instances blockv Attributes/Optimization

Directives/Design & set the Ungroup button

v Compile whole design using hierarchy compile

v Remove a single level of hierarchy

v Does not preserve the hierarchy

v Take more memoryv Take more compile time



UniquifyUniquify

v Create a unique design file for each instance

v May select one cell or entire design hierarchy to be uniquify

v Allow design to be customized to its interface

v If the environment varies significantly, use uniquify rather than compile+dont_touch

v Uniquify uses more memory and cause longer compile time than compile+dont_touch

v Select the most top design of the hierarchy

v Edit/Uniquify/Hierarchy



Check Constraints & AttributesCheck Constraints & Attributesv Use the following reports to check constraints & attributes

before compilingv Analysis/Report



Save Constraints & AttributesSave Constraints & AttributesvSave attributes & constraints setting as the

design setup file in dc_shell command format, use File/Save Info/Design Setup



Execute Script FileExecute Script FilevExecute dc_shell command script file, use

Setup/Execute Script

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Synthesis Report and AnalysisSynthesis Report and Analysis



ReportReportv Analysis/Reportv From report and analysis, you can find the set attributes and

the results after optimization

v Attribute reportsv All attributes, clock, port,

design, net

v Analysis reportsv Area, hierarchy, constraints,

timing, point timing



Timing ReportTiming Report



Analyze Circuit with SchematicAnalyze Circuit with Schematicv To determine the time the signal arrived at pin which is selected

in the schematicv Analysis/Show Timing



Analyze Circuit with SchematicAnalyze Circuit with Schematicv To determine the net load which selected in the schematicv Analysis/Show Net Load



Save DesignSave Designv Save your design in verilog format, run Verilog gate-level simulation,

and we will use Verilog In interface to translate it into OPUS database for place & route

v If you can’t Verilog In, please check assign problemv if there is any assignment problem, choose the block & use the

dc_shell command as follow to fix itv set_fix_multiple_port_nets -all -buffer_constantsv compile -map_effort medium



GateGate--Level Simulation (Verilog)Level Simulation (Verilog)v Write out gate-level netlistv File/Save As è Verilog (for File format)v dc_shell> write -format verilog –hierarchy -output chip.vg

v Get SDFv File/Save Info è Design timing è Select chip.sdfv dc_shell> write_sdf –version 1.0 -context verilog chip.sdf

v Modify your testbench file$sdf_annotate (“the_SDF_file_name”, top_module_instance_name);

v Simulation using Verilog-XL>> Verilog chip.vg testbench.v –v cell_model.v

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