SystemC and Behavior Coding Alan P. Su, Ph.D. alansuphd@gmail.com

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SystemC 2.3, IEEE 1666-2011

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Chapter Chapter Chapter Chapter Chapter

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SystemC Overview Module, Signal, Port & Blockingness Processes, Interface & Channel Data Types Fixed Point Types

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Learn how to code in SystemC Understand the SystemC simulation mechanism, thus understand how to verify a SystemC design Familiar with SystemC basic data types Levels of abstraction: system level, transaction level, cycle-accurate, behavior level and RTL Using High Level Synthesis

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Accellera is an independent not-for-profit standard organization. It is the home of Verilog, SystemVerilog & SystemC. Among which SystemC is an open source standard for system-level design Where is Accellera http://www.accellera.org/home/

Until March 2013

the latest version is SystemC 2.3 (IEEE 1666-2011)

http://www.accellera.org/downloads/standards/sy stemc5

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The dream to realize the unison of HW/SW designing languages. A unified design environment. Version 1: it is just another HDL, not much to do with system-level designing Version 2: with the adding of channel, now it is a serious system-level language Version 2.1: adding some programming language features and simulation semantics, e.g. sc_spawn, before_end_of_elaboration, etc. IEEE approved OSCI SystemC 2.1 as the IEEE 1666 Standard on 12/12/2005 SystemC 2.2 is some enhancements and bug fixes of 2.1 IEEE 1666-2011, aka SystemC 2.3, adding TLM 2.0 and some process control syntax

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Is a C++ class library and a methodology that one can use to effectively create cycle-accurate models of functions, hardware architecture, and interfaces of the SoC and system-level designs. One can use SystemC and standard C++ development tools to create a systemlevel model, quickly simulate to validate and optimize the design, explore various algorithms, and provide the hardware and software development team with an executable specification of the system.

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Modules: component Processes: functions, SC_THREAD & SC_METHOD Ports: I/O ports Signals: wires Rich set of port and signal types Rich set of data types Clocks Cycle-based simulation: ultra light-weight and fast Multiple abstraction levels Communication protocols: channel & interface Debugging support: runtime error checking Waveform tracing: VCD, WIF and ISDB formats

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C, C++ System-level Modeling

Done Verilog/VHDL

Refine

Simulation & Analysis Simulation

Results Synthesis

To tape out, test and product delivery10

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Methodology-Specific LibrariesMaster/Slave Library, etc.

Layered LibrariesVerification Library, TLM 2.0 Library, etc.

Signal, Mutex, Semaphore, FIFO, etc.

Primitive Channels

Core LanguageModules Ports Interfaces Channels

4-valued Logic Type 4-valued Logic Vectors Bits and Bit Vectors Arbitrary Precision Integers Fixed-Point Types Events, Processes

Data Types

Event-Driven Simulation

C++ Language Standards

SystemC is a set of C++ class definitions and a methodology for using these classes. C++ class definition means systemc.h and the matching library. Methodology means the use of simulation kernel and modeling. You can use all of the C++ syntax, semantics, run time library, STL and such. However you need to follow SystemC methodology closely to make sure the simulation executes correctly.

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SystemC is a Hardware Description Language (HDL) from system-level down to gate level. Modules written in traditional HDLs like Verilog and VHDL can be translated into SystemC, but not vise versa. Reason: Verilog and VHDL do not support transaction-level. System-Verilog is Verilog plus assertion, which is an idea borrowed from programming languages. And SystemC supports assertion as well through the C++ syntax and semantics.13

SystemVerilog is Verilog plus verification (assertion). Actually the above statement is not fair but it is the truth now. SystemVerilog and SystemC work together to complete the design platform from system-level to gate-level. SystemC deals with whatever above RTL. SystemVerilog deals with RTL and below.

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Methodology

It is a language to unify the design environment, SW and HW. A unified design environment. Well, this is a dream in the academy. In industry, this is a long way to go and as of today, SystemC is not the answer. Notice, SystemC is an HDL, it itself does not support software performance measure mechanism. Will the day that an unified design language be realized? We just dont know. But people are talking about UML, the Unified Modeling Language.16

SystemC does not model software. It is an HDL. Period.17

SystemC does not run faster, higher abstraction level does.18

To be categorized as a system-level language, the simulation SPEED is the key. The simulation speed should take no 1,000 time slower than the real HW. In another word, 1 second of HW execution time equals 16 minutes and 40 seconds simulation time To achieve this kind of performance, the system is best modeled in transaction level, e.g. token based

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A module is the basic structural building block in SystemC, the same as Verilog module. It may contain Ports for communication Data members Channel members Processes Member functions not registered as processes Instances of other modules

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Derived from class sc_module: class my_module : public sc_module { }; A more commonly used way: SC_MODULE (module_name) { // ports, sc_export, data members, member functions // processes, etc. SC_CTOR(module_name) { // constructur // body of constructor // process registration, sensitivity lists // module instantiations, port binding etc. } }; // do not forget this final ; SC_MODULE is a macro: #define SC_MODULE(user_module_name) \ struct user_module_name : sc_module

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sc_in; //input port sc_out; //output port sc_inout; //in/out port If data_type is a type with size declaration, a space is needed before the closing bracket, e.g.

sc_in;

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Using HW port-to-port binding is not intuitive at system-level and slow. Starting 2.1 SC_EXPORT is supported for light weight binding. Vastly used in the TLM library. People say at transaction level SC_EXPORT must be used. The purpose is to speed up the simulation.

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Is a un-directional wire when connects to ports The flow of data is determined by the ports a signal connects to Example:

sc_signal w1;

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Non-blocking descriptor Example:

sc_signal reg1; Reg1 = 3;

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An assignment statement has two sides, Right-Hand-Side (LHS) and Left-Hand-Side (LHS) A = 5 + 3;

Evaluate: the execution of the RHS expression 5+38

Update: update the LHS expression A8

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Evaluate and update immediately and in one step/statement// a == b = a; c = b; a = c; 3, // // // b b c a == is is is 4, c == 5 now 3 now 3 3, again

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Two steps Evaluate first and immediately, and update occurs when all evaluations at current time step are completed// a == b = a; c = b; a = c; Wait(); 3, // // // b b c a == is is is 4, c == 5 still 4 still 5 still 3

// b is updated as 3 // c is updated as 4 // a is updated as 529

sc_uint ary[8] = {1,2,3,4,5,6,7,8}; for (i=0; idout ( s ); c1 = new coeff(c1); c1->out ( c ); m1 = new mult(m1); m1->a ( s ); m1->b ( c ); m1->q ( q ); } };

c1

s1

m1

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Positional Mapping is no longer supported in 2.2#include systemc.h #include mult.h #include coeff.h #include sample.h SC_MODULE(filter) { sample *s1; coeff *c1; mult *m1; sc_signal q, s, c; SC_CTOR(filter) { s1 = new sample(s1); (*s1) ( q,s ); // 2.2 illegal c1 = new coeff(c1); (*c1) ( c ); // 2.2 illegal m1 = new mult(m1); (*m1) ( s, c, q ); // 2.2 illegal } };

c1

s1

m1

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Processes are the basic unit of execution within SystemC. Processes are called to emulate the behavior of the target device or system. The real work of a module is performed in processes. Processes are functions that are identified to the SystemC kernel and called/activated whenever signals these processes are sensitive to. These statements are executed sequentially until the end of the process, or being suspended by a wait() statement. SC_METHOD, SC_THREAD, SC_CTHREAD

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#include systemc.h SC_MODULE(timer) { sc_inout start; sc_out timeout; sc_in clock; int count; void runtimer(); SC_CTOR(timer) { SC_THREAD(runtimer); sensitive