tektronix innovation forum · centers and communications networks ask for more bandwidth • sas...

Tektronix Innovation ForumEnabling Innovation in the Digital Age

Presenter: Xin Zhang

泰克最新高速信号完整性测试--涵盖收发端及链路的完整解决方案

2

High-Speed Serial TestTrends and Implications

• 100 GbE is becoming more relevant as data centers and communications networks ask for more bandwidth

• SAS 12G is needed by data centers for efficient transport of internet traffic (YouTube, Facebook, Smart Phone, etc)

• High-Speed FPGA’s are increasing in complexity to support early designs above 20Gb/sec

• Proliferation of 10+ Gb/sec signaling in the communications network

Industry/Technology Trends

• Closed data eyes requiring new techniques for transmitter and receiver equalization

• Higher data rate signals have less margin –requires de-embedding

• Edge/Slew rate speeds are difficult to characterize

• New Jitter Separation Measurements are required

• Complex 8b/10b signaling difficult to verify in PHY

Implications

2011-Tektronix Innovation Forum

高速串行设计、测试挑战

设计检验一致性测试

Simulation Signal IntegrityEye and Jitter Analysis

Characterization & Validation

System IntegrationDigital Validation & Debug

Serial Data Network & Link Analysis

Data Link Analysis

Digital validation & Debug

Compliance Testing

Receiver TestDirect Synthesis

Transaction Layer

Data Link Layer

Ph

ysic

al L

ayer

LogicalSub-block

ElectricalSub-block

路径Tx +

-

+

-

+

-

+

-

Rx

仿真信号完整性眼图和抖动分析

检定和验证

系统集成数字验证和调试

串行数据网络和链路分析

数据链路分析数字验证和调试

一致性测试

接收机测

事务层

数据链路层

逻辑子块

电气子块

3 2011-Tektronix Innovation Forum

完善的泰克串行数据测试解决方案

HO

ST

端口

发射机 / 接收机

Dev

ice

端口

发射机 / 接收机

Lane

链路

RefClk

实时频谱分析仪

PLL环路带宽信号互连测试

DSA8200采样示波器TDR模块S参数测量模型提取建模

数字验证和调试协议测试

Intel最佳测试平台TLA逻辑协议分析仪

DPO/DSA/MSO70000C4Ch实时示波器20GHz带宽100GS/s采样率DPOJET平台化测试软件

Tx信号质量, 参考时钟和一致性测试

Rx容限测试

BERTSCope最高26Gbps误码测试能力具有丰富系统调试功能


高速串行信号测试挑战

8Gbps速率的信号仍然在FR4板材上传输，势必增加更多的信道

损耗– 信号高频分量消失殆尽，影响到对示波器带宽的需求

– 由于信道损耗，上升时间没有像数据率成倍的增长

– Tx和Rx端芯片增加了更加负载的均衡处理

Tx端需要3阶的去加重(De-emphasis)以及全新的Pre-shoot Rx端需要CTLE、DFE弥补长链路的损耗

– 为了考虑到互操作性，Tx端接口一致性测试必须考虑到信号的传输通道

由于芯片的封装，通常探头无法直接探测到信号输出管脚– 使用反嵌技术(De-embedding)消除测试走线、夹具的影响

定义了很多新型的抖动测量项目– J2、J9、DDWPS、BUJ...


反嵌(De-embedding)技术

反嵌会使得高频噪声放大，因此需要带限滤波器抑制带外噪声

– 示波器带宽会影响到反嵌的效果

– 带宽限制和板材有关

成功的反嵌需要良好的电路板设计以及准确的S参数测试

– 阻抗匹配、低损耗

– 无增益、过大的谐振和陷波

5 GHz 10 GHz

5GHz Filter 10GHz Filter -> Noise amplification


反嵌必须在测量之前完成

考虑到信号走线、互联，仿真到达接收端的信号

仿真接收端均衡，得到芯片内部真实信号的特性

对信号进行抖动、眼图测试

分离抖动类型，提出优化意见

复杂的Tx端信号测量

Signal at TX Pins Measured Signalat TP1

Apply Sparameters Signal with ChannelEffects Removed


Link Analysis-Embed/De-embed and EQ Post processing is required on most signals before

measurements are performed– Compliance Channels are embedded and eye is opened with a reference

equalizer as defined in the specification

Virtual probe access at intermediate test points is critical forsystem visibility

– Visually see and measure the effects of de-embedding, embedding, and equalization


9

Transmitter Jitter Measurements

Necessary to take transmitter jitter measurements with all lanesoperating in order to capture crosstalk effects

Measurements are taken at TP1 and de-embedded back to the pins of the TX

Necessary to separate uncorrelated and data dependent jitter in order to ensure that jitter that can be recovered is not budgeted as uncorrelated jitter

Jitter measurements Data Dependent Jitter Uncorrelated Jitter

Cause Due to package loss and reflections (dynamics in the channel, ISI)

Uncorrelated - PLL jitter, crosstalk, noise conversion (amplitude to phase)

How to compensate Can be reduced by equalization

Difficult to remove (better components, layout)


10

Transmitter Jitter Measurements: Data Dependent JitterDDJ Measurement Process Measurement taken on multiple repeats of the compliance pattern using a 1st

order CDR function representing a high pass filter

A PDF is created for each edge crossing of the compliance pattern

DDJ is calculated as the difference of the mean of each PDF and the recovered clock edge

Measurement is defined as the absolute value of DDJ(max) – DDJ(min)


11

Uncorrelated Jitter ExampleTTX-UTJ / TTX-UDJDD

• DDJ is removed from the PDF of each edge

• Data is converted to Q-Scale

• Uncorrelated Deterministic Jitter Dual Dirac (UDJDD)

– Accounts for Periodic Jitter and Crosstalk Convert the PDF to Q-Scale

• Random Jitter is implied by subtracting UDJDD from UTJ


New Jitter Separation Measurements Next Generation Standards require separate jitter budgets for Data

Dependent(DDJ) and Uncorrelated Jitter– TX and RX Equalization only compensate for DDJ

Crosstalk is a key contributor to Bounded Uncorrelated Jitter (BUJ) and is worse in multi-lane topologies

– BUJ, if counted as RJ will artificially inflate TJ – NEW! Tektronix Sampling and Real-Time platforms provide BUJ

measurements which provides more accurate jitter separation to support next generation standards

12 2011-Tektronix Innovation Forum12

Jitter Analysis AdvancesBUJ in Thunderbolt example

Tektronix Technology Innovation Forum 2011

Cloud Computing

TJ@BER1, Math1 10.105psRJ1, Math1 506.04fsPJ1, Math1 3.6968psDJ1, Math1 3.6968psNPJ1, Math1 881.89fsTIE2, Math1 55.789fsRise Slew Rate1, Math1 9.2627V/ns

TJ@BER1, Math1 9.9087psRJ1, Math1 556.41fsPJ1, Math1 2.6685psDJ1, Math1 2.6685psNPJ1, Math1 592.92fsTIE2, Math1 89.108fsRise Slew Rate1, Math1 9.2542V/ns

TJ@BER1, Math1 10.315psRJ1, Math1 680.95fsPJ1, Math1 1.7365psDJ1, Math1 1.7365psTIE2, Math1 44.029fsRise Slew Rate1, Math1 9.3228V/ns

TJ@BER1, Math1 11.159psRJ1, Math1 694.31fsPJ1, Math1 2.8264psDJ1, Math1 2.8264psTIE2, Math1 -25.694fsRise Slew Rate1, Math1 9.2843V/ns

Legacy DecompositionNew BUJ Decomposition

13

High-speed Tx testing require PriciseClock Data Recovery

1. Clock recovery is also required for many test instruments which characterize serial data systems.– Recovering clock may be desirable even when Tx

clock is available.

2. Instruments which sample the data contiguously, such are ‘real time’ oscilloscopes, implement software based clock recovery.– Generally limited to lower data rates / limited

measurement depth.

3. Sampled data instruments require a hardware clock, derived from hardware clock recovery.– Sampling oscilloscopes – for measuring higher data

rates.– Analyzing BERTs – for greater measurement depth or

higher data rates.

4. “Instrumentation Grade” clock recovery is required.– Calibrated, repeatable, and adjustable.

Decision

CircuitData In

Clock

Regenerated Data Out

Jittered incoming data

Jittered incoming data

What does CDR really do?

Regenerated data cleaned upRegenerated data cleaned up

Recovered clock moveswith the data.Recovered clock moveswith the data.

Receiver decisions relative

Receiver decisions relative

Tracking of jitter is a key attribute of clock recovery

Tracking of jitter is a key attribute of clock recovery

1.1.

2.2.

3.3.

4.4.

5.5.

CDR effect jitter measurement dramatically

10 kHz 100 kHz 1 MHz 10 MHz

Jitter Modulation Frequency, Hz

Jitter In:Jitter In:

PLL not able to track as

effectively. Jitter seen is attenuated compared to the

input.

PLL hardly able to

track input jitter at all. Output is

stable signal.

PLL tracks data closely,

jitter on output

similar to input

RecoveredClock

Jitter Out:

RecoveredClock

Jitter Out:

0

-40

-20

-60Jitte

r Tra

nsfe

r Fun

ctio

n (d

B)

= 20

Log

(Jitt

er O

ut/ J

itter

In)

1.1.

4.4.5.5.

6.6.

2.2.3.3.

Jitter Mod. Freq., Hz

Constant Amplitude SJChange Peaking by 3 dB

In: 35ps Jitter

1.

Out: 35ps Jitter

2.

Out: 50ps Jitter

3.

The Effect of Peaking Illustrated

1 MHz loop bandwidth, 400 kHz SJ modulation

The eye diagram from the green response shows jitter gain – more jitter out of the device than was present on the input.

The eye diagram from the green response shows jitter gain – more jitter out of the device than was present on the input. 4.4.

The Effect of Edge Density

1. Different data patterns have different “edge density” or “transition density”.– A 1010 clock pattern has a 100 % edge

density.– A true PRBS pattern has a 50 % edge density.

LBW2. The pattern’s edge density effects the

energy entering the PLL phase detector, which affects the loop response, loop bandwidth.

3. The calibration of loop response requires knowledge of the edge density.

Measurements: “Instrumentation Grade” Clock Recovery Units

1. Clock Recovery loop response affects the amount of jitter “seen” by serial data analysis instruments.– Loop bandwidth– Roll off slope– Peaking

2. The parameters must be tightly controlled for accurate and repeatable jitter measurements.

3. The ability to adjust these parameters is often required.– CR characteristics are often dictated by many Compliance Test

Standards.– Setting the parameters to match those in receiver allows the instrument

to “see” the data as receiver does in the real system.

Visual Trigger and Serial Decode

Next generation designs have less margin and additional analysis must be done to pinpoint in on pattern dependent issues

– NEW! Visual Trigger qualifies hard to define trigger events 8 customizable shapes for capture of real

signal behaviors

Electrical and Logic layer are merging and requires simultaneous analog and protocol views

– NEW! 8b/10b Serial Decode Trigger or Search on decoded traffic Compare to analog views to speed up time to

answer

2011-Tektronix Innovation Forum20

High Speed Device connectivity Solder-Down probing is required when a signal needs

to be measured and no SMA or RF connector is available

High Speed standards like PCI Express are commonly seen in embedded designs

Debugging often requires signal access as close to the TX and RX as possible

TriMode probing enables simultaneous access of single ended and differential signals– No need to re-solder probe tips to switch between

measurements (i.e. common mode measurements)

World’s Highest Performing Solution For Next Generation Serial Technologies21 2011-Tektronix Innovation Forum

信号产生

高速串行信号不断增加的数据率

不断增加的信号带宽

复现现实世界中的信号

复现传输线效应

产生各种干扰信号：抖动、噪声和其他干扰，并精确的知道干扰量的大小

高速串行系统Rx端容限测试

pathTx +

-

+

-

+

-

+

-

Rcv

单纯考察Tx端是不足以保证BER

Rx端复杂的结构：Equalizer、CDR

没有Tx和传输链路时对Rx的压力测试

对Rx端施加各种各样的压力和一致性测试信号


Why Receiver Testing is Different

ReceiverBright…Bright… Shiny…Shiny…

New…New…

“Receiver”, “Re-Timer”“Decision Circuit”, “SERDES”

Poor quality bits in…. Pristine bits out…..

• Transmitters are tested with eye diagram analysis but a Receiver Changes Everything

• Can no longer rely on how good the eye looks as a measure of performance….….the eye shape only tells how nice the output stage is.

Receivers are Tested with BER

Receivers

What causes “poor bits”?

无论是针对设计还是生产制造，规范都定义了明确的Rx端测

试需求

所有标准都要求进行Jitter Tolerance 一致性测试

被测设备类型:– SerDes – Transceivers – Multi Media Sink devices– Rx devices

各种高速串行总线对Rx接收端测试的要求

Standard Data Rate

Jitter Tolerance

Timing Skew

Amplitude Sensitivity Emphasis

SATA Gen 3 6 Gb/s 　　 - 　 -PCI Express 2.0 5 Gb/s 　　　　

PCI Express 3.0 8 Gb/s 　　　　

HDMI 1.40.75 Gb/s

to 3.4 Gb/s

　　　 -

FC 4, 8 G4.25 Gb/s

to 8.5 Gb/s

　　　　

DisplayPort2.7 Gb/s

5.4Gb/s 　　　　

USB 3.0 5 Gb/s 　 - 　　


各种高速串行总线对Rx接收端测试的要求

1.设置DUT进入Loopback模式(Analog/Re-timing)

2.产生规范要求的抖动分量，在不同的频点上分别产生相应的抖动量

3.将stressed信号注入DUT Rx4.统计DUT Tx端发出的信号的误码率是否达到要求

12

4

3


BERTScope产生各种压力类型

Sine jitter– 1KHz~100MHz– max.1100ps

Random jitter– f>1GHz

Bounded PRBS jitter

SSC– 12,500ppm

Sine Interference


动态改变速率、压力、码型等

6 Gb/sPRBS-7DJ:SJ:RJ:SI:



11

22

33


PCIe Gen 3 Stress Recipe - Overview

Tx Eq

8G PRBSGen

RJSource

SJSource

Combiner

DiffInterference

Cal.Channel

ReplicaChannel

Test Equipment

CMInterference

Post‐processing

Eye HeightAdjust

(Taken from PCI Express Base Spec, Figure 4‐71)

PCI Express Gen 3 uses a long circuit board channel that closes the eye, and two forms of vertical eye closure (‘Interference’).

PCI Express Gen 3 uses a long circuit board channel that closes the eye, and two forms of vertical eye closure (‘Interference’).

29

PCIe Gen 3: Example Add-In Card Stress Calibration

In Out+

‐

+

‐

To RT Scope for calibration

SI Combiner

Gen 3 CBB Riser

Gen 2 CLB

Gen 3 CBB (Main)

Rx Lane 0

Tx Lane 0

Last Cal. details being refined. This setup beingsuccessfully used at Plugfests

Last Cal. details being refined. This setup beingsuccessfully used at Plugfests

30

自动化Jitter Tolerance一致性测试方案

Test for compliance

Use Search mode to find device limits

PCIE GEN1,2,3

SATA I,II,III

USB3

Display Port

XFP/XFI

10GBase-KR

Optical

Serial Bus...


完整的高速串行系统测试、调试过程

测量BER测量BER

BER是否合格BER是否合格

测量眼图测量眼图

眼图是否闭合眼图是否闭合

测量BER等高线测量BER等高线

定位故障点定位故障点

分析误码率事件规律

分析误码率事件规律

Pattern SensitivityPattern Sensitivity

Error Free IntervalError Free Interval

BER Strip ChartBER Strip Chart

CorrelationCorrelation

PassPass

检查Tx端预加重

连接可靠增加驱动

检查Tx端预加重

连接可靠增加驱动

Y

Y

N

N

根据误码事件特点找到误码根源解决误码问题

根据误码事件特点找到误码根源解决误码问题


参考时钟泄露

多余的波形：出现的频度不高

内存芯片设计


深入调试“异常”现象

将BERTScope的采样器放置在“可疑”区域

BERTScope将统计落在采样器上的码型出现的规律– 可以使用Error Correlation

出现非常有规律的事件，间隔为“24”34 2011-Tektronix Innovation Forum

解决问题

推论：Data Rate的24 分之一为时钟的频率，因此，可以定位到

异常的眼图有可能是时钟串扰引起的。

行动：增加时钟和数据走线之间的隔离；减缓时钟的slew rate


22-SEPT-201036

全新的“逻辑协议测试”理念

示波器逻辑协议分析仪

Logic Protocol Analyzer for PCI Express 3.0Performance You Can See - One tool to span from protocol to physical

协议分析仪

Summary Profile WindowTransaction Window

? Poor physical layer support

OpenEYEFastSYNCScopePHY


22-SEPT-201037

TLA7000平台+逻辑协议分析模块

支持高速串行总线协议– PCIE Gen1/2/3– DDR2/3– USB3– SATA/SAS– Serial RapidIO– FC...

对信号模拟特性采集

– 可以无缝的和示波器联合使用

– 时间相关的模拟、数字、协议层联合测试

– 不漏失任意一个总线异常

– 直接定位故障到系统模拟层面

灵活多样的探测方式

– 焊接式、嵌入式以及自定义信号探测方式，支持最多样的总线拓扑

– 内置均衡处理模块，真实可靠反映信号模拟特征

TCA-SMA TekConnect Adapters shown connected to 1-lane (2 differential inputs) out of the 2-lanes per P67SAxxx probe connector. Unconnected lanes have 50ohm terminators connected at end of coax.

TLA70122-module

logic analyzer

mainframe2x TLA7SA16

x8 PCIe3Modules

DPO/DSA70000B

4-channel33 GHz

oscilloscopewith

DPOJETloaded withP67SAxxx

S-parameter file to

de-embed the probe

P67UHDSMA2-lane probe leadset


TEKTRONIX CONFIDENTIAL

Information Density - Transaction Window (1/3)

Packet pane to view fields (can simultaneously open multiple

packets

Toolbar(Search, filter,

display management)

Status bar &access to “Summary

Profile Window”

BEV(Bird’s Eye

View)

ConfigLinks

Transaction stitching shows

packets participating in transaction – or

incomplete transactions as errors – mouse over shows time

–arrowheads/squares filled or not

based upon completion

PHY layer info (shows sub-packet info

such as ordered sets –view in more

detail in Listing Window)

Flow control credit

tracking

Each row of the Packet View pane

represents a single packet

22-SEPT-201038 Transaction - Link based behavior of protocol elements (transactions, packets, fields, ordered sets)38 2011-Tektronix Innovation Forum

22-SEPT-201039

协议逻辑分析仪--协议层、模拟层联合观测

Waveform symbolic decode

(lane alignment

disabled for accurate time correlation)

Waveform - Time based view of the data on each lane


Tektronix高速计算机验证系统

DDR3 Validation DIMM *

PCI Express 3

DDR3 Interposer Probe *

CPU Bus

Electrical compliance test

DD

RD

DR

DD

R

IOH

CPU

DD

R

DD

R

DD

R

DD

R

DD

R

DD

R

PCIe3SATA

Other buses

* Nexus Technology and FuturePlus products available for DDR2 and DDR3 including 1600MT/s

*Courtesy of Intel.

业内性能最高的TLA7BB4 模块，轻松应对DDR3-1867逻辑协议测试

定时采样率50G/s

状态速率3GHz


Jan 2011 Tektronix最新测试测量解决方案构架

全新的信号完整性调试理念-模拟数字联合调试

TriggerState

Machine

4 ch

CH 1

CH 2

CH 3

CH 4

DPODPOLALA

Analog In

CH 1

CH 2

CH 3

CH 4

Analog Out2 GHz

AnalogMux

34 ch

34 ch

34 ch

34 ch

单LA探头连接信号，同时测量

信号模拟、逻辑特性

LA探头所有通道模拟带宽指标2~3 GHz

LA中136通道任意4路可以输出

到外部示波器

新


模拟、数字联合调试方案

毛刺捕获技术

– 实时动态监控信号中的异常逻辑

– 高亮标注

– 准确定位异常发生时刻、位置

iView– 将逻辑分析仪和示波器无缝连接

为一套测试系统

– 在逻辑分析仪屏幕上显示自动时间对齐后的同一信号模拟和数字的波形

– 通过逻辑分析仪对示波器的触发控制，准确定位信号异常时的模拟采集


数字、模拟联合调试系统

TLA Logic Analyzer P6860 Probe (34ch)

TLA BNC Cables

iCapture: 逻辑分析仪集成式数字/模拟探头

TLA iViewTLA逻辑分析仪 DPO/DSA示波器

ZhangXin,Tektronix China44

iView 外部示波器接口电缆

USB接口

USB-to-GPIB接口

连接至TLA7000逻辑分析仪连接至DPO示波器

小结

业内最丰富的针对于高速计算机系统

测试方案，从链路层、模拟层到逻辑协议层

业内最高的误码率分析仪，提供了深邃的误码率事件分析功能；一键式接收端容限测试

业内最新的“逻辑协议”分析仪，结合

了模拟层、数据层和协议层的调试、测试于一体

支持广泛的高速总线标准测试


Link Analysis Post processing is required on most signals before

measurements are performed– Compliance Channels are embedded and eye is opened with a reference

equalizer as defined in the specification

Virtual probe access at intermediate test points is critical forsystem visibility

– Visually see and measure the effects of de-embedding, embedding, and equalization


New Jitter Separation Measurements Next Generation Standards require separate jitter budgets for Data

Dependent(DDJ) and Uncorrelated Jitter– TX and RX Equalization only compensate for DDJ

Crosstalk is a key contributor to Bounded Uncorrelated Jitter (BUJ) and is worse in multi-lane topologies

– BUJ, if counted as RJ will artificially inflate TJ – NEW! Tektronix Sampling and Real-Time platforms provide BUJ

measurements which provides more accurate jitter separation to support next generation standards


Visual Trigger and Serial Decode

Next generation designs have less margin and additional analysis must be done to pinpoint in on pattern dependent issues

– NEW! Visual Trigger qualifies hard to define trigger events 8 customizable shapes for capture of real

signal behaviors

Electrical and Logic layer are merging and requires simultaneous analog and protocol views

– NEW! 8b/10b Serial Decode Trigger or Search on decoded traffic Compare to analog views to speed up time to

answer


Bandwidth Impact on Measurement Accuracy

An Example, SAS 12G

At 12G, only the entire First Harmonic is captured– Edge definition comes after the 2nd Harmonic– Resulting signal is a sine wave and results in higher TJ and an eye

height that is larger than expected when baselined with a sampling scope (470mV)



At 24G only the entire 3rd harmonic is captured– Note the peanut in the center of the eye that closes the eye– TJ is improved, but eye height is lower than the sampling scope baseline



At 33G the entire 5th harmonic is captured– TJ is reduced and eye height correlates with the sampling scope


Receiver Testing is Required for Certification

Compliance Testing is just the start of characterizing RX performance

Margin Testing can lead to insight on system margins and errors that can cause interoperability problems

BERTScope enables insight into RX failures Eye diagram for quick

diagnosis of synchronization and BER failure issues

Debug challenging signal integrity problems

Error Location Analysis

Pattern Capture

Jitter Map

BER Contour

JitterJitter

Error Correlation

Error Correlation

BERBER

Jitter DecompositionJitter Decomposition

Jitter ToleranceJitter Tolerance

PLUS…PLUS…

52

Proven Expertise in High Speed Serial Data Testing Transmitter Signal Quality

4Ch 33Ghz Real Time Oscilloscopes High Bandwidth Differential Probes Jitter and Eye Analysis Serial Data Link Analysis

Digital Validation and Debug Protocol and Logic Analyzers Protocol Debug and Validation

Receiver Testing BERTScope Bit Error Rate Teste Jitter Tolerance Test

S Parameters

Interconnect Testing DSA8300 Sampling Oscilloscopes TDR Heads TDNA SW


tektronix innovation forum · centers and communications networks ask for more bandwidth • sas...

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