to designing counters using verilog code
TRANSCRIPT
Experiment No:9 Aim: To Implement counters. NAME: Shyamveer Singh SECTION: E1207
REG N0: 11205816 ROLL NO: B-54
Truth Table: Up down counter:
Up counter:
Theory: An up counter simply counts from 0 to 9. We can use this circuit to make , This circuit can also be used to make a digital clock. Both Synchronous and Asynchronous counters are capable of counting “Up” or counting “Down”, but their is another more “Universal” type of counter that can count in both directions either Up or Down depending on the state of their input control pin and these are known as Bidirectional Counters.
Bidirectional counters, also known as a up down counter.
PROGRAMME CODES
4bit up counter: module fbuc(clk,reset,q); input clk,reset; output [3:0]q;
reg [3:0]q;
always@(clk)
begin if(reset) q=0; else if(reset==0&&q<15) q=q+1; end endmodule
reset = 1;clk = 0;
// Wait 100 ns for global reset to finish #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1;
#10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10;
// Add stimulus here
end
endmodule // Initialize Inputs
reset = 1;clk = 0;
// Wait 100 ns for global reset to finish #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10;
reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10;
// Add stimulus here
end
endmodule
4bit down counter module fbdc(clk,reset,q); input clk,reset; output [3:0]q;
reg [3:0]q;
always@(clk)
begin if(reset)
q=15;
else if(reset==0&&q>0) q=q-1; end
endmodule
reset = 1;clk = 0;
// Wait 100 ns for global reset to finish #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0;
#10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10; reset = 0;clk = 1; #10; reset = 0;clk = 0; #10;
reset = 0;clk = 1; #10;
// Add stimulus here
end
endmodule
4b Up down counter
module fbudc(clk,reset,up,dn,q); input clk,up,dn,reset; output [3:0]q; reg [3:0]q; always@(clk) begin if (reset) q=0; else if(up)
q=q+1;
else if(dn)
q=q-1; end
endmodule
clk = 0; reset = 1; up = 1; dn = 0;
// Wait 100 ns for global reset to finish #10; clk = 1; reset = 0; up = 1; dn = 0; #10; clk = 0; reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 1; dn = 0; #10; clk = 0;
reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 1; dn = 0; #10; clk = 0; reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 1; dn = 0; #10; clk = 0; reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 1; dn = 0; #10; clk = 0; reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 1; dn = 0; #10; clk = 0; reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 1; dn = 0; #10;
clk = 0; reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 1; dn = 0; #10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1; #10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1; #10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1; #10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1;
#10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1; #10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1; #10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1; #10; clk = 1; reset = 0; up = 0; dn = 1; #10; clk = 0; reset = 0; up = 0; dn = 1; #10;
// Add stimulus here
end
endmodule
