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RELE KAVS10001D155EG

RELE 25 SAC 8711

SERIAL 139293K  

SYSTEM DATA COLUMN SETTING

1 SYS DESCRIPTION SYNCH CHECK 

2 SYS PLANT REF CB

3 SYS FREQUENCY 60 HZ4 SYS COMMS LEVEL 1

5 SYS RLY ADDRESS 12

6 20001

CSS PHASE ANGLE 30!

" CSS SLIP FREQ# 100 $H%

& CSS SYNCH TIMER 200 $'()

10 CSS SPLIT ANGLE &0!

11 CSS SPLIT TIMER 100 $'()

12 CSS SYSTEM ANGLE 30!13 CSS SYSTEM SLIP 50 $HZ

14 CSS SYSTEM TIMER 1 '()

15 CSS V# B*L LIVE 106 +V

16 CSS V# B*L DEAD 53 +V

1 CSS UNDER VOLTAGE 106 +V

1" CSS DIFF# VOLTAGE 13 +V

RELE KAVS10001D155EG

RELE 25 SAC 8720

SERIAL 345894L

SYSTEM DATA COLUMN SETTING

1 SYS DESCRIPTION SYNCH CHECK 

2 SYS PLANT REF CB

3 SYS FREQUENCY 60 HZ

4 SYS COMMS LEVEL 1

5 SYS RLY ADDRESS 12

6 253

CSS PHASE ANGLE 30!

" CSS SLIP FREQ# 100 $H%

& CSS SYNCH TIMER 200 $'()

10 CSS SPLIT ANGLE &0!

11 CSS SPLIT TIMER 100 $'()

12 CSS SYSTEM ANGLE 30!

13 CSS SYSTEM SLIP 50 $HZ

14 CSS SYSTEM TIMER 1 '()

15 CSS V# B*L LIVE 106 +V

CHECK SYNCHRINISM SETTINGSCSS VT RATIO

CHECK SYNCHRINISM SETTINGSCSS VT RATIO

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16 CSS V# B*L DEAD 53 +V

1 CSS UNDER VOLTAGE 106 +V

1" CSS DIFF# VOLTAGE 13 +V

RELE KAVS10001D155EG

RELE 25 SAC 8730SERIAL 139292K  

SYSTEM DATA COLUMN SETTING

1 SYS DESCRIPTION SYNCH CHECK 

2 SYS PLANT REF CB

3 SYS FREQUENCY 60 HZ

4 SYS COMMS LEVEL 1

5 SYS RLY ADDRESS 12

6 10

CSS PHASE ANGLE 30!" CSS SLIP FREQ# 100 $H%

& CSS SYNCH TIMER 200 $'()

10 CSS SPLIT ANGLE &0!

11 CSS SPLIT TIMER 100 $'()

12 CSS SYSTEM ANGLE 30!

13 CSS SYSTEM SLIP 50 $HZ

14 CSS SYSTEM TIMER 1 '()

15 CSS V# B*L LIVE 106 +V

16 CSS V# B*L DEAD 53 +V

1 CSS UNDER VOLTAGE 106 +V

1" CSS DIFF# VOLTAGE 13 +V

CHECK SYNCHRINISM SETTINGSCSS VT RATIO

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I OPTO INPUT NUMBER

A INP START CHSYN

B INP START SYSSYN

C INP INH DLLB*CHSD INP INH LLDB*CHS

E INP INH DLDB*CHS

F INP INH DLLB*SYS

G INP INH LLDB*SYS

H INP INH DLDB*SYS

I INP INH SYSPLIT

II RELAY MASK SETTINGS,KAVS 100

RELAY NUMBERA RLY START SYNCH

B RLY CHECK SYN OK  

C RLY CHECK SYN OK  

D RLY D#LINE*L#BUS

E RLY L#LINE D#BUS

F RLY D#LINE*D#BUS

G RLY UNDERVOLTAGE

H RLY DIFF VOLTAGE

I RLY SYSTEM SPLIT

 - RLY DLLB*CHSYN

K RLY LLDB*CHSYN

L RLY DLDB*CHSYN

M RLY DLLB*SYSSYN

N SLY LLDB*SYSSYN

O RLY DLDB*SYSSYN

LOGIC FUNTIONS

SCHEME FN# LINKS 1 .3/

LOGIC INPUT STATUS

LOGIC OUTPUT STATUS

LOGIC DEFAULT DI L(

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LOGIC ROTATION EVERY 5 SECONDS

LOGIC TEST REALY 

CTL OUTPUTS

CTL START SYNCHCTL CHECK SYN OK 

CTL SYST SYN OK 

CTL DLINE*L#BUS

CTL LLINE*D#BUS

CTL DLINE*D#BUS

CTL UNDERVOLTAGE

CTL DIFF VOLTAGE

CTL SYSTEM SPLIT

I OPTO INPUT NUMBER

A INP START CHSYN

B INP START SYSSYN

C INP INH DLLB*CHS

D INP INH LLDB*CHS

E INP INH DLDB*CHS

F INP INH DLLB*SYS

G INP INH LLDB*SYS

H INP INH DLDB*SYS

I INP INH SYSPLIT

II RELAY MASK SETTINGS,KAVS 100

RELAY NUMBER

A RLY START SYNCH

B RLY CHECK SYN OK  

C RLY CHECK SYN OK  

D RLY D#LINE*L#BUS

E RLY L#LINE D#BUS

F RLY D#LINE*D#BUS

G RLY UNDERVOLTAGE

H RLY DIFF VOLTAGE

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I RLY SYSTEM SPLIT

 - RLY DLLB*CHSYN

K RLY LLDB*CHSYN

L RLY DLDB*CHSYN

M RLY DLLB*SYSSYN

N SLY LLDB*SYSSYN

O RLY DLDB*SYSSYN

LOGIC FUNTIONS

SCHEME FN# LINKS 1 .3/

LOGIC INPUT STATUS

LOGIC OUTPUT STATUS

LOGIC DEFAULT DI L(

LOGIC ROTATION EVERY 5 SECONDS

LOGIC TEST REALY 

CTL OUTPUTS

CTL START SYNCH

CTL CHECK SYN OK 

CTL SYST SYN OK 

CTL DLINE*L#BUS

CTL LLINE*D#BUS

CTL DLINE*D#BUS

CTL UNDERVOLTAGE

CTL DIFF VOLTAGE

CTL SYSTEM SPLIT

I OPTO INPUT NUMBER

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A INP START CHSYN

B INP START SYSSYN

C INP INH DLLB*CHS

D INP INH LLDB*CHS

E INP INH DLDB*CHS

F INP INH DLLB*SYS

G INP INH LLDB*SYSH INP INH DLDB*SYS

I INP INH SYSPLIT

II RELAY MASK SETTINGS,KAVS 100

RELAY NUMBER

A RLY START SYNCH

B RLY CHECK SYN OK  

C RLY CHECK SYN OK  

D RLY D#LINE*L#BUS

E RLY L#LINE D#BUSF RLY D#LINE*D#BUS

G RLY UNDERVOLTAGE

H RLY DIFF VOLTAGE

I RLY SYSTEM SPLIT

 - RLY DLLB*CHSYN

K RLY LLDB*CHSYN

L RLY DLDB*CHSYN

M RLY DLLB*SYSSYN

N SLY LLDB*SYSSYN

O RLY DLDB*SYSSYN

LOGIC FUNTIONS

SCHEME FN# LINKS 1 .3/

LOGIC INPUT STATUS

LOGIC OUTPUT STATUS

LOGIC DEFAULT DI L(

LOGIC ROTATION EVERY 5 SECONDS

LOGIC TEST REALY 

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CTL OUTPUTS

CTL START SYNCH

CTL CHECK SYN OK 

CTL SYST SYN OK 

CTL DLINE*L#BUS

CTL LLINE*D#BUS

CTL DLINE*D#BUSCTL UNDERVOLTAGE

CTL DIFF VOLTAGE

CTL SYSTEM SPLIT

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INPUT MASK SETTING-KAVS100

RELE 25 SAC 8710

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 00 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 00 0 0 0 0 0 0 0

0 0 0 0 0 0 1 1

0 0 0 0 0 0 1 1

0 0 0 0 0 0 1 1

0 0 0 0 0 0 1 1

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

F E D C B A & " 6 5 4 3 2 1

0 0 0 0 0 0 0 0 0 0 1 0 1 0 0

F E D C B A & " 6 5 4 3 2 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

F E D C B A & " 6 5 4 3 2 1

0 1 0 0 1 0 0 0 0 1 1 0 0 0 0

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F E D C B A & " 6 5 4 3 2 1

0 0 0 0 0 0 0 0 1 0 1 0 1 0 1

OFFOFF

OFF

OFF

OFF

ON

ON

OFF

OFF

INPUT MASK SETTING-KAVS100

RELE 25 SAC 8720

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0

0 0 0 0 0 1 1 1

0 0 0 0 0 1 1 1

0 0 0 0 0 1 1 1

0 0 0 0 0 1 1 1

0 0 0 0 0 1 1 1

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

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0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

F E D C B A & " 6 5 4 3 2 1

0 0 0 0 0 0 0 0 0 0 1 0 1 0 0

F E D C B A & " 6 5 4 3 2 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

F E D C B A & " 6 5 4 3 2 1

0 1 0 0 1 0 0 0 0 1 1 0 0 0 0

F E D C B A & " 6 5 4 3 2 1

0 0 0 0 0 0 0 0 1 1 1 0 1 0 1

OFF

OFF

OFF

OFF

OFF

ON

ON

OFF

OFF

INPUT MASK SETTING-KAVS100

RELE 25 SAC 8730

7 6 5 4 3 2 1 0

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0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 00 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 00 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

F E D C B A & " 6 5 4 3 2 1

0 0 0 0 0 0 0 0 0 0 1 0 1 0 0

F E D C B A & " 6 5 4 3 2 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

F E D C B A & " 6 5 4 3 2 1

0 1 0 0 1 0 0 0 0 1 1 0 0 0 0

F E D C B A & " 6 5 4 3 2 1

0 0 0 0 0 0 0 0 1 1 1 0 1 0 1

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OFF

OFF

OFF

OFF

OFF

ONON

OFF

OFF

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SORECORRIENTE

CIRCUITO 3080

SPA! 140C

I * I

 T+ .5/

I*II.5/

I * I

 TK.5/

I * I

 T .5/

SGB

SGR

SGF

N! SERIE

ALTO Y A!O VOLTA

SPAU 130C

UU

 T+.5/

UU

 T.5/

SG1

SGR

N! SERIE

0

0

0

0

0

0

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0

0

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0

0

0

0

0

0

0

1

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0

0

0

0

0

0

0

1

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0#5

0#05

4#340#04

0#1D

0#05

0#15

0#5

&6

10

115

13456

GE

1#2

0#5

0#"

5#05

36

1345

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