5/25/2018 Uart LPC2148

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3. UART

Unlike avr stop bits (logic 1) may be 1/1.5/2 in no. ALWAYS lsb first out: RS232

UART1 has interface for modems

UART0 Divisior Latch Regs (U0DLL and U0DLM) to set baud rate (8b each)

To auto set baud rate built-in fractional reg (U0FDR) (unlike avr): first key pressed gives arm idea baud rate which it hooks internally:

used for hw/sw flow control

Formula to calc baud rate (UART0):

b.r = Pclk / (16 (16 u0dlm + u0dll) (1+ DivAddVal/MulVal) )

0 8;

i.e get the lower/higher bytes from DL which is 2 Bytesso define macro 'baud b.r' then each time changing value of baud enough.

Before loading UDLL:

Set 7th bit (DLAB bit) 0f U0LCR (line control reg) to 1 (see pg 104 of manual)

Use UCLR for setting frame format as indicated

Again U0LSR (line status reg contains all flags for polling)

Rx char stred in read-only buffer: U0RBR

Tx char stred in: U0THR (tx hold reg)

Tx enable module reg : U0TER (shld be reset)

For intr: U0IER

Steps to initialize Uart: Configure PINSEL

Set DLAB bit

load UDLL

set a frame format

5/25/2018 Uart LPC2148

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