ultrafast 设计方法快捷参考指南 ( g1231) - xilinx

UG949PCB

IP

7 UltraScale UltraScale+

UG949

I/O

UltraFast

UltraFast FPGA SoC (UG949)

UltraFast (XTP301)

Documentation Navigator (DocNav)

Documention Navigator (DocNav) UltraFast

UltraFast (UG1231)

UG949 IP IP Integrator

PCB FPGA/SoC

I/O

SSI I/O

I/O I/O

GT

IP

I/O

DRC SSN

I/O

I/O

XPE

DELPHI

I/O

IP

RTL RTL

DSP

RTL

(OOC)

RTL

RTL DRC

UG1231 (v2020.2) 2021 2 18

PCB

PCB

FPGA

FPGA

PCB

PDS

I/O

I/O

I/O

See all versionsof this document

https://china.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;d=c_ug949-vivado-design-methodology.pdf;a=xBoardAndDevicePlanning

https://china.xilinx.com/products/design_resources/signal_integrity/si_pcbcheck.htm

https://china.xilinx.com/cgi-bin/docs/ndoc?t=memory+ip

https://china.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;d=c_ug949-vivado-design-methodology.pdf;a=xBoardAndDevicePlanning

https://china.xilinx.com/cgi-bin/docs/ndoc?t=design+hubs;d=dh0008-vivado-power-estimation-and-optimization-hub.html

https://china.xilinx.com/cgi-bin/docs/ndoc?t=design+hubs;d=dh0007-vivado-pin-planning-hub.html

https://china.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;d=c_ug949-vivado-design-methodology.pdf;a=xDesignCreation

https://china.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;d=c_ug949-vivado-design-methodology.pdf;a=xImplementation

https://china.xilinx.com/cgi-bin/docs/ndoc?t=design+hubs;d=dh0003-vivado-designing-with-ip-hub.html

https://china.xilinx.com/cgi-bin/docs/ndoc?t=design+hubs;d=dh0009-vivado-using-ip-integrator-hub.html

https://china.xilinx.com/cgi-bin/docs/ndoc?t=design+hubs;d=dh0018-vivado-synthesis-hub.html

https://china.xilinx.com/cgi-bin/docs/ndoc?t=design+hubs;d=dh0004-vivado-applying-design-constraints-hub.html

https://china.xilinx.com/cgi-bin/docs/ndoc?t=design+hubs;d=dh0019-vivado-implementation-hub.html

https://secure.xilinx.com/webreg/clickthrough.do?cid=198776&license=RefDesLicense&filename=xmp277-7series-schematic-review-recommendations.zip

https://china.xilinx.com/cgi-bin/docs/ctdoc?cid=359174;d=xtp344-ultrascale-schematic-review-checklist.zip

https://china.xilinx.com/cgi-bin/docs/ctdoc?cid=423500;d=xtp427-ultrascale-plus-schematic-review-checklist.zip

https://www.xilinx.com/bin/public/docSeeAllVersions?productType=DesignTools&documentId=UG1231

UltraFast (UG1231)

UG949

UG949

report_qor_suggestions

report_timing_summary report_design_analysis

7 > 25% UltraScale > 50% 7 > 75% UltraScale > 50%

> 0 ns

(> 500 ps) / (> 200 ps)

RTL

DSP RAM LUT_REMAP LUT SRL / SRL KEEP/DONT_TOUCH/MARK_DEBUG

> 4 report_design_analysis

PLL CLOCK_DELAY_GROUP

MMCM UltraScale BUFGCE_DIV

UG949

IP

IP

I/O

report_timing_summary

WNS 0.0 ns

RTL QoR

report_timing_summary check_timing

report_methodology TIMING* XDC*

report_clock_interaction

report_cdc

report_exceptions

Critical Warning

UG1231 (v2020.2) 2021 2 18

MAX_FANOUT

opt_design

RTL opt_design -merge_equivalent_drivers

-hier_fanout_limit

FORCE_MAX_FANOUT

SLR AltSpreadLogic* SSI_Spread* report_design_analysis -

complexity -congestion

AlternateRoutability opt_design MUXF*/CARRY*

CELL_BLOAT_FACTOR

DSP RAM

place_design ML report_qor_suggestions

set_clock_uncertainty

power_opt

RAM

https://china.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;d=c_ug949-vivado-design-methodology.pdf;a=xDesignClosure

https://china.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;d=c_ug949-vivado-design-methodology.pdf;a=xCheckingThatYourDesignIsProperlyConstrained

https://china.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;d=c_ug949-vivado-design-methodology.pdf;a=xBaseliningTheDesign

https://china.xilinx.com/cgi-bin/docs/ndoc?t=design+hubs;d=dh0004-vivado-applying-design-constraints-hub.html

https://china.xilinx.com/cgi-bin/docs/ndoc?t=design+hubs;d=dh0006-vivado-design-analysis-and-timing-closure-hub.html


https://china.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;d=c_ug949-vivado-design-methodology.pdf;a=xUnderstandingTimingReports

https://china.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;d=c_ug949-vivado-design-methodology.pdf;a=xIdentifyingTimingViolationsRootCause


https://china.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;d=c_ug949-vivado-design-methodology.pdf;a=xImplementation


https://china.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;d=c_ug949-vivado-design-methodology.pdf;a=xAnalyzingAndResolvingTimingViolations

https://china.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;d=c_ug949-vivado-design-methodology.pdf;a=xApplyingCommonTimingClosureTechniques

https://china.xilinx.com/cgi-bin/docs/ndoc?t=design+hubs;d=dh0019-vivado-implementation-hub.html


ultrafast 设计方法快捷参考指南 ( g1231) - xilinx

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