UNIVERSIDAD AUTONOMA METROPOLITANA

IZTAPALAPA

DEPARTAMENTO DE INGENIERIA ELECTRICA

“MEDIDOR DE POTENCIA DIGITAL”

PROYECTO TERMINAL

P R E S E N TA

GARCÍA RÍOS PERLA

ASESOR DE PROYECTO

_________________________________

ING. DONACIANO JIMENEZ V.

1-ANTECEDENTES

2-OBJETIVOS

2.1 Objetivo general

2.2 Objetivos Particulares

3-METODOLOGÏA

3.1 Diseño general del medidor de potencia

3.2 Componentes básicos del medidor de potencia

3.2.1 Convertidor A/D

3.2.2 Resistencia de carga

3.2.3 Atenuador

3.2.4 Convertidor de CA a CD

4-RESULTADOS Y DISCUSIÓN

5- CONCLUSIONES

6-ANEXO

7-REFERENCIAS

MEDIDOR DE POTENCIA DIGITAL

1- ANTECEDENTES

En los hospitales como parte del equipo de cirugía se cuenta con

unidades de electrocirugía. Estos dispositivos son conocidos como

electrocauterio, su uso es una practica común para el cirujano, en vez de

bisturí convencional, para la creación de incisiones. Los instrumentos

electocirugía dividen el tejido mediante la energía creada por una

corriente alterna de alta frecuencia. Esta frecuencia incrementa la

temperatura tisular con la punta del instrumento para lesionar y

seccionar la membrana celular. Dependiendo de onda empleada, la

corriente puede ser usada para seccionar tejido o para coagular vasos

sanguíneos.

Dado que la corriente pasa a través del cuerpo es importante que se

tenga un control estricto de la potencia que incide en él, de no hacerlo

se corre el riesgo que el equipo no este funcionando correctamente y se

le aplique más corriente de la necesaria el paciente produciéndole

quemaduras de grado significativo.

La potencia instantánea es el ritmo al que un elemento absorbe

energía, y varía como función del tiempo. Esta definida como la corriente

por el voltaje que pasa por el cuerpo, para realizar esta medición es

necesario contar con el equipo adecuado, el costo comercial de dicho

equipo es alto.[1,2,3]

El presente proyecto presenta una alternativa de bajo costo para

medir la potencia de dispositivos con las características de los

electrocauterios.

2-OBJETIVOS

2.1 Objetivo general

Diseñar e implementar un dispositivo que se capaz de medir la

potencia electrica en forma digital.

2.2 Objetivos Particulares

• Implementar el medidor potencia propuesto para el Valleylab

E3000 (SurgiStat Electrosurgical Generator).

• Utilizar el ICL 7107 en su aplicación medidor de voltaje.

• Diseñar un transformador que disminuya la corriente del

primario y proporcione un valor en el secundario que refleje la

potencia.

3-METODOLOGÏA

3.1 Diseño general del medidor de potencia

Para la realización del diseño de medidor se potencia se toma como

base la propuesta mostrada en el manual de servicio Valleylab E3000

(SurgiStat Electrosurgical Generator) .

El diagrama se muestra en la figura 1. Esta formado por la resistencia

de carga de 500 a 50 W, un medidor de corriente a radio frecuencia y

un seleccionador de escala para mediciones de 0 –125 W y de 0 – 500 W.

La medición de la potencia se realiza de forma indirecta, leyendo en el

galvanometro la medición de la corriente con un calculo simple se

obtiene la potencia, a continuación se muestra matemáticamente en la

ecuación 1[3].

P = V²/ R (1)

Donde:

P = Potencia

V = Voltaje

R = Resistencia

Figura 1

En la figura 2 se muestra el diagrama a bloques del diseño modificado

de la figura 1. para su implementación en forma digital.

La primera etapa es el acondicionamiento de la señal está formada por

la resistencia de carga, el atenuador y el convertidor de AC a DC.

La segunda etapa es la conversión A/D y el despliegue.

Corriente o voltaje a medir Señal en CC

Señal en CA Señal preescalada

Figura 2

El instrumento es el dispositivo al que se le va a medir la potencia,

se conecta en serie con la resistencia de carga y con el primario del

transformador, este arreglo permite disminuir la corriente que viene del

instrumento o dispositivo que se esta midiendo . La parte del secundario

va conectada a la entrada del circuito Convertidor de AC a DC del cual

se obtiene un voltaje el DC que representa el valor de la potencia

eléctrica del dispositivo, El voltaje entra al convertidor analogico/digital

y el nivel de voltaje se muestra en los displays. La figura 2 se explica

con más detalle en la siguiente sección.

3.2 Componentes básicos del medidor de potencia

3.2.1 Convertidor A/D

Como la medición de la potencia es de forma digital necesitamos un

dispositivo que nos convierta la medición de analógica a digital.

El Convertidor A/D de 3 ½ dígitos sus aplicaciones más comunes son

voltímetros y amperímetros digitales. En el diseño de este voltímetro

Instrumento

Resistencia decarga Atenuador

Convertidor deAC a DC

Convertidor A/DDespliegue

digital se presenta el convertidor A/D CMOS ICL 7107. El diagrama de

terminales para este circuito integrado se muestra en la figura 3. El

ICL7107 alimenta un despliegue de diodos emisor de luz (LED). Se

incluyen descodificadores de 7 segmentos, alimentadores de despliegue,

referencias y un reloj.

El circuito integrado opera en tres fases:

1) regreso automático a cero,

2) integración de la señal y

3) integración de la referencia.

En la fase 1 de la conversión de doble pendiente, el ciclo se lleva a

cero para empezar nuevamente. Este proceso se conoce como fase de

regreso automático a cero. En la fase dos del método de doble

pendiente, la señal se integra durante un tiempo fijo con una pendiente

que depende de la combinación RC del amplificador operacional de

integración. En la fase 3, la entrada del integrador se conmuta de Vi a

Vref. La polaridad se determina durante la fase 2 de modo que el

integrador se descargue hacia cero. El número de pulsos de reloj que se

cuentan entre el inicio de este ciclo (fase 3) y el momento en que la

salida del integrador pasa por cero es una medida digital de la magnitud

de Vi.

El potencial de alimentación del integrado se aplica a los pines 1 y 21,

siendo de +5V y -5V respectivamente, respecto a tierra. Se requiere de

4 unidades de display siete segmentos, ánodo común para mostrar la

medición con tres cifras signada y otro display del mismo tipo para

indicar que la medición está fuera del rango de la escala.

Los pines del 2 al 8 manejan el display que muestra las unidades de la

cifra, los pines del 9 al 14 manejan el display que muestra las decenas y

los pines de 15 al 18 y del 22 al 25 manejan el display que muestra las

centenas. Con el pin 20 se maneja el display que muestra el signo

negativo y con el pin 19 se maneja el display que indica el sobre rango.

El pin 32 (COM) actúa como tierra flotante para los voltajes de entrada y

de referencia. El voltaje que se quiere medir se coloca entre los pines

31 y 30, es capas de medir hasta 2 V , observándose en los displays

hasta 1.999 V .

Los pines 38 (OSC3), 39 (OSC2) y 40 (OSC1) proporcionan acceso al

reloj interno. La frecuencia de oscilación se determina con la ecuación 2:

Fosc = 0.45 / (R5 C5) (2)

Internamente esta frecuencia se divide entre cuatro para obtener los

pulsos utilizados por el contador y la circuitería de control lógico durante

cada ciclo de medida. Con el pin 37 (TEST) se comprueba la correcta

conexión de los displays.

La presición de la medición depende de la exactitud de los

componentes con los que es construido.

Figura 3

Donde:

R1 = 470 KΩ

R2 = 1MΩ

R3 potenciómetro de 25 KΩ

R4 = 24KΩ

R5 = 100KΩ

C1 = 0.22µF

C2 = 0.047µF

C3 = 0.01µF

C4 = 0.1µF

C5 = 100pF

3.2.2 Resistencia de carga

La resistencia de carga representa la impedancia que presenta el

cuerpo al pasar la corriente a través de él, de la punta activa a la placa de

paciente del electrocauterio, dicha impedancia es considerada de 500 Ω (el

valor considera la impedancia de la placa de paciente)[1,3].

En la figura 1 se muestra el arreglo de resistencias propuesto, esta

formado por 4 resistencias de 250 Ω a 50 W en paralelo con 4 del mismo

valor, debido a problemas por los valores comerciales se utilizan 8 juegos

de resistencias en paralelo de 470 Ω a 25 W y 2 juegos de resistencias de

120 Ω a 25 W, se obtiene una resistencia equivalente de 500 Ω.

Se utilizan resistencias de potencia debido a que la los niveles

corriente que manejan los electrocauterios es alto.

3.2.3 Atenuador

El atenuador no es más que un transformador de núcleo de ferrita. La

función de todo tipo de transformador consiste en transformar o

cambiar la electricidad de alguna manera. Un transformador básico consta

de dos bobinas enrolladas sobre el mismo núcleo de hierro, el cual forma un

circuito magnético cerrado. El transformador no funciona con corriente

continua es necesario suministrar corriente alterna o corriente continua

pulsátil.

En el devanado, al que se le suministra energía se le denomina

primario, y al devanado del cual se toma la energía se llama secundario.

Cualquier cambio en la corriente del primario produce un cambio en

el flujo que enlaza el devanado secundario inducirá un voltaje en las

terminales del secundario.

Si el voltaje en el secundario es el mismo que el voltaje del primario,

al trasformador se le denomina transformador uno a uno, si el voltaje del

secundario es mayor que el del primario, éste será un transformador

elevador, y cuando el voltaje del secundario es menor que el voltaje del

primario, éste será un transformador reductor. La potencia suministrada al

primario, con una frecuencia específica, produce una potencia de la misma

frecuencia en el secundario[2].

Las relaciones de corriente en un transformador son:

Ep/Es = Is/Ip (3)

Donde:

Ep = voltaje aplicado en el primario

Es = voltaje en el secundario

Ip = corriente en el primario

Is = corriente en el secundario

Las relaciones de voltaje en un transformador son:

Ep/Es = Np/Ns (3)

Donde:

Ep = voltaje aplicado en el primario

Es = voltaje en el secundario

Np = número de vueltas en el primario

Ns = número de vueltas en el secundario

Con base en lo anterior el tipo de transformador que se requiere en este

proyecto es un transformador elevador, con el embobinado primario de 4

vueltas de alambre magneto con calibre 11 para que no existan perdidas de

voltaje en la señal de entrada, el embobinado secundario son 7 vueltas las

suficientes para que el voltaje en el secundario represente la potencia

eléctrica en la resistencia de carga.

3.2.4 Convertidor de CA a CD

Figura 4

En convertidor de CA a CD es parte del acondicionamiento de la

señal, normaliza la entrada a un voltaje de corriente continua. La figura 4

muestra el circuito utilizado, a la entrada no inversora del AOP entra el

voltaje del secundario del transformador, dicho voltaje es de corriente

alterna a la salida obtenemos un voltaje en corriente continua. La

polarización del TL081 es de +5 V y –5 V.

4-RESULTADOS Y DISCUSIÓN

Tabla 1: Resultados obtenidos a diferentes frecuencias y resultados teoricos

Vrms (V) W54kHz

(m watts)

W100kHz

(m watts)

W147kHz

(m watts)

W199kHz

(m watts)

Wteo

(m watts)

7.07 53 98 141 190 99

6.03 44 80 118 156 72

5.03 36 64 95 123 50

4.03 28 48 71 92 32

3.01 18 32 47 62 18

Para realizar estas mediciones se utiliza un generador de funciones

por no contar con un electrocoagulador.

La tabla 1 muestra los resultados experimentales, estos valores se

obtuvieron directamente del despliegue del convertidor A/D. Se fijaron 4

diferentes valores de frecuencias y se tomaron 5 valores diferentes de

voltaje, la ultima columna son los resultados teoricos obtenidos con la

ecuación 1.

De la tabla podemos observar que 100 Hz es la frecuencia en que los

valores de potencia son muy aproximados, a frecuencias menores los

valores disminuyen y en el caso contrario aumentan, esto se debe al

ancho de banda del medidor de potencia.

También se observa los valores obtenidos son pequeños por

limitaciones propias del generador de funciones.

En el Anexo se muestran ilustraciones del circuito funcionando.

5-CONCLUSIONES

Se ha presentado el diseño de un medidor de potencia digital

como una alternativa de bajo costo, para la realizar mantenimiento

preventivo a unidades de electrocirugia en hospitales que no cuenten con

los recursos para adquirir uno comercial.

El dispositivo es capaz de mostrar la potencia eléctrica de un

instrumento o dispositivo de su voltaje o corriente de salida del mismo.

El dispositivo tiene un rango de medición limitado de 0 W a 2 W,como

sugerencia para mejorar al diseño anterior se puede aumentar el rango de

medición con el diagrama de la figura 5, es un circuito de auto rango, con el

cual podemos realizar mediciones de 0 W a 200W sin necesidad de

seleccionar las escalas de manera manual.

Figura 5

7-REFERENCIAS

[1] Medical Instrumentation, Aplication and Design, Webster, Editorial

Houghton Mifflin, Segunda Edición.

[2] Electrónica Moderna para ingenieros y técnicos, Milton Kaufman,

Editorial Mc Graw Hill, Segunda Edición.

[3] Manual de servicio Valleylab E3000 (SurgiStat Electrosurgical

Generator) .

1

AN046

1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

Building a Battery Operated Auto Ranging DVMwith the ICL7106

IntroductionIn the field of DVM design, three areas are being addressedwith vigor: size, power dissipation, and novelty. Thehandheld portable multimeter has gained in popularity sincelow power dissipation devices enabled battery operation, LSIA/D converters reduced IC count, and novelties such asconductance, automatic range scaling, and calculating wereincluded to entice the user.

This application note describes a technique for auto-ranginga battery operated DVM suitable for panel meterapplications. Also, circuit ideas will be presented forconductance and resistance measurement, 9V battery and5V supply operations, and current measurement.

Auto Ranging CircuitryThe control signals necessary for auto-ranging are over-range, under-range, and clock. The over-range and under-range inputs control the direction of a scale shift, becomingactive at the completion of an invalid conversion andremaining active until a valid conversion occurs. The clockinput controls the timing of a scale shift. This signal shouldoccur only once per conversion cycle, during a time windowwhich will not upset an ongoing conversion and must bedisabled after valid conversions.

In the circuit of Figure 1, inverted over-range (O/R) andunder-range (U/R) are generated by detecting the displayreading. The ICL7106 turns the most significant digit on andblanks the rest to indicate an over-range. An under-rangeoccurs if the display reads less than 0100. R1C1 and R2C2are required to deglitch O/R and U/R.

The next step in the logic disables O/R and U/R prior toshifting into nonexistent ranges. O/R is disabled when in the200V range, while U/R is disabled when in the 200mV range.

The next level of gating disables the clock if the conditionsare as described above and a valid conversion state exists.Clock is enabled only when a range shift is called for andthere exists a valid range to shift into.

The CD4029 is a four bit up/down counter, used as a registerto hold the present state and as a counter to shift the scaleas directed by the control inputs. The CD4028 is a BCD todecimal decoder interfacing the CD4029 and ladderswitches. An additional exclusive OR gate package is addedto drive the appropriate decimal point.

Input Divider NetworkA simplified drawing of the divider network is shown inFigure 2. This configuration was chosen for simplicity andimplementation using analog switches. The low leakageID101s are used for input protection, and the second set ofswitches to IN LO reduces the net error due to switchresistance. This can be seen calculating IN HI and IN LOvoltages for the two equivalent circuits.

For equivalent circuit A,

where RS = switch resistance, R = input resistance (1MΩ),and 1 + K is the desired divider ratio.

Ideally VINHI should be

Therefore the percent error is:

The worst case error occurs at (1+K) = 1000. For thisexample, the error due to a 1kW switch resistance is 99.7%.

IN HI for equivalent circuit B is the same as Equation 1.However, IN LO for circuit B is:

and combining Equations (1) and (5)

The percent error is equal to:

Using the same values for RS, (1+K), and R, the worst caseerror is 0.1%. This error can be further improved if lowerrDS(ON) switches are used. From the results calculatedabove, the worst case conversion error due to switchresistance will be one count of the least significant digit for afull scale input, and a slight adjustment to R itself will correctthe remaining error on all scales.

VMEAS VIN HI

RS R K⁄+

RS R R K⁄+ +-------------------------------------

VIN= = (EQ. 1)

VIDEALR K⁄

R K R+⁄-----------------------

VIN1

1 K+-------------

VIN== (EQ. 2)

(EQ. 3)Ideal Actual–

Ideal--------------------------------------- 100,

(EQ. 4)or 1 1 K+( )RS R/K+

RS R/K R+ +-----------------------------------–

100

RSRS R R K⁄+ +-------------------------------------

VIN, (EQ. 5)

VMEAS VINHI VINLO–R K⁄

RS R R K⁄+ +-------------------------------------

VIN= = (EQ. 6)

1 1 K+( ) R/KR R+ S R/K+-----------------------------------–

100 (EQ. 7)

Application Note

Larry Goff

2

13

1

2

3

4

5

6

7

8

9

10

11

12

14

15

16

17

18

19

20

V+

D1

C1

B1

A1

F1

G1

E1

D2

C2

B2

A2

F2

E2

D3

B3

F3

E3

AB4

POL

28

40

39

38

37

36

35

34

33

32

31

30

29

27

26

25

24

23

22

21

OSC 1

OSC 2

OSC 3

TEST

REF HI

REF LO

CREF

CREF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V-

G2

C3

A3

G3

BP

V-

12

13

2

1

5

6

89

C1R1

0.005µF

C2R2

0.005µF

TEST

TEST

A

D

100pF

1µF

100kΩ

1kΩ

24kΩ

47kΩ

0.22µF

0.47µF

0.01µF

DIG GND

V+

47MΩ

20kΩ

22kΩ

0.1µF

TEST

OPEN

OPEN

VIN

VIN

12 131 2 5 6 8 9

TESTBACK

PLANE

A OR DCBA

A

D

C

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

V+

3

1

B

C

D

A

V

2

O

TEST

B

V+

DECODER

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

V+

CLK

Q7

V

V+TEST

UP/DOWNCOUNTER

BINARYDECODE

UP/DOWN

PE

Q1

C1

ARROW

FIGURE 1. AUTO RANGING CIRCUITRY

V+

CREF

CLOCK A/Z

ICL7106 PIN26

V -

O/RANGE

10kΩ

4023

4023

6

O/RANGE10kΩ

9 8

11

1021 13

4023

1211 4

3

10

4

3

5

23

10

4011

21

12

3

13

74C32

11

4011

4011

89

1

5

46

CD4029BC CD402T

1.001kΩ

D1Q2

DD

Q1

S

3N169N CH. 1MΩ D2

100kΩ

Q3

2N3702

C3

ID101

R1 R2 R3 R6

1MΩ13, 5

6, 12

5, 1312

8

6

911

10

43

111010.1kΩ

R4

R51 2

34

CD4016

CD4016

9

4011

R8

S

5.1kΩ

8

111.1kΩ

Ap

plicatio

n N

ote 046

3

Ranging Clock CircuitTwo N-Channel MOSFETs, a PNP transistor and a handfulof passive components combine to generate the clock signalused to gate the auto-ranging logic. A closer look at the innerworkings of the ICL7106 will help clarify the discussion ofthis circuit. The analog section of the ICL7106 is shown inFigure 3.

It can be shown that CREF low (pin 33 of ICL7106) will sit at-VREF for DE+ and at common for DE-, with DE+designating the deintegrate phase for a positive input signaland DE- referring to a negative input signal. During the auto-zero phase, CREF low is tied to an external referencethrough pin 35, which in Figure 1 is VREF below the positivesupply. The net result is that CREF low is above COMMONduring auto-zero, is left to float during signal integrate, and isat or below COMMON during deintegrate. R8 and D1 areadded externally to pull CREF to COMMON during integrate,with Q2 and R1 included to speed this action. The signal atCREF low is now a square wave that is high during auto-zeroand low at all other times. Q1 and Q3 amplify and level shiftthis waveform for logic level compatibility. This clock signal is

gated through D2 and controls the timing of the auto-rangingcircuitry. C3 is added to delay the clock, eliminating disparitywith O/R and U/R (see Figure 4 for timing diagram).

FIGURE 2A.

FIGURE 2B. EQUIVALENT CIRCUIT A(SWITCHES TO IN LO REMOVED)

FIGURE 2C. EQUIVALENT CIRCUIT B(SWITCHES TO IN LO INCLUDED)

FIGURE 2. INPUT DIVIDER NETWORK

R/999

200V

R/99.01

20V

R/9

2V 200mV

SWITCH CONTROLLINES

VIN

+

-

R

ID101

IN HI

IN LO

+

-

R

R/K

R SWITCH

TO IN HI

TO IN LO

VIN

VMEAS

+

-

R

R/K

R SWITCH

TO IN HI

TO IN LO

VIN VMEAS

Application Note 046

4

Supply RequirementsThe circuit of Figure 1 operates on a standard 9V transistorbattery. CMOS logic and a CMOS A/D converter (ICL7106)are used to extend battery life; the approximate power drainfor this circuit is 8mW. The circuit in Figure 5 can also beadded to detect low supply voltage.

The circuit of Figure 6 can be used to generate ±5V from asingle 5V supply. The ICL7660 is a voltage converter whichtakes a 5V input and produces a -5V output. With respect tocommon mode signals, the circuit of Figure 1 will haveinfinite common mode handling capability if operated from afloating 9V battery. However, if powered by a fixed supplysuch as in Figure 6, the common mode capability of the

converter will be limited to approximately ±2V, if COMMON isdisconnected from -VIN.

FIGURE 3. ANALOG SECTION OF ICL7106

FIGURE 4. TIMING DIAGRAM

DE-DE+

CINTCAZRINT

BUFFER A-Z INT

-+

A-Z

COMPARATOR

IN HI

COMMON

IN LO

31

32

30

DE- DE+INT

A-Z

34

CREF+

36

REF HI

CREF

REF LO

35

A-Z A-Z

33

CREF-

28 29 27

TODIGITALSECTION

A-Z AND DE(±)

INTEGRATOR

INT

V+

10µA

V-

N

INPUTHIGH

2.8V

6.2V

V+

1

INPUTLOW

-+

-+

-+

26

INTEGRATOR

CREF LOW(PIN 33)

CLOCK

O/R, U/R

A/Z OVER-RANGECONVERSION

VALIDCONVERSION

A/Z A/Z

Application Note 046

5

Resistance, Transconductance andCurrent CircuitsThe purpose of this section is to show the simplicity ofmeasuring transconductance (1/R) and resistance with theICL7106. The circuit of Figure 7 requires only one precisionresistor per decade range of interest. The conversion outputis described by the formula:

For transconductance measurement, merely switch RSTDand RX. This scheme makes the measurement of largeresistors, in conductance form, convenient and easy. This isalso convenient for leakage measurements.

A simple current meter can be built using the circuit ofFigure 8. The low leakage of the ICL7106 (10pA/max)makes possible the measurement of currents in the midpico-Amp range. However, the switch leakage current willlimit the accuracy of the resistor network and may degradeconverter resolution.

Using the ICL7126 and ICL7107With a few modifications, the circuit of Figure 1 can easily beadapted for use with either the low power ICL7126 or theICL7107. Using the ICL7126 simply requires a change in thevalues of the integrating and auto-zero components. Refer tothe ICL7126 data sheet for details.

The ICL7107 is an LED version of the ICL7106, and is a bittrickier to use in this application. First the over-range/under-range logic must be changed slightly. Simply replace thequad exclusive-NOR with an LM339; connect the outputs, asbefore, to the CD4023 triple 3-input NAND. Second, theICL7107 requires +5V and -5V rather than the +9V batteryused in Figure 1. If battery operation is desired, the negativesupply can be derived from 4 Ni-Cad cells in series and anICL7660 (see Figure 9). Note that both supplies float withrespect to the input terminals. (Logic supplies are V+ andDIG. GND.)

FIGURE 5. LOW VOLTAGE DETECTOR

FIGURE 6. GENERATING ±5V FROM +5V

FIG 7

1

2

3

4

8

7

6

5

1MΩ

ICL8211

180K

1MΩ

TO DISPLAYINDICATOR

TESTBACKPLANE

1

2

3

4

8

7

6

5

+

-10µF

+5V

10µF

ICL7660

NC

NC

NC AUTO-RANGINGDVM CIRCUIT

-5V

RXRSTD---------------

1000 (EQ. 8)

REF HI

REF LO

COMMON

IN HI

IN LO

ICL7106

V+

RSTD

X4

RX

FIGURE 7. TRANSCONDUCTANCE AND RESISTANCEMEASUREMENT

IN914 orIN4148

IN HI

IN LO

ICL7106

900R

FIGURE 8. CURRENT METER

90R

9R

R

IIN

Application Note 046

6

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate andreliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may resultfrom its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Office HeadquartersNORTH AMERICAIntersil CorporationP. O. Box 883, Mail Stop 53-204Melbourne, FL 32902TEL: ( 321) 724-7000FAX: ( 321) 724-7240

EUROPEIntersil SAMercure Center100, Rue de la Fusee1130 Brussels, BelgiumTEL: (32) 2.724.2111FAX: (32) 2.724.22.05

ASIAIntersil (Taiwan) Ltd.7F-6, No. 101 Fu Hsing North RoadTaipei, TaiwanRepublic of ChinaTEL: (886) 2 2716 9310FAX: (886) 2 2715 3029

O /RANGE

U /RANGE

CD4023 OR74C10

-5V

33kΩ

13

1

2

3

4

5

6

7

8

9

10

11

12

14

15

16

17

18

19

20

V3

D1

C1

B1

A1

F1

G1

E1

D2

C2

B2

A2

F2

E2

D3

B3

F3

E3

AB4

POL

28

40

39

38

37

36

35

34

33

32

31

30

29

27

26

25

24

23

22

21

OSC 1

OSC 2

OSC 3

TEST

REF HI

REF LO

CREF

CREF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V-

G2

C3

A3

G3

GND

12kΩ

+-

+-

+-

FIGURE 9. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNALS FROM ICL7107 OUTPUTS. THE LM339 ISREQUIRED TO ENSURE LOGIC COMPATIBILITY WITH HEAVY DISPLAY LOADING

NEGATIVE (0V)LOGIC SUPPLY

LM339

1

2

3

4

8

7

6

5

+

-10µF

ICL7660

-5V

+

-10µF

+5V

ICL7107

+-

Application Note 046

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.

Copyright © Harris Corporation 19932-33

S E M I C O N D U C T O R

PinoutsICL7106, ICL7107

(PDIP)TOP VIEW

ICL7106, ICL7107(MQFP)

TOP VIEW

13

1

2

3

4

5

6

7

8

9

10

11

12

14

15

16

17

18

19

20

V+

D1

C1

B1

A1

F1

G1

E1

D2

C2

B2

A2

F2

E2

D3

B3

F3

E3

(1000) AB4

POL

28

40

39

38

37

36

35

34

33

32

31

30

29

27

26

25

24

23

22

21

OSC 1

OSC 2

OSC 3

TEST

REF HI

REF LO

CREF+

CREF-

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V-

G2 (10’s)

C3

A3

G3

BP/GND

(1’s)

(10’s)

(100’s)

(MINUS)

(100’s)

OSC 2

NC

OSC 3

TEST

NC

NC 1

2

3

4

5

6

7

8

9

10

1112 13 14 15 16 17

OSC 1

V+

D1

C1

B1

A1 F1 G1 E1 D2 C2

28

27

26

25

24

232221201918

B2 A2 F2 E2 D3

B3

F3

E3

AB4

POL

BP/GND

39 38 37 36 35 3433

32

31

30

29

44 43 42 41 40

IN H

I

IN L

O

A-Z

BU

FF

INT

V-

NC

G2

C3

A3

G3

RE

F H

I

RE

F L

O

CR

EF+

CR

EF-

CO

MM

ON

ICL7106, ICL710731/2 Digit LCD/LED

Display A/D Converter

Features• Guaranteed Zero Reading for 0V Input on All Scales

• True Polarity at Zero for Precise Null Detection

• 1pA Typical Input Current

• True Differential Input and Reference, Direct Display Drive- LCD ICL7106- LED lCL7l07

• Low Noise - Less Than 15 µVp-p

• On Chip Clock and Reference

• Low Power Dissipation - Typically Less Than 10mW

• No Additional Active Circuits Required

• New Small Outline Surface Mount Package Available

Ordering Information

PARTNUMBER

TEMPERATURERANGE PACKAGE

ICL7106CPL 0oC to +70oC 40 Lead Plastic DIP

ICL7106RCPL 0oC to +70oC 40 Lead Plastic DIP (Note 1)

ICL7106CM44 0oC to +70oC 44 Lead Metric Plastic Quad Flatpack

ICL7107CPL 0oC to +70oC 40 Lead Plastic DIP

ICL7107RCPL 0oC to +70oC 40 Lead Plastic DIP (Note 1)

ICL7107CM44 0oC to +70oC 44 Lead Metric Plastic Quad Flatpack

NOTE: 1. “R” indicates device with reversed leads.

File Number 3082

January 1994

DescriptionThe Harris ICL7106 and ICL7107 are highperformance, low power 31/2 digit A/D converters.Included are seven segment decoders, display drivers,a reference, and a clock. The ICL7106 is designed tointerface with a liquid crystal display (LCD) andincludes a multiplexed backplane drive; the ICL7107will directly drive an instrument size light emittingdiode (LED) display.

The ICL7106 and ICL7107 bring together acombination of high accuracy, versatility, and trueeconomy. It features auto-zero to less than 10µV, zerodrift of less than 1µV/οC, input bias current of 10pAmax., and rollover error of less than one count. Truedifferential inputs and reference are useful in all sys-tems, but give the designer an uncommon advantagewhen measuring load cells, strain gauges and otherbridge type transducers. Finally, the true economy ofsingle power supply operation (ICL7106), enables ahigh performance panel meter to be built with theaddition of only 10 passive components and a display.

2-34

Specifications ICL7106, ICL7107

Absolute Maximum Ratings Thermal InformationSupply Voltage

ICL7106, V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15VICL7107, V+ to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6VICL7107, V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-9V

Analog Input Voltage (Either Input) (Note 1). . . . . . . . . . . . . V+ to V-Reference Input Voltage (Either Input) . . . . . . . . . . . . . . . . . V+ to V-Clock Input

ICL7106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+ICL7107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND to V+

Thermal Resistance (MAX, See Note 1) θJA40 Pin Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . 50oC/W44 Pin MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . 80oC/W

Maximum Power DissipationICL7106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0WICL7107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2W

Operating Temperature Range . . . . . . . . . . . . . . . . . . 0oC to +70oCStorage Temperature Range. . . . . . . . . . . . . . . . . . -65oC to +150oCLead Temperature (Soldering 10s Max) . . . . . . . . . . . . . . . . +265oCJunction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationof the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Electrical Specifications (Note 3)

PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT

SYSTEM PERFORMANCE

Zero Input Reading VIN = 0.0V, Full-Scale = 200mV -000.0 ±000.0 +000.0 DigitalReading

Ratiometric Reading VlN = VREF, VREF = 100mV 999 999/1000

1000 DigitalReading

Rollover Error -VIN = +VlN ≅ 200mVDifference in Reading for Equal Positive and Nega-tive Inputs Near Full-Scale

- ±0.2 ±1 Counts

Linearity Full-Scale = 200mV or Full-Scale = 2V MaximumDeviation from Best Straight Line Fit (Note 5)

- ±0.2 ±1 Counts

Common Mode Rejection Ratio VCM = 1V, VIN = 0V, Full-Scale = 200mV (Note 5) - 50 - µV/V

Noise VIN = 0V, Full-Scale = 200mV (Pk-Pk Value Not Exceeded 95% of Time)

- 15 - µV

Leakage Current Input VlN = 0 (Note 5) - 1 10 pA

Zero Reading Drift VlN = 0, 0o < TA < +70oC (Note 5) - 0.2 1 µV/oC

Scale Factor Temperature Coefficient VIN = 199mV, 0o < TA < +70oC,(Ext. Ref. 0ppm/°oC) (Note 5)

- 1 5 ppm/oC

End Power Supply Character V+ Supply Cur-rent

VIN = 0 (Does Not Include LED Current for ICL7107) - 0.8 1.8 mA

End Power Supply Character V- Supply Current ICL7107 Only - 0.6 1.8 mA

COMMON Pin Analog Common Voltage 25kΩ Between Common andPositive Supply (With Respect to + Supply)

2.4 2.8 3.2 V

Temperature Coefficient of Analog Common 25kΩ Between Common andPositive Supply (With Respect to + Supply)

- 80 - ppm/oC

DISPLAY DRIVER ICL7106 ONLY

Pk-Pk Segment Drive VoltagePk-Pk Backplane Drive Voltage

V+= to V- = 9V, (Note 4) 4 5 6 V

2-35

ICL7106, ICL7107

Typical Applications and Test Circuits

ICL7107 ONLY

Segment Sinking Current V+ = 5V, Segment Voltage = 3V

(Except Pin 19 and 20) 5 8 - mA

Pin 19 Only 10 16 - mA

Pin 20 Only 4 7 - mA

NOTES:1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA.

2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.

3. Unless otherwise noted, specifications apply to both the ICL7106 and ICL7107 at TA = +25oC, fCLOCK = 48kHz. ICL7106 is tested in thecircuit of Figure 1. ICL7107 is tested in the circuit of Figure 2.

4. Back plane drive is in phase with segment drive for ‘off’ segment, 180o out of phase for ‘on’ segment. Frequency is 20 times conversionrate. Average DC component is less than 50mV.

5. Not tested, guaranteed by design.

FIGURE 1. ICL7106 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL-SCALE

FIGURE 2. ICL7107 TEST CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV FULL-SCALE

Electrical Specifications (Note 3) (Continued)

PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT

131 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20

2840 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21

V+

D1

C1

B1

A1

F1

G1

E1

D2

C2

B2

A2

F2

E2

D3

B3

F3

E3

AB

4

PO

L

OS

C 1

OS

C 2

OS

C 3

TE

ST

RE

F H

I

RE

F L

O

CR

EF+

CR

EF-

CO

M

IN H

I

IN L

O

A-Z

BU

FF

INT V-

G2

C3

A3

G3

BP

DISPLAY

DISPLAYC1 C2 C3

C4R3

R1

R4C5

+ -IN

R5

R2

9V

ICL7106

C1 = 0.1µFC2 = 0.47µFC3 = 0.22µFC4 = 100pFC5 = 0.02µFR1 = 24kΩR2 = 47kΩR3 = 100kΩR4 = 1kΩR5 = 1MΩ

131 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20

2840 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21

V+

D1

C1

B1

A1

F1

G1

E1

D2

C2

B2

A2

F2

E2

D3

B3

F3

E3

AB

4

PO

L

OS

C 1

OS

C 2

OS

C 3

TE

ST

RE

F H

I

RE

F L

O

CR

EF+

CR

EF-

CO

M

IN H

I

IN L

O

A-Z

BU

FF

INT V-

G2

C3

A3

G3

GN

D

DISPLAY

DISPLAYC1 C2 C3

C4R3

R1

R4C5

+ -IN

R5

R2

ICL7107

+5V -5V

C1 = 0.1µFC2 = 0.47µFC3 = 0.22µFC4 = 100pFC5 = 0.02µFR1 = 24kΩR2 = 47kΩR3 = 100kΩR4 = 1kΩR5 = 1MΩ

2-36

ICL7106, ICL7107

Typical Integrator Amplifier Output Waveform (INT Pin)

Design Information Summary Sheet• OSCILLATOR FREQUENCY

fOSC = 0.45/RCCOSC > 50pF; ROSC > 50KΩfOSC Typ. = 48KHz

• OSCILLATOR PERIODtOSC = RC/0.45

• INTEGRATION CLOCK FREQUENCYfCLOCK = fOSC/4

• INTEGRATION PERIODtINT = 1000 x (4/fOSC)

• 60/50Hz REJECTION CRITERIONtINT/t60Hz or tlNT/t60Hz = Integer

• OPTIMUM INTEGRATION CURRENTIINT = 4.0µA

• FULL-SCALE ANALOG INPUT VOLTAGEVlNFS Typically = 200mV or 2.0V

• INTEGRATE RESISTOR

• INTEGRATE CAPACITOR

• INTEGRATOR OUTPUT VOLTAGE SWING

• VINT MAXIMUM SWING:(V- + 0.5V) < VINT < (V+ - 0.5V), VINT typically = 2.0V

• DISPLAY COUNT

• CONVERSION CYCLEtCYC = tCL0CK x 4000tCYC = tOSC x 16,000when fOSC = 48KHz; tCYC = 333ms

• COMMON MODE INPUT VOLTAGE

(V- + 1.0V) < VlN < (V+ - 0.5V)

• AUTO-ZERO CAPACITOR0.01µF < CAZ < 1.0µF

• REFERENCE CAPACITOR0.1µF < CREF < 1.0µF

• VCOMBiased between Vi and V-.

• VCOM ≅ V+ - 2.8VRegulation lost when V+ to V- < ≅6.8V.If VCOM is externally pulled down to (V + to V -)/2,the VCOM circuit will turn off.

• ICL7106 POWER SUPPLY: SINGLE 9VV+ - V- = 9VDigital supply is generated internallyVGND ≅ V+ - 4.5V

• ICL7106 DISPLAY: LCDType: Direct drive with digital logic supply amplitude.

• ICL7107 POWER SUPPLY: DUAL ±5.0VV+ = +5.0V to GNDV- = -5.0V to GNDDigital Logic and LED driver supply V+ to GND

• ICL7107 DISPLAY: LEDType: Non-Multiplexed Common Anode

RINT

VINFSIINT

=

CINT

tINT( ) IINT( )

VINT=

VINT

tINT( ) IINT( )

CINT=

COUNT 1000VIN

VREF×=

AUTO ZERO PHASE(COUNTS)2999 - 1000

SIGNAL INTEGRATEPHASE FIXED1000 COUNTS

DE-INTEGRATE PHASE0 - 1999 COUNTS

TOTAL CONVERSION TIME = 4000 x t CLOCK = 16,000 x tOSC

2-37

ICL7106, ICL7107

Detailed DescriptionAnalog Section

Figure 3 shows the Analog Section for the ICL7106 andICL7107. Each measurement cycle is divided into threephases. They are (1) auto-zero (A-Z), (2) signal integrate(INT) and (3) de-integrate (DE).

Auto-Zero Phase

During auto-zero three things happen. First, input high andlow are disconnected from the pins and internally shorted toanalog COMMON. Second, the reference capacitor ischarged to the reference voltage. Third, a feedback loop isclosed around the system to charge the auto-zero capacitorCAZ to compensate for offset voltages in the buffer amplifier,integrator, and comparator. Since the comparator is includedin the loop, the A-Z accuracy is limited only by the noise ofthe system. In any case, the offset referred to the input isless than 10µV.

Signal Integrate Phase

During signal integrate, the auto-zero loop is opened, theinternal short is removed, and the internal input high and loware connected to the external pins. The converter thenintegrates the differential voltage between IN HI and IN LOfor a fixed time. This differential voltage can be within a widecommon mode range: up to 1V from either supply. If, on theother hand, the input signal has no return with respect to theconverter power supply, IN LO can be tied to analogCOMMON to establish the correct common mode voltage. Atthe end of this phase, the polarity of the integrated signal isdetermined.

De-Integrate Phase

The final phase is de-integrate, or reference integrate. Inputlow is internally connected to analog COMMON and inputhigh is connected across the previously charged referencecapacitor. Circuitry within the chip ensures that the capacitorwill be connected with the correct polarity to cause theintegrator output to return to zero. The time required for theoutput to return to zero is proportional to the input signal.Specifically the digital reading displayed is:

.

Differential Input

The input can accept differential voltages anywhere withinthe common mode range of the input amplifier, or specificallyfrom 0.5V below the positive supply to 1.0V above thenegative supply. In this range, the system has a CMRR of86dB typical. However, care must be exercised to assure theintegrator output does not saturate. A worst case conditionwould be a large positive common mode voltage with a nearfull-scale negative differential input voltage. The negativeinput signal drives the integrator positive when most of itsswing has been used up by the positive common modevoltage. For these critical applications the integrator outputswing can be reduced to less than the recommended 2V full-scale swing with little loss of accuracy. The integrator outputcan swing to within 0.3V of either supply without loss oflinearity.

DISPLAYCOUNT = 1000VIN

VREF

FIGURE 3. ANALOG SECTION OF ICL7106 AND ICL7107

DE-DE+

CINTCAZRINT

BUFFERA-Z INT

-+

A-Z

COMPARATOR

IN HI

COMMON

IN LO

31

32

30

DE- DE+INT

A-Z

34

CREF+

36

REF HI

CREF

REF LO

35

A-Z A-Z

33

CREF-

28 29 27

TODIGITALSECTION

A-Z AND DE (±)

INTEGRATOR

INT

STRAY STRAY

V+

10µA

V-

N

INPUTHIGH

2.8V

6.2V

V+

1

INPUTLOW

-+

-+

-+

2-38

ICL7106, ICL7107

Differential Reference

The reference voltage can be generated anywhere within thepower supply voltage of the converter. The main source ofcommon mode error is a roll-over voltage caused by thereference capacitor losing or gaining charge to stray capacityon its nodes. If there is a large common mode voltage, thereference capacitor can gain charge (increase voltage) whencalled up to de-integrate a positive signal but lose charge(decrease voltage) when called up to de-integrate a negativeinput signal. This difference in reference for positive ornegative input voltage will give a roll-over error. However, byselecting the reference capacitor such that it is large enoughin comparison to the stray capacitance, this error can beheld to less than 0.5 count worst case. (See ComponentValue Selection.)

Analog COMMON

This pin is included primarily to set the common modevoltage for battery operation (ICL7106) or for any systemwhere the input signals are floating with respect to the powersupply. The COMMON pin sets a voltage that is approxi-mately 2.8V more negative than the positive supply. This isselected to give a minimum end-of-life battery voltage ofabout 6V. However, analog COMMON has some of theattributes of a reference voltage. When the total supplyvoltage is large enough to cause the zener to regulate (>7V),the COMMON voltage will have a low voltage coefficient(0.001%/V), low output impedance (≅15Ω), and atemperature coefficient typically less than 80ppm/°oC.

The limitations of the on chip reference should also berecognized, however. With the ICL7107, the internal heatingwhich results from the LED drivers can cause somedegradation in performance. Due to their higher thermalresistance, plastic parts are poorer in this respect thanceramic. The combination of reference TemperatureCoefficient (TC), internal chip dissipation, and package ther-mal resistance can increase noise near full-scale from 25µVto 80µVp-p. Also the linearity in going from a high dissipationcount such as 1000 (20 segments on) to a low dissipationcount such as 1111(8 segments on) can suffer by a count ormore. Devices with a positive TC reference may requireseveral counts to pull out of an over-range condition. This isbecause over-range is a low dissipation mode, with the threeleast significant digits blanked. Similarly, units with anegative TC may cycle between over-range and a non-over-range count as the die alternately heats and cools. All theseproblems are of course eliminated if an external reference isused.

The ICL7106, with its negligible dissipation, suffers fromnone of these problems. In either case, an externalreference can easily be added, as shown in Figure 4.

Analog COMMON is also used as the input low return duringauto-zero and de-integrate. If IN LO is different from analogCOMMON, a common mode voltage exists in the systemand is taken care of by the excellent CMRR of the converter.However, in some applications IN LO will be set at a fixedknown voltage (power supply common for instance). In thisapplication, analog COMMON should be tied to the samepoint, thus removing the common mode voltage from the

converter. The same holds true for the reference voltage. Ifreference can be conveniently tied to analog COMMON, itshould be since this removes the common mode voltagefrom the reference system.

Within the lC, analog COMMON is tied to an N channel FETthat can sink approximately 30mA of current to hold thevoltage 2.8V below the positive supply (when a load is tryingto pull the common line positive). However, there is only10µA of source current, so COMMON may easily be tied to amore negative voltage thus overriding the internal reference.

FIGURE 4. USING AN EXTERNAL REFERENCE

TEST

The TEST pin serves two functions. On the ICL7106 it iscoupled to the internally generated digital supply through a500Ω resistor. Thus it can be used as the negative supply forexternally generated segment drivers such as decimal pointsor any other presentation the user may want to include onthe LCD display. Figures 5 and 6 show such an application.No more than a 1mA load should be applied.

FIGURE 5. SIMPLE INVERTER FOR FIXED DECIMAL POINT

ICL7106

V

REF LO

ICL7107

REF HI

V+

V-

6.8VZENER

IZ

ICL7106

V

REF HI

REF LO

COMMON

V+

ICL80691.2VREFERENCE

6.8kΩ

20kΩICL7107

FIGURE 4A.

FIGURE 4B.

ICL7106

V+

BP

TEST

21

37 TO LCDBACKPLANE

TO LCDDECIMALPOINT

1MΩ

2-39

ICL7106, ICL7107

The second function is a “lamp test”. When TEST is pulledhigh (to V+) all segments will be turned on and the displayshould read “1888”. The TEST pin will sink about 15mAunder these conditions.

CAUTION: In the lamp test mode, the segments have a constant DCvoltage (no square-wave). This may burn the LCD display if main-tained for extended periods.

FIGURE 6. EXCLUSIVE ‘OR’ GATE FOR DECIMAL POINT DRIVE

ICL7106

V+BP

TEST

DECIMALPOINT

SELECT

CD4030

GND

V+

TO LCDDECIMALPOINTS

Digital SectionFigures 7 and 8 show the digital section for the ICL7106 andICL7107, respectively. In the ICL7106, an internal digitalground is generated from a 6V Zener diode and a large P-channel source follower. This supply is made stiff to absorbthe relative large capacitive currents when the back plane(BP) voltage is switched. The BP frequency is the clock fre-quency divided by 800. For three readings/second this is a60Hz square wave with a nominal amplitude of 5V. The seg-ments are driven at the same frequency and amplitude andare in phase with BP when OFF, but out of phase when ON.In all cases negligible DC voltage exists across the seg-ments.

Figure 8 is the Digital Section of the ICL7107. It is identicalto the ICL7106 except that the regulated supply and backplane drive have been eliminated and the segment drive hasbeen increased from 2mA to 8mA, typical for instrument sizecommon anode LED displays. Since the 1000 output (pin 19)must sink current from two LED segments, it has twice thedrive capability or 16mA.

In both devices, the polarity indication is “on” for negativeanalog inputs. If IN LO and IN HI are reversed, this indicationcan be reversed also, if desired.

FIGURE 7. ICL7106 DIGITAL SECTION

7SEGMENTDECODE

SEGMENTOUTPUT

0.5mA

2.0mA

INTERNAL DIGITAL GROUND

TYPICAL SEGMENT OUTPUTV+

LCD PHASE DRIVER

LATCH

7SEGMENTDECODE

÷200

LOGIC CONTROL

INTERNALVTH = 1V

7SEGMENTDECODE

1000’s 100’s 10’s 1’s

TO SWITCH DRIVERSFROM COMPARATOR OUTPUT

DIGITALGROUND

÷4

CLOCK

40 39 38

OSC 1 OSC 2 OSC 3

BACKPLANE

21

V+

TEST

V-

500Ω

37

26

6.2V

COUNTER COUNTER COUNTER COUNTER

1

c

ab

cd

fg

e

a

b

ab

cd

fg

e

ab

cd

fg

e

†

† THREE INVERTERSONE INVERTER SHOWN FOR CLARITY

2-40

ICL7106, ICL7107

System Timing

Figure 9 shows the clocking arrangement used in theICL7106 and ICL7107. Two basic clocking arrangementscan be used:

1. An external oscillator connected to pin 40.

2. An R-C oscillator using all three pins.

The oscillator frequency is divided by four before it clocks thedecade counters. It is then further divided to form the threeconvert-cycle phases. These are signal integrate (1000counts), reference de-integrate (0 to 2000 counts) and auto-zero (1000 to 3000 counts). For signals less than full-scale,auto-zero gets the unused portion of reference de-integrate.This makes a complete measure cycle of 4,000 counts(16,000 clock pulses) independent of input voltage. For threereadings/second, an oscillator frequency of 48kHz would beused.

To achieve maximum rejection of 60Hz pickup, the signalintegrate cycle should be a multiple of 60Hz. Oscillatorfrequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz,40kHz, 331/3kHz, etc. should be selected. For 50Hz rejec-tion, Oscillator frequencies of 200kHz, 100kHz, 662/3kHz,50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5readings/second) will reject both 50Hz and 60Hz (also400Hz and 440Hz). FIGURE 9. CLOCK CIRCUITS

CLOCK

INTERNAL TO PART

40 39 38

GND ICL7107

÷4

CLOCK

INTERNAL TO PART

40 39 38

÷4

RC OSCILLATOR

R C

TEST ICL7106

FIGURE 8. ICL7107 DIGITAL SECTION

7SEGMENTDECODE

TOSEGMENT

0.5mA

8.0mA

DIGITAL GROUND

TYPICAL SEGMENT OUTPUTV+ LATCH

7SEGMENTDECODE

LOGIC CONTROL

7SEGMENTDECODE

1000’s 100’s 10’s 1’s

TO SWITCH DRIVERSFROM COMPARATOR OUTPUT

DIGITALGROUND

÷4CLOCK

40 39 38

OSC 1 OSC 2 OSC 3

V+

TEST

500Ω

COUNTER COUNTER COUNTER COUNTER

1

V+

37

27

c

ab

cd

fg

e

a

b

ab

cd

fg

e

ab

cd

fg

e

†

† THREE INVERTERSONE INVERTER SHOWN FOR CLARITY

2-41

ICL7106, ICL7107

Component Value SelectionIntegrating Resistor

Both the buffer amplifier and the integrator have a class Aoutput stage with 100µA of quiescent current. They cansupply 4µA of drive current with negligible nonlinearity. Theintegrating resistor should be large enough to remain in thisvery linear region over the input voltage range, but smallenough that undue leakage requirements are not placed onthe PC board. For 2V full-scale, 470kΩ is near optimum andsimilarly a 47kΩ for a 200mV scale.

Integrating Capacitor

The integrating capacitor should be selected to give themaximum voltage swing that ensures tolerance buildup willnot saturate the integrator swing (approximately. 0.3V fromeither supply). In the ICL7106 or the ICL7107, when theanalog COMMON is used as a reference, a nominal +2V full-scale integrator swing is fine. For the ICL7107 with +5Vsupplies and analog COMMON tied to supply ground, a±3.5V to +4V swing is nominal. For three readings/second(48kHz clock) nominal values for ClNT are 0.22µF and0.10µF, respectively. Of course, if different oscillator frequen-cies are used, these values should be changed in inverseproportion to maintain the same output swing.

An additional requirement of the integrating capacitor is thatit must have a low dielectric absorption to prevent roll-overerrors. While other types of capacitors are adequate for thisapplication, polypropylene capacitors give undetectableerrors at reasonable cost.

Auto-Zero Capacitor

The size of the auto-zero capacitor has some influence onthe noise of the system. For 200mV full-scale where noise isvery important, a 0.47µF capacitor is recommended. On the2V scale, a 0.047µF capacitor increases the speed of recov-ery from overload and is adequate for noise on this scale.

Reference Capacitor

A 0.1µF capacitor gives good results in most applications.However, where a large common mode voltage exists (i.e.the REF LO pin is not at analog COMMON) and a 200mVscale is used, a larger value is required to prevent roll-overerror. Generally 1.0µF will hold the roll-over error to 0.5count in this instance.

Oscillator Components

For all ranges of frequency a 100kΩ resistor is recom-mended and the capacitor is selected from the equation

f0.45RC

For48kHzClock(3Readings/second),=

C 100pF=

Reference Voltage

The analog input required to generate full-scale output (2000counts) is: VlN = 2VREF. Thus, for the 200mV and 2V scale,VREF should equal 100mV and 1V, respectively. However, inmany applications where the A/D is connected to atransducer, there will exist a scale factor other than unitybetween the input voltage and the digital reading. Forinstance, in a weighing system, the designer might like tohave a full-scale reading when the voltage from thetransducer is 0.662V. Instead of dividing the input down to200mV, the designer should use the input voltage directlyand select VREF = 0.341V. Suitable values for integratingresistor and capacitor would be 1 20kΩ and 0.22µF. Thismakes the system slightly quieter and also avoids a dividernetwork on the input. The ICL7107 with ±5V supplies canaccept input signals up to ±4V. Another advantage of thissystem occurs when a digital reading of zero is desired forVIN ≠ 0. Temperature and weighing systems with a variablefare are examples. This offset reading can be convenientlygenerated by connecting the voltage transducer between INHI and COMMON and the variable (or fixed) offset voltagebetween COMMON and IN LO.

ICL7107 Power Supplies

The ICL7107 is designed to work from ±5V supplies.However, if a negative supply is not available, it can begenerated from the clock output with 2 diodes, 2 capacitors,and an inexpensive l.C. Figure 10 shows this application.See ICL7660 data sheet for an alternative.

In fact, in selected applications no negative supply isrequired. The conditions to use a single +5V supply are:

1. The input signal can be referenced to the center of thecommon mode range of the converter.

2. The signal is less than ±1.5V.

3. An external reference is used.

FIGURE 10. GENERATING NEGATIVE SUPPLY FROM +5V

ICL7107

V+OSC 1

V-

OSC 2

OSC 3

GND

V+

V- = 3.3V

0.047µF

10µF

+

-

IN914

IN914

CD4009

2-42

ICL7106, ICL7107

Typical Applications

FIGURE 11. ICL7106 USING THE INTERNAL REFERENCE FIGURE 12. ICL7107 USING THE INTERNAL REFERENCE

28

40

39

38

37

36

35

34

33

32

31

30

29

27

26

25

24

23

22

21

OSC 1

OSC 2

OSC 3

TEST

REF HI

REF LO

CREF

CREF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V -

G2

C3

A3

G3

BP

100pF

TO PIN 1

SET VREF= 100mV

0.1µF

0.01µF

1MΩ

100KΩ

1KΩ 22KΩ

IN

+

-

9V47KΩ

0.22µF

0.47µF

TO BACKPLANE

TO DISPLAY

Values shown are for 200mV full-scale, 3 readings/sec., floatingsupply voltage (9V battery).

Values shown are for 200mV full-scale, 3 readings/sec. IN LO maybe tied to either COMMON for inputs floating with respect tosupplies, or GND for single ended inputs. (See discussion underAnalog COMMON.)

28

40

39

38

37

36

35

34

33

32

31

30

29

27

26

25

24

23

22

21

OSC 1

OSC 2

OSC 3

TEST

REF HI

REF LO

CREF

CREF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V -

G2

C3

A3

G3

GND

100pF

TO PIN 1

SET VREF= 100mV

0.1µF

0.01µF

1MΩ

100KΩ

1KΩ 22KΩ

IN

+

-47KΩ

0.22µF

0.47µF

TO DISPLAY

+5V

-5V

Typical ApplicationsThe ICL7106 and ICL7107 may be used in a wide variety ofconfigurations. The circuits which follow show some of thepossibilities, and serve to illustrate the exceptional versatilityof these A/D converters.

The following application notes contain very usefulinformation on understanding and applying this part and areavailable from Harris semiconductor.

Application NotesA016 “Selecting A/D Converters”

A017 “The Integrating A/D Converter”

A018 “Do’s and Don’ts of Applying A/D Converters”

A023 “Low Cost Digital Panel Meter Designs”

A032 “Understanding the Auto-Zero and Common ModePerformance of the ICL7106/7/9 Family”

A046 “Building a Battery-Operated Auto Ranging DVM withthe ICL7106”

A052 “Tips for Using Single Chip 31/2 Digit A/D Converters”

2-43

ICL7106, ICL7107

FIGURE 13. ICL7107 WITH AN EXTERNAL BAND-GAPREFERENCE (1.2V TYPE)

FIGURE 14. ICL7107 WITH ZENER DIODE REFERENCE

FIGURE 15. ICL7106 AND ICL7107: RECOMMENDED COMPO-NENT VALUES FOR 2.0V FULL-SCALE FIGURE 16. ICL7107 OPERATED FROM SINGLE +5V

Typical Applications (Continued)

28

40

39

38

37

36

35

34

33

32

31

30

29

27

26

25

24

23

22

21

OSC 1

OSC 2

OSC 3

TEST

REF HI

REF LO

CREF

CREF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V -

G2

C3

A3

G3

GND

100pF

TO PIN 1

SET VREF= 100mV

0.1µF

0.01µF

1MΩ

100KΩ

1KΩ 10KΩ

IN

+

47KΩ

0.47µF

TO DISPLAY

IN LO is tied to supply COMMON establishing the correct commonmode voltage. If COMMON is not shorted to GND, the input voltagemay float with respect to the power supply and COMMON acts as apre-regulator for the reference. If COMMON is shorted to GND, theinput is single ended (referred to supply GND) and the pre-regulatoris overridden.

10KΩ

1.2V (ICL8069)

V -

V +

-

0.22µF

Since low TC zeners have breakdown voltages ~ 6.8V, diode mustbe plasced across the total supply (10V). As in the case of Figure14, IN LO may be tied to either COMMON or GND

28

40

39

38

37

36

35

34

33

32

31

30

29

27

26

25

24

23

22

21

OSC 1

OSC 2

OSC 3

TEST

REF HI

REF LO

CREF

CREF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V -

G2

C3

A3

G3

GND

100pF

TO PIN 1

SET VREF= 100mV

0.1µF

0.01µF

1MΩ

100KΩ

1KΩ 100KΩ

IN

+

-47KΩ

0.22µF

0.47µF

TO DISPLAY

+5V

-5V

6.8V

28

40

39

38

37

36

35

34

33

32

31

30

29

27

26

25

24

23

22

21

OSC 1

OSC 2

OSC 3

TEST

REF HI

REF LO

CREF

CREF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V -

G2

C3

A3

G3

BP/GND

100pF

TO PIN 1

SET VREF= 100mV

0.1µF

0.01µF

1MΩ

100KΩ

25KΩ 24KΩ

IN

+

-470KΩ

0.22µF

0.047µF

TO DISPLAY

V+

V-

28

40

39

38

37

36

35

34

33

32

31

30

29

27

26

25

24

23

22

21

OSC 1

OSC 2

OSC 3

TEST

REF HI

REF LO

CREF

CREF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V -

G2

C3

A3

G3

GND

100pF

TO PIN 1

SET VREF= 100mV

0.1µF

0.01µF

1MΩ

100kΩ

1KΩ 10KΩ

IN

+

-47KΩ

0.22µF

0.47µF

TO DISPLAY

An external reference must be used in this application, since thevoltage between V+ and V- is insufficient for correct operation of theinternal reference.

15KΩ

1.2V (ICL8069)

+5V

2-44

ICL7106, ICL7107

FIGURE 17. ICL7107 MEASUREING RATIOMETRIC VALUES OFQUAD LOAD CELL

FIGURE 18. ICL7106 USED AS A DIGITAL CENTIGRADETHERMOMETER

FIGURE 19. CIRCUIT FOR DEVELOPING UNDERRANGE ANDOVERRANGE SIGNAL FROM ICL7106 OUTPUTS

FIGURE 20. CIRCUIT FOR DEVELOPING UNDERRANGE ANDOVERRANGE SIGNALS FROM ICL7107 OUTPUT

Typical Applications (Continued)

28

40

39

38

37

36

35

34

33

32

31

30

29

27

26

25

24

23

22

21

OSC 1

OSC 2

OSC 3

TEST

REF HI

REF LO

CREF

CREF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V -

G2

C3

A3

G3

GND

100pF

TO PIN 1

0.1µF

100KΩ

0.47µF

TO DISPLAY

The resistor values within the bridge are determined by the desiredsensitivity.

V+

0.22µF

47KΩ 28

40

39

38

37

36

35

34

33

32

31

30

29

27

26

25

24

23

22

21

OSC 1

OSC 2

OSC 3

TEST

REF HI

REF LO

CREF

CREF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V -

G2

C3

A3

G3

BP

100pF

TO PIN 1

0.1µF

0.01µF

100KΩ

100kΩ 1MΩ

9V47KΩ

0.22µF

0.47µF

TO BACKPLANE

TO DISPLAY

A silicon diode-connected transistor has a temperature coefficient ofabout -2mV/oC. Calibration is achieved by placing the sensingtransistor in ice water and adjusting the zeroing potentiometer for a000.0 reading. The sensor should then be placed in boiling waterand the scale-factor potentiometer adjusted for a 100.0 reading.

SCALEFACTORADJUST

100kΩ 220kΩ

22KΩ

SILICON NPNMPS 3704 ORSIMILAR

ZEROADJUST

13

1

2

3

4

5

6

7

8

9

10

11

12

14

15

16

17

18

19

20

V+

D1

C1

B1

A1

F1

G1

E1

D2

C2

B2

A2

F2

E2

D3

B3

F3

E3

AB4

POL

28

40

39

38

37

36

35

34

33

32

31

30

29

27

26

25

24

23

22

21

OSC 1

OSC 2

OSC 3

TEST

REF HI

REF LO

CREF

CREF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V-

G2

C3

A3

G3

BP

O /RANGE

U /RANGE

CD4023 OR74C10 CD4077

TO LOGICVCC

V+

TOLOGIC

V-

GND

O /RANGE

U /RANGE

CD4023 OR74C10

TO LOGICVCC

+5V

V-

33KΩ

The LM339 is required toensure logic compatibilitywith heavy display loading.

13

1

2

3

4

5

6

7

8

9

10

11

12

14

15

16

17

18

19

20

V+

D1

C1

B1

A1

F1

G1

E1

D2

C2

B2

A2

F2

E2

D3

B3

F3

E3

AB4

POL

28

40

39

38

37

36

35

34

33

32

31

30

29

27

26

25

24

23

22

21

OSC 1

OSC 2

OSC 3

TEST

REF HI

REF LO

CREF

CREF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V-

G2

C3

A3

G3

BP

12KΩ

+-

+-

+-

+-

2-45

ICL7106, ICL7107

FIGURE 21. AC TO DC CONVERTER WITH ICL7106

FIGURE 22. DISPLAY BUFFERING FOR INCREASED DRIVE CURRENT

Typical Applications (Continued)

28

40

39

38

37

36

35

34

33

32

31

30

29

27

26

25

24

23

22

21

OSC 1

OSC 2

OSC 3

TEST

REF HI

REF LO

CREF

CREF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V -

G2

C3

A3

G3

BP

100pF

TO PIN 1

0.1µF

100kΩ

1KΩ 22KΩ

47KΩ

0.22µF

0.47µF

TO BACKPLANE

TO DISPLAY

Test is used as a common-mode reference level to ensure compatibility with most op amps.

10µF

9V10µF

470KΩ

1µF

4.3KΩ

100pF(FOR OPTIMUM BANDWIDTH)

1µF10KΩ 10KΩ

1N914

1µF

0.22µF

5µFCA3140

2.2MΩ

+

-

100kΩ

AC IN

SCALE FACTOR ADJUST(VREF = 100mV FOR AC TO RMS)

ICL7107 130Ω

130Ω

130Ω

LEDSEGMENTS

+5V

DM7407