verilog lab5
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Veriolog
Furqan Farooq
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Introduction to Verilog
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Hardware Descriptive Languages
l HDL is used to represent and document
digital systems in a form that can be read
by both humans and computers and is
suitable as an exchange language
between designers.
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Hardware Description Language
Major languages:• Verilog
• Emphasis on practical use (I/O well-defined, ability to record)• Possibly most widely used
• VHDL• Department of Defense• Emphasis on abstraction
• Popular in academic circles, Europe; required of defense contr actors
• System C• Emphasis is “higher -level” simulation – really just a C++ template library
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Basic Limitation of Verilog
l Description of digital systems only
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Abstraction Levels in Verilog
Behavioral
Behavioral
Data Flow
Data Flow
Gate
Gate
Switch Level
Switch Level
Our focus
RTL
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Switch level
l This is the lowest level of abstraction
provided by Verilog. A module can beimplemented in terms of switches, storage
nodes, and the interconnections between
them. Design at this level requires
knowledge of switch-level implementationdetails.
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Gate level
l The module is implemented in terms of
logic gates and interconnections betweenthese gates. Design at this level is similar to
describing a design in terms of a gate-level
logic diagram.
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Dataflow level
l At this level, the module is designed by
specifying the data flow. The designer is
aware of how data flows between hardware
registers and how the data is processed in
the design.
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Behavioral or algorithmic level
l This is the highest level of abstraction
provided by Verilog HDL. A module can be
implemented in terms of the desired designalgorithm without concern for the hardware
implementation details. Designing at this
level is very similar to C programming.
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Principal Features of HDL
l Structurall Concurrent
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Structural
• Structural – describe designs as blocks
connected by signals
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Concurrent
l Concurrent – blocks execute concurrently
• Requires a “model of computation” to explain
concurrent behavior
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Applications
l Simulation
l
Synthesis
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Simulation vs. Synthesis
l HDLs are used for both simulation and synthesis
• Simulation: does the design work?
• Can also be used for “does the design meet timing?”
• Synthesis: generate a circuit that is equivalent
• Recognize state and combinational logic
• Optimize the circuit
l Not all valid HDL programs are synthesizable
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Data Values
• 4-valued logic: 0, 1, x, z
• 0, 1 – normal binary 0 and 1
• z – high-impedance value: this is what tri-state buffers drivewhen they are off
• x – simulator doesn’t know; sometimes used as “don’t care”
• At simulation start, all signals have x’s in every bit
• Unconnected inputs to a module have value ‘z’.
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Language Rules• Verilog is a case sensitive language (with a few exceptions)
• Identifiers (space-free sequence of symbols)upper and lower case letters from the alphabet
digits (0, 1, ..., 9 )underscore ( _ )
$ symbol (only for system tasks and functions)
Max length of 1024 symbols
• Terminate lines with semicolon
• Single line comments: // A single-line comment goes here
• Multi-line comments: /* Do not /* nest multi-line comments*/ likethis */
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Gate Level Modeling
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Example: AND Gate
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Example: Half Adder
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Primitives
• Verilog primitives encapsulate
pre-defined functionality of
common logic gates
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Primitives (Contd.)
l Verilog has 26 built-inprimitives
(combinational)
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Structural Modeling
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Design Encapsulation
• Encapsulate structural and functional detailsin a module
module my_design (module_ports);... // Declarations of ports go here
... // Structural and functional details go here
endmodule
• Encapsulation makes the model availablefor instantiation in other modules
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Example: AND OR INVERT
pp g p
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ANY QUESTION?????
pp g p
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Thanks!!!!
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