vlsi특론 semiconductor memory - yonsei...

Semiconductor Memory

Seong-Ook Jung2011. 4. 1.

[email protected]

VLSI SYSTEM LAB, YONSEI UniversitySchool of Electrical & Electronic Engineering

2 YONSEI Univ. School of EEE

Contents

1. Current Memory2. Future of NAND Flash3. Universal memory

1. PRAM 2. STT-MRAM

Current Memory


Memory Hierarchy

by Samsung electronics


Volatile vs. Non-Volatile Volatile memory

DRAM: fast speed, high density Main memory

SRAM: very fast speed, very low density Cache memory

Non-volatile memory NOR: very slow speed, low density

Program memory Flash: very slow speed, very high density

Storage memory


Charge Based vs. Resistance Based

Charge based device (Current memory) DRAM SRAM Flash

Resistance base memory (Future memory Universal memory) PRAM RRAM


SRAM

Intel processor ; Lynnfield

Layout of Lynnfield SRAM cell

Cache hierarchy in LynnfieldL1 ; 32KB (1core)L2 ; 256KB (1core)L3 ; 8MB (shared)


DRAM

SAMSUNG DDR3 4GB DRAM DRAM cell


DRAM Cell


Flash Memory

Samsung 256GB SSD

Flash memory cell

Samsung 32GB USB memory


Comparison

by Korea Institute of Science & Technology Information (KISTI)


Improve performance and capacity of DRAM and SRAM Technology scaling Design technique

Function and role of DRAM and SRAM are not changed. SRAM ; cache memory in processor DRAM ; main memory unit in system

DRAM and SRAM TrendBan

dw

idth

Year

1996 2000 2004 2008 2012

DDR3

DDR2

DDR

DRDRAM

XDR DRAM

DDR4

NGM diff?

SDRAM

by Intel Technology Journal


NAND Flash Trend Improve capacity and performance of NAND flash memory

Technology scaling Design technique

Positioning of NAND flash have been changed. Past ; digital camera, MP3, USB memory.. Recent ; solid state drive (SSD) for replacing HDD

0.1

1

10

100

Bit

Cos

t NAND

DRAM

SRAM

NOR

101 102 103 104 105 106

~1015 ~105

Endurance

Write Speed

Storage ClassStorage ClassMemory (SCM)Memory (SCM)

UniversalUniversalMemoryMemory

**IBMIBM

STT-MRAM

3D ReRAM

PRAM

PRAM


Future of NAND Flash


Invention of NAND Flash

by Toshiba, IEDM, 1988by Toshiba, Flash handbook, 1992


Application I / Flash Cards

Digital camera

Cellular phoneCar navigation

PCPortable Video game

Flash card is used for mobile devices with memory slot


Application II / Embedded Application

8GB Flash

MP3 player

E-Book


Application III / Contents Preloaded Media


Application IV / SSD

Samsung 256GB SSD

SATA interfacecompatibility


Evolution of NAND Flash Technology



Limitation of NAND Beyond 30nm, Uncertainty of EUV Availability Limit of Patterning Beyond 20nm, Uncertainty of Conv. Linear Scaling Limit of Device Super-MLC (3-bit, 4-bit, etc.), High Speed I/F, 3D Technology

11970 1980 1990 2000 2010

100

1000

1970 1980 1990 2000 2010

10

2020

NA

ND

Tec

hnol

ogy

Nod

e ( n

m ) G-line

436nmI-line365nm

KrF248nm

ArF193nm

EUV ?13.5 nm

Year

ConventionalLinear Scaling ?

Litho. Tool ?

203011970 1980 1990 2000 2010

100

1000

1970 1980 1990 2000 2010

10

2020

NA

ND

Tec

hnol

ogy

Nod

e ( n

m ) G-line

436nmI-line365nm

KrF248nm

ArF193nm

EUV ?13.5 nm

Year

ConventionalLinear Scaling ?

Litho. Tool ?

2030

DPT



High Speed Interface (DDR) NAND

by Micron-Intel, ISSSC, 2008

20ns

10ns

200MB/s100MB/s

ONFI (Open NAND Flash Interface): Intel, Micron, Hynix, etc. Toggle-mode NAND: Samsung, Toshiba


3D NAND for Tera-bit Storage

by Toshiba, IEDM, 2007 by Toshiba, VLSI, 2007

3D Vertical NAND High Density Oriented, CTF, MLC


SDD vs. HDD

Low weightHigh performanceLow powerLow vibration

Low noiseLow endurance

However, high cost per capacity, now by Samsung electronics


Component of SSD


Performance = f(CPU, DRAM, Flash, Host Interface, HW automation)


SSD / Solving the I/O BottleneckSp

eed/

Thro

ughp

uts

1980 1985 1990 1995 2000 2005 2010

10GHz

1GHz

100MHz

10MHz 1993: EDO, 33MHz

2001: DDR266

2004: DDR2-533

2007: DDR3-1067

1985: FP, 13MHz

2010: Future, 1600

1997: SDR, 133MHz

1994: SDR, 66MHz

2005: P4, 3.8GHz

1982: 286, 6MHz

1985: 386, 16MHz

1993: P, 66MHz

1997: PII, 300MHz

1999: PIII, 500MHz

2000: P4, 1.5GHz

2003: P4, 3GHz

1989: 486, 25MHz

(52MB/s)

(132MB/s)

(528MB/s)

(1GB/s)

(2.1GB/s)

(4.2GB/s)

(8.5GB/s)

2000: ATA5 (20/66 MB/s)

2005: SATA3G (50/300 MB/s)

2008: SATA6G (100/600 MB/s)

2003: SATA1.5G (40/150 MB/s)

CPUDRAMHDD (12.8GB/s)

1998: ATA4(10/33 MB/s)1996: ATA2

(5/16 MB/s)

2002: ATA6(30/100 MB/s)

2006: Core Duo2006: Quad Core

Year

SSD

Bridge Performance Gap between CPU and HDD



SSD / Solving the Power Bottleneck

HDD: Higher RPM = Higher Power + Generates more Heat SSD: Less Power /No Heat saves lifetime Energy Costs…

Watts used in Operation Mode Watts used in Idle Mode

HDD RPM HDD RPM



Wear-leveling for Optimization

0

500

1000

1500

2000

2500

3000

3500

4000

1 77 153 229 305 381 457 533 609 685 761 837 913 989

W ith wear-level W ithout wear-level

Physical Block Address

P/ECycling

Wear-leveling by FTL (Flash Controller)

SSD

MP3, USB, DSC etc. SSD

Dynamic Wear-leveling Static Wear-leveling



Sector Size for Optimization

by K. Takeuchi, ISSCC Forum, 2008

Existing OS is for HDD! OS should be optimized for SSD!!!


Self-monitoring, Analysis and Reporting Technology

by K. Takeuchi, ISSCC Forum, 2008

SMART(Self-Monitoring, Analysis andReporting Technology)

Future Memory (Universal Memory)


Universal Memory

Universal memory is desired for next-generation memory. Nonvolatile memory High speed High density High endurability Low power

Some candidates PRAM STT-MRAM FeRAM ReRAM …….

0.1

1

10

100

Bit

Cos

t

NAND

DRAM

SRAM

NOR

101 102 103 104 105 106

~1015 ~105

Endurance

Write Speed

Storage ClassStorage ClassMemory (SCM)Memory (SCM)

UniversalUniversalMemoryMemory

**IBMIBM

STT-MRAM

3D ReRAM

PRAM

PRAM

UniversalMemory



Power Dissipation of IT Equipments

In 2025, Power dissipation will reach 5 times larger.

by T. Kawahara, IEEE ED/SSC Mini-Colloquium, 2009


Normally OFF, Instant ON

Normally OFF

Instant ON

Read operation ; sensing resistance of GST Voltage biased to GST must to limited under Vth to prevent disturb. Current sensing scheme

Appling read voltage to cell converts from resistance to current Load device converts from current to voltage Sense amplifier converts from analog voltage value to digital output



Change Memory Configuration Nonvolatile RAM enhances user’s convenience. Instant ON. Quickly software changing.



Nonvolatile (NV) RAM Application

Innovation for low power system including hardware, software, and architecture



Impact on Performance Power ON time is improved to 1/9. Nonvolatility achieves low power also.



Impact on Power High-end cellular phone with large memory with low stand-

by power (1/10).


Universal Memory IPRAM


Structure of PRAM Cell



Write Operation of PRAM

Reset pulse (strong & short) ; Amorphous state (~100kΩ) Set pulse (weak & long) ; Crystalline state (kΩ)

by KIST, 대한전자공학회, 2005


Read Operation of PRAM Read operation ; sensing resistance of GST Voltage biased to GST must to limited under Vth to prevent disturb. Current sensing scheme

Appling read voltage to cell converts from resistance to current Load device converts from current to voltage Sense amplifier converts from analog voltage value to digital output

by KIST, 대한전자공학회, 2005


Recent Technical IssuesReducing Required RESET Current

Reducing BEC

Confined contact

Increasing heat by increasing current density→ reducing IRESET

Increasing heat by increasing current density→ reducing IRESET

by Samsung Electronics, Sym. VLSI Tech., 2007


Recent Technical IssuesReducing Required RESET Current

Impurity doping

Reset Current Regime

Reducing IRESET

Increasing GST resistance→ increasing heat→ reducing IRESET

by Samsung Electronics, Sym. VLSI Tech., 2007


Recent Technical IssuesObtaining Larger RESET Current

Enhancing current driving capability Vertical BJT

by Samsung Electronics


History of PRAM

by T. Kawahara, ASP-DAC Non-volatile Memory, 2011


Future of PRAM

When ?? 2011 ? Samsung and Micron expect to possess technology to mass-produce

512Mb~1Gb PRAM. Absence of alternative market is obstacle of commercialization of PRAM. Samsung or Micron may launch PRAM in 2011.

Target !! NOR Flash !! Recently, improvement of NOR flash disturbs commercialization of PRAM. Main product of NOR flash is 256, 512Mb and uses for embedded system.

Future !! SSD drive System that don’t need booting

Universal Memory IISTT-MRAM


MTJ Device StructureMTJ

• Two magnetic layer(Free and pinned layer)• Insulating layer(Tunnel barrier)

RMTJ ; depends on the state of free layer

State Effective resistance

Parallel 0 Low (R0)

Anti-Parallel 1 High (R1=R0*(1+MR))

(MR ; magnetoresistance)

Reading operation

Writing operation

Reading resistance of MTJ

Switching free layer of MTJ


Write Operation of Conventional MRAM

Applied Magnetic Fields

State Change

< State change >

< Half selection issue >

< Applied magnetic field >

Selected CellSelected BL

Selected WL

Write 0

(a)

(b)

Half-select

Selected BL

Write 1

Hy(word line)

Hx(bit line)

Selected WL70

60

50

40

30

20

10

0

-200 -100 0 100 200Applied magnetic field (Oe)

Res

ista

nce

chan

ge (%

) 1

0

T. M. Maffitt, et al., IBM J., 2007


Write Operation of STT-MRAM

writing 1

writing 0

Spin-polarized electron

< Parallelizing and Anti-Parallelizing Current>

(c) R-I Characteristics

(a) “0” Write (Parallelizing)

(b) “1” Write (Anti-Parallelizing)

SNNS

N SNS

by T. Kawahara, et al., ISSCC, 2007


Conventional MRAM vs. STT-MRAM

STT-MRAM has good potential in scalability due to Write current.

Conventional MRAM STT-MRAMby Samsung electronics


Recent Technical IssuesReducing Required Critical Current

Research Group

ConferenceMTJ size

(diameter)Criticalcurrent

Switchingtime

Toshiba IEDM2008 55nm49uA (AP-P)100uA (P-AP)

4ns

Critical current (IC) of P-ST is dependent on MTJ size. (opposite result compared with page 2)IC=49uA

Perpendicular MTJ TMR element with perpendicular magnetic anisotropy (P-TMR) Lower critical current than I-TMR

by T. Kishi, et al., IEDM, 2008


Recent Technical IssuesObtaining Larger Write Current

To minimize the cell area, the isolation area between a cell and an adjacent cell is replaced by the adjacent cell’s transistor; the “off” state of the channel region of the adjacent cell can insulate electrically among memory cells.

2 Transistor – 1 MTJ (2T1MTJ) cell structure

by R. Takemura, et al., Symposium on VLSI circuits, 2009

Larger write current with same area


Full adder with nonvolatile input B• Dynamic logic type• Dynamic power can reduced to 23%

Nonvolatile Flip-flop• Cross-coupled inverter latch type• Standby power can reduced to 0%

NEW Application using MTJSpintronics Logic

Recently, nonvolatile logic using MTJ had been studied.Highly expected for LSI advancement and innovation.

by Shoun Matsunage, et al., Applied Physics Express, 2008

by Noboru Sakimura, et al., CICC, 2008


Power Reduction by STT-MRAM and Spintronics Logic

Keep normally the equipment turned off. Power consumption adjusted to one third.

Conventional structure

with STT-MRAM

with STT-MRAM and Spintronics logic



History of STT-MRAM

by T. Kawahara, ASP-DAC Non-volatile Memory, 2011


Conclusion The density and performance of flash memory have been improved by

improvement of process and design technology. Solid state drive (SSD) is remarkable as alternate storage device. As cost per

capacity decreases, SDD will replace HDD, gradually. Advantage of SSD

Low power High performance No noise & vibration Low heat

Next generation memory had been studied for overcoming current memory. (PRAM, STT-MRAM, …)

Requirement for universal memory Nonvolatile Low power High performance High density

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