vlsi_lecture02_openidea(정무경).ppt

7/27/2019 VLSI_Lecture02_OpenIDEA( ).ppt

1/69

OpenRISC-Based Embedded

System Design

Dynalith Systems

www.dynalith.com

April. 3, 2007


2/69

Introduction ( 2 )

Agenda

Introduction to OpenCores

OpenRISC Architecture

OpenIDEA

Example


3/69

Introduction ( 3 )

Introduction to OpenRISC

OpenRISC

Free open-source synthesizable RISC processor

Distributed by OpenCores, http://www.opencores.orgOpenRISC 1000 (or1k)

Target

medium and high performance networking and embedded computer environments

Architecture

32/64-bit load/store RISC architecture

Designed with emphasis on performance, simplicity, low power requirements and scalabilityArchitecture Definition

Instruction set, register set, cache management & coherency, memory model, exception model,

addressing mode, operands conventions, application binary interface

Not define implementation-specific details

Pipeline depth, cache organization, branch prediction, instruction timing, bus interface

Reference: OpenRISC 1000 Architecture Manual
http://www.opencores.org/http://www.opencores.org/


4/69

Introduction ( 4 )

OR1K Architecture Overview

Address space 32-bit or 64-bit logical address space

Instruction

Simple and uniform-length instruction

Different instruction set extensions

- ORBIS 32/64 (OpenRISC Basic Instruction Set)

32-bit wide, operating on 32- and 64-bit data

- ORDVX64 (OpenRISC Vector/DSP eXtension)

32-bit wide, operating on 8-, 16-, 32- and 64-bit data

- ORFPX32/64 (OpenRISC Floating-Point eXtension)

32-bit wide, operating 32- and 64-bit data

ArchitectureSeparate instruction and data cache/MMU (Harvard architecture)

Unified instruction and data cache/MMU (Stanford architecture)

Memory addressing Addition of a register operand and a signed 16bit immediate

Instruction operands Two source register operands (or one register and a constant) and one result register

Branch Branch delay slot for keeping the pipeline as full as possible

Context switch Fast context switch support in register set, caches and MMUs


5/69Introduction ( 5 )

OpenRISC 1000 implementations

OR1200

Entry level 32bit RISC processor

I/D Cache, I/D MMU, Tick timer, PIC, Debug

Internet appliances, Networking, Handheld

OR1100

Entry level 32bit DSP

I Cache, Tick timer, PIC, Debug

VoIP, Modems, Imaging

OR1400

High performance superscalar 64bit RISCI/D Cache, I/D MMU, Tick timer, PIC, Debug, FPU,

Vector/DSP

Telecom, Home entertainment

OR1500

A limited configuration

SystemC implementation

OpenRISC 1 2 0 0

How theimplementation is

configured

Which features areimplemented

OpenRISC 1000family

OpenRISC 1000

architecture 32/64-bit

OpenRISC 1200

32/-bitOpenRISC 1x00



OpenRISC 1200

An implementation of OR1K architecture

32-bit scalar RISC

ORBIS32 instruction setHarvard micro-architecture

Five-stage integer pipeline

Virtual memory support (MMU)

Separated IMMU and DMMU

Separated I-cache and D-cache

Including ComponentsDebug unit

Tick timer

Programmable interrupt controller

Power management

Performance

250 MIPS Dhrystone 2.1 @ 250Mhz wc

250 MMAC operations @ 250Mhz wc



OpenRISC 1200

POWERMPM

I/F

DEBUG

DB

I/F

TICK TIMER

PICINT

I/F

IMMU

WB

IICache

8KB

DCache

8KBWB

I

DMMU

CPU/DSP

System I/FOpenRISC 1200

L1 CachesI/D Cache (1 to 8 KB)

1-way direct-mapped cache

MMUWith 1-way direct-mapped TLBHarvard model

TLB, 16 to 64 entries

Power ManagementPower save modes

Software controlled clock frequency

Interrupt wake-up

Dynamic clock gating for individual units

Interrupt Controller

30 maskable interrupt sourcesTick Timer

Task scheduling

Time measurement

Interrupt generation

Single-run, restartable or continuous mode

Debug UnitJTAG Test Access Port

Non-intrusive Realtime debug/trace for both CPU and

SystemAccessible via development interface

Links into GDB

Reference: OpenRISC 1200 IP Core Specification



OpenRISC 1200, Leon 2, MicroBlaze



Architecture Details

Register Set

Instruction Set

Exception Model

Memory Model

Memory Management

Cache

Debug Unit

Performance Counter Unit

Power Management

Timer/PIC

Application Binary Interface



Register Set

Register set

Thirty-two or sixteen 32/64-bit general purpose

registers

All other registers are special purpose registers

User-level/supervisor-level register

Multiple sets of GPRs (not implemented in or1200)

Special-purpose registers

32 groups, up to 2048 registers in a group

l.mtspr/l.mfspr instruction

Group # Description

0 System control/status1 Data MMU

2 Instruction MMU

3 Data cache

4 Instruction cache

5 MAC unit

6 Debug unit

7 Performance counter

8 Power management

9 PIC

10 Tick timer

11 Floating point unt

12-23 Reserved

24-31 Custom unit

Special purpose registers

Reference: OpenRISC 1000 Architecture Manual


11/69

Introduction ( 11 )

Instruction Set

Simple and uniform-length instruction format

ORBIS32 (or1200)

32-bit wide, 32-bit boundary aligned, 32-bit data

operation32-bit integer instructions

Basic DSP instructions

32-bit load/store instructions

Program flow instructions

Special instructions

ORBIS64

32-bit wide, 32-bit boundary aligned, 64-bit dataoperation

64-bit integer instructions

64-bit load/store instructions

ORFPX32


Single-precision floating-point instructions

ORFPX64


Double-precision floating-point instructions64-bit load/store instructions

ORVDX64

32-bit wide, 32-bit boundary aligned, 8-, 16-, 32-,64-bit data operation

Vector instructions

DSP instructions

Reserved opcodes for custom instructions


12/69

Introduction ( 12 )

Instruction Set

prefix

Precision/datawidthd : doubles : singleb : byte

h : half-wordn : nibble

Instruction

Instruction setl : ORBSISlf : ORFPXlv : ORVDX

instruction postfix. .

Or1200 Implementation

Arithmetic/

logical

l.add/l.addc/l.addi

l.sub

l.mul/l.Mulu

l.and/l.andi

l.or/l.ori

l.rori

l.sll/l.slli/l.sra/l.srai/l.srl/l.srli

l.xor/l.Xori

Branch l.bf/l.bnf

l.j/l.jal/l.jalr/l.jr

l.Rfe

Load

/Store

l.lbs/l.lbz/l.lhs/l.lhz/l.lws/l.lwz

l.sb/l.sh/l.sw

Flag l.sfeq/l.sfne

l.sfges/l.sfgeu/l.sfgts/l.sfgtu

l.sfles/l.sfleu/l.sflts/l.sfltu

Register l.mfspr/l.mtspr

l.movhi

Exception l.trap/l.sys

Etc. l.Nop


13/69

Introduction ( 13 )

Exception Model

Reset vector

0x100

Bus errorCaused by a bus interface error

Bus error

Instruction/Data page fault

Caused by access to an invalid virtual

address

Segmentation faultAlignment

Caused by not aligned access

Bus error

Range

Caused by not available register access


14/69

Introduction ( 14 )

Memory Model

Weakly ordered memory model

High performance memory system

Responsibility for strict access ordering on programmerMemory synchronization instruction

l.msync : complete of all load/store operations before the RISC core continues

Or1200 implementation

Strongly ordered memory model

Atomicity

Atomic memory access instructionsl.lwa, l.swa

Or1200 implementation

Not intended for use in multiprocessor environments

No support for coherency between local data cache and caches of other processors ormain memory

Write-through cache


15/69

Introduction ( 15 )

Memory Management

Support for implementation specific size of physical address spaces up to 35address bits (32 GByte)

Three different page sizes:Level 0 pages (32 Gbyte; only with 64-bit EA) translated with D/I Area TranslationBuffer (ATB)

Level 1 pages (16 MByte) translated with D/I Area Translation Buffer (ATB)

Level 2 pages (8 Kbyte) translated with D/I Translation Lookaside Buffer (TLB)

Address translation using one-, two- or three-level page tables

Powerful page based access protection with support for demand-paged virtualmemory

Support for simultaneous multi-threading (SMT)

OR1200 implementation

Only level 2 paging is implemented.


16/69

Introduction ( 16 )

Memory Management

OpenRISC 1000 Specification

32-bit implementation

64-bit implementation


17/69

Introduction ( 17 )

Memory Management


Level 3 paging implemented

1-way direct mapped TLB

TLB Tag

(13(12)-bit)

Page Offset

(13-bit; 8KB)

31 13 12 0

TLB

Match Register

TLB

Translate Register

13

Virtual Page Number (VPN)

19(20)31

TLB Index

(7(8)-bit; 64(128)-entry)

Tag (13(12)-bit) V Physical PN (19-bit) swe

0114(13)

sre uwe ure ci

01331

?

Hit/Miss

Page Offset

(13-bit)

13 12 0

Physical Page Number

(19-bit)

31

64(128)

-entry

64(128)

-entry

Physical Address


18/69

Introduction ( 18 )

Cache

Cache

1-way direct-map

Up to 8KB for each I/D cacheCache control

Block prefetch

Block flush

Block invalidate

Block write-backBlock lock

Or1200 cache implementation

Write-through mode

No support for coherency

No prefetch

No support for cache line lock


19/69

Introduction ( 19 )

Quick Memory

Quick memory

On-chip memory

Unified I&D memory

LSU D-MMU

QMEM

D-Cache

I-MMU I-CacheGenPC

Store

BufferData BIU

Data BIU

Virtual

Addr.

VirtualAddr

Physical

Addr.

PhysicalAddr

Inst.

Data


20/69

Introduction ( 20 )

Debug Unit

Eight sets of debug value/compare registers

Match signed/unsigned conditions on

instruction fetch EAload/store EA

load/store data

Combining match conditions for complex watchpoints

Watch-points can be counted by Performance Counters Unit

Watch-points can generate a breakpoint (trap exception)Counting watch-points for generation of additional watch-points


21/69

Introduction ( 21 )

Debug Unit

Registers

DVR (Debug Value Register)

DCR (Debug Control Register)

Compare target

Compare condition

DMR (Debug Mode Register)

WP/BP setting

Combination of conditions of DVRs

DWCR (Debug Watch-point Counter

Register)DSR (Debug Stop Register)

Core stop condition

DRR (debug Reason Register)


Breakpoint but no watchpoint


22/69

Introduction ( 22 )

Performance Counter Unit

Benefits

To improve performance by developing better application level algorithms,

To better optimized operating system routines

For improvements in the hardware architecture of these systems

To improve future OpenRISC implementations

To add future enhancements to the OpenRISC architecture.

To help system developers debug and test their systems.

Performance counter

Eight countersCounting predefined events

Load/store/instruction fetch

I/D-cache miss

LSU/branch/instruction fetch/data dependency stall

I/D-TLB miss

Watch point

Not implemented in OR1200


23/69

Introduction ( 23 )

Power Management

Slow down

Support 0~15 clock frequency level

Need external clock synthesizer

Power mode (dynamic clock gating, dynamic voltage scaling)

Normal mode

Doze mode

All disabled (clock gating) except tick timer and PIC

Enter normal mode by timer or interrupt

Sleep mode

All disabled (clock gating) and voltage down except PIC

Enter normal mode by interrupt

Suspend mode

All disabled (clock gating) and voltage down

Enter normal mode by reset

OR1200

Power manager implemented

But no clock gating implemented


24/69

Introduction ( 24 )

Overall Blocks

LSU

D-MMU

QMEM

D-Cache

I-MMU I-Cache

GenPC

Store

BufferData BIU

Inst. BIU

Virtual

Addr.

Virtual

Addr

Physical

Addr.

Physical

Addr

Inst.

Data

PIC

Timer

Power

Manager

Debug

Unit

Inst.

Fetch

Register

File

ALU

Operand

MUX

Multiplier

MAC

SPR

Freeze

Except

Write-back MUX

Control Logic

(decode)

C fi bl F t


25/69

Introduction ( 25 )

Configurable Features

Supporting FPGA XilinxOn-chip memory

AlteraInstruction cache 1-way 512-bytes

1-way 4K-bytes

1-way 8K-bytes

No

Data cache 1-way 4K-bytes

1-way 8K-bytes

No

Instruction MMU 64-entry TLB

128-entry TLB

No

Data MMU 64-entry TLB

128-entry TLB

No

BIST RAM BIST

No

C fi bl F t


26/69

Introduction ( 26 )


Burst bus interface On

OffBus retry count 1~256

WISHBONE Prior to WISHBONE B.3

CAP (consecutive address burst)

(prior to B.3)

WISHBONE B.3

Divider OnOff

Rotate On

Off

Multiplier Fast

Slow

Off

MAC On

Off

Multiplier On

Off

C fi bl F t


27/69

Introduction ( 27 )


Clock divide 1 or 2 or 4

Register file Two port RAM

Dual Port RAM

Flip-flop based register

Debug unit HW break point On/Off

# of DVR/DCR pair 0~7

Trace buffer On

OffPIC # of interrupt (2~31)

Off

No

Tick timer 64-entry TLB

128-entry TLB

No

Qmem On

Off

Store buffer Entry 4 or 8

No

C t I t ti


28/69

Introduction ( 28 )

Custom Instruction

Reserved instructions for custom implementation

ORBIS32/64

Eight instructions are reservedl.cust1 ~ l.cust8

ORFPX64

Two instructions are reserved

lf.cust1.d, lf.cust1.s

ORVDX64

Eight instructions are reservedlv.cust1 ~ lv.cust8

Custom instruction implementation

Add decode logic for the instruction (or1200_ctrl.v)

Add processing logic for the instruction (or1200_alu.v)

Development Tools


29/69

Introduction ( 29 )

Development Tools

Development Tool Name Version

Compiler gcc 3.4.4 GNU compiler

Binary utility binutils 2.16.1 GNU binary utilities

C library newlib 1.10.0 GNU C library

Architecture simulator or1ksim 0.2.0 Or100 ISS with peri.models

Debugger gdb 5.3 GNU source level

debugger

GUI insight GUI

Operating System


30/69

Introduction ( 30 )

Operating System

Operating System Name Version

Linux Linux Kernel 2.4

uClinux uClinux 2.0

RTEMS RTEMS 4.5.0 Hard real-time OS

ecos ecos 2.0

Reference Platform/Example


31/69

Introduction ( 31 )

Reference Platform/Example

Etc. Name Version

SoC platform orp_soc SoC reference platform

Monitor program orpmon

MP3 decoder mad-xess MAD MP3 player porting

GUI Microwindows

examples Various simple

examples

Outline


32/69

Introduction ( 32 )

Outline

Software Development with OpenIDEA

Software Development

Architecture SimulationHardware Development with iNSPIRE-Lite

Hardware/Software Co-Verification with OpenIDEA

Verification Flow



33/69

Introduction ( 33 )


SourceBrowser CodeEditor

Compiler

Window



34/69

Introduction ( 34 )


Platform

Windows 2000/XP

Target Processor

or1200

Code Editor

Source Browser

Syntax Highlighting

Syntax Checking

Block Indent/Dedent/FoldingComment out/uncomment

Line Number

Find/Replace/Find in Files



35/69

Introduction ( 35 )


Compiler

gcc 3.4.4

Utilities

binutil 2.16.1

make

bin2c

bin2hex

bin2flash

bin2srec

Newlib

1.10.0



36/69

Introduction ( 36 )


Startup Code

Link Script File

Architecture Simulation

S L l D b i


37/69

Introduction ( 37 )

Source-Level Debugging

OpenIDEAOpenIDEA

Socket

Debug

Windows

Source-Level

Debugger

ISS: Architecture SimISS: Architecture Sim

Processor Model

SRAM Model

Flash Model

Peripheral Models

C Models



38/69

Introduction ( 38 )

Source Level Debugging

SourceBrowser

Register

Code

Watch Stack

Debugger Break Point



39/69

Introduction ( 39 )

Source Level Debugging

Debugger

gdb 5.0

C Source-Level Debugging

Break

Step

Watch, etc.

Assembly-Level Debugging

Instruction Step

Register View, etc.

Architecture Simulation


40/69

Introduction ( 40 )

Processor Architecture Exploration

Core

MMU

Cache, etc.

System-Level Simulation with Peripheral

Models

Memory

UART

Ethernet

VGA, etc.

Performance Profiling

Execution Log

Memory Profile, etc.

Agenda


41/69

Introduction ( 41 )

g


Hardware Development with iNSPIRE-Lite

Automatic Hardware CompositionOpen-Source Library

Simulation/Synthesis/Prototyping

Hardware/Software Co-Verification with OpenIDEA

Verification Flow

iNSPIRE


42/69

Introduction ( 42 )

EDIF

HDLHDL

HDL

EDIFEDIF

Library

HDL SimuilationEnvironment

Synthesis &

Mappnig(for FPGA)

Cycle-Level &

Transaction -LevelCo-Simuilation

Environment

Integrated Design Environment for Hardware DevelopmentArchitecture Exploration

Generation ofHDL Simulation Environment

SystemC Simulation Environment

Synthesis & FPGA MappingCycle-Level & Transaction-Level Co-Simulation Environment

Supporting Various Library

Architecture-Wizard


43/69

Introduction ( 43 )

LEGO-Brick-Like Hardware Composition

GUI-Based Hardware Composition

Various IP Library

Open Source IP

Architecture Exploration

IP Properties

Architecture-Wizard


44/69

Introduction ( 44 )

Bus Generation

AMBA AHB

AMBA APB

WISBHBONE

Bus Architecture Exploration

Bus Architecture

Address Map

Priority, etc.

IP Library


45/69

Introduction ( 45 )

OpenCores Library

License (L)GPL

OR1200

OR1200 Debug

Audio

Video

Ethernet

CAN

DMA

PS2, etc.

Dynalith Library

FLASH Controller

SRAM Controller

JTAG to USB, etc.

IP Library


46/69

Introduction ( 46 )

RTL Source

Synthesis Script

Example

Hardware

Software

Simulation/Synthesis


47/69

Introduction ( 47 )

Simulation Environment

Top Module Generation

Simulation Model Connection

SRAM, SDRAM, UART, etc.

Simulation Script

Synthesis

Top Module Gereration

Synthesis Script

Synthesis Assist

FPGA P&R

FPGA Mapping Script

P&R Assist

Simulation

Synthesis

Emulation

Agenda


48/69

Introduction ( 48 )


Hardware Development with iNSPIRE-Lite

Hardware/Software Co-Verification with OpenIDEADebugger + ISS

Debugger + ISS + HDL Simulator (SystemC)

Debugger + ISS + HDL Simulator + FPGA

Debugger + HDL Simulator (+ FPGA)

Debugger + FPGA Prototyping

Debugger + ASIC

Verification Flow

1. SW Simulation


49/69

Introduction ( 49 )

OpenIDEA (Debugger+ISS)


OpenIDEAOpenIDEA

Socket

Debug

Windows

Source-Level

Debugger

ISSISS

Processor Model

SRAM Model

Profile/Log

Flash Model

UART Model

TerminalTerminal

Hello World.SocketC Models

2.1 HW/SW Co-Simulation (IP Verification)


50/69

Introduction ( 50 )

( )OpenIDEA (Debugger+ISS) + Third Party HDL Simulator

IP Verification

Device Driver Development

OpenIDEAOpenIDEA

Socket

Debug

Windows

Source-LevelDebugger

ISSISS

Processor Model

SRAM Model

IP1

C Models

HDL Sim.HDL Sim.

IP2

IP3

Socket

2.2 HW/SW Co-Simulation (System-Level)


51/69

Introduction ( 51 )

OpenIDEA (Debugger+ISS) + Third Party HDL Simulator + FPGA Board (Dynalith)

System-Level Co-Simulation

OpenIDEAOpenIDEA

Socket

DebugWindows


ISSISS

Processor Model

C Models

HDL Sim.HDL Sim.

IP3

Socket

IP2

BUS

IP1

SRAM Model

3 HW/SW Co-Simulation/Co-Emulation


52/69

Introduction ( 52 )

OpenIDEA (Debugger+ISS) + Third Party HDL Simulator + FPGA Board (Dynalith)

System-Level Co-Simulation/Co-Emulation

OpenIDEAOpenIDEA

Socket

DebugWindows


ISSISS

Processor Model

C Models

HDL Sim.HDL Sim.

IP3

Socket BUS

IP1SRAM Model IP2

FPGA

PCI/USB

4.1 HW Simulation with SW Debugging


53/69

Introduction ( 53 )

OpenIDEA (Debugger) + Third Party HDL Simulator

HW/SW Co-Verification with Accurate Processor Model

SW Debugging with HW Probing

OpenIDEAOpenIDEA

Socket

Debug

Windows


C Models

HDL Sim.HDL Sim.

BUS

IP1

SRAM Model

IP2

IP3

Processor Model

4.2 HW Simulation with SW Debugging(2)


54/69

Introduction ( 54 )

OpenIDEA (Debugger) + Third Party HDL Simulator + FPGA Board (Dynalith)

HW/SW Co-Verification with Accurate Processor Model

SW Debugging with HW Probing

OpenIDEAOpenIDEA

Socket

DebugWindows


C Models

HDL Sim.HDL Sim.

BUS

IP1

SRAM Model

IP3

Processor Model

IP2

FPGA Board

PCI/USB

5. HW Prototyping SW Debugging


55/69

Introduction ( 55 )

OpenIDEA (Debugger) + FPGA Board (Dynalith)

HW/SW Co-Verification with Source-Level Debugger and BILA (Built In Logic Analyzer) or

ChipScope(Xilinx)

FPGA BoardOpenIDEAOpenIDEA

PCI/USB

JTAG

Debug

Windows

Source-Level

Debugger

BUS

IP1

SRAM Model

IP2

IP3

Processor Model

6. In Circuit Emulation (ICE)


56/69

Introduction ( 56 )

OpenIDEA (Debugger) + Evaluation Board/FPGA Board (Custom)

In-Circuit Emulation

Software Development with Real Platform

ASIC Board / Custom FPGA BoardOpenIDEAOpenIDEA

USB

DebugWindows

Source-Level

Debugger

BUS

IP1

SRAM Model

IP2

IP3

Processor

ASIC/FPGAOpenICE

JTAG

Agenda


57/69

Introduction ( 57 )

Introduction to OpenRISC


Hardware Development with iNSPIRE-LiteHardware/Software Co-Verification with OpenIDEA

Verification Flow

Hardware Design/Verification Flow


58/69

Introduction ( 58 )

Gate-Level Simulation

RTL Design of Each IP

Individulal IP Verification Using HDL

Test-Bench

Individulal IP

Design &Verification

System-LevelHW-SW Co-

Verification

IP Verification in System

System-Level RTL Verification

FPGA Prototyping

Synthesis

PnR

Static Timing Analysis

Post PnR Simulation

RT

-Level

Gate-Level

IP Design and Verification


59/69

Introduction ( 59 )




Test-Bench

Individulal IP



Verification



FPGA Prototyping

Synthesis

PnR


Post PnR Simulation

RT

-Level

Gate-Level

iNSPIREiNSPIRE

Socket

ArchitectureWizard

HDL SimulatorHDL Simulator

IPDriver/Phy/Mem

ory Model

DUV

Simuilation Top

Generation

Test-bench

HDL Simulation

IP Design and Verification


60/69

Introduction ( 60 )




Test-Bench

Individulal IP



Verification



FPGA Prototyping

Synthesis

PnR


Post PnR Simulation

RT

-Level

Gate-Level

HDL SimulatorHDL Simulator

Simuilation Top

Test-bench

FPGA Board

IPDriver/Phy/Memory

FPGADUV

Proxy

iNSPIREiNSPIRE

ArchitectureWizard

Generation

Design FlowWizard

Co-Emulation (Acceleration)

System-Level HW/SW Co-Verification (RTL)


61/69

Introduction ( 61 )




Test-Bench

Individulal IP



Verification



FPGA Prototyping

Synthesis

PnR


Post PnR Simulation

RT

-Level

Gate-Level

OpenIDEAOpenIDEA

Socket

DebugWindows


ISSISS

Processor Model

SRAM Model

IP1

C Models

HDL Sim.HDL Sim.

IP2

IP3

Socket

2.1 HW/SW Co-Simulation



62/69

Introduction ( 62 )




Test-Bench

Individulal IP



Verification



FPGA Prototyping

Synthesis

PnR


Post PnR Simulation

RT

-Level

Gate-Level

OpenIDEAOpenIDEA

Socket

DebugWindows


C Models

HDL Sim.HDL Sim.

BUS

IP1

SRAM Model

IP2

IP3

Processor Model




63/69

Introduction ( 63 )




Test-Bench

Individulal IP



Verification



FPGA Prototyping

Synthesis

PnR


Post PnR Simulation

RT

-Level

Gate-Level

OpenIDEAOpenIDEA

Socket

DebugWindows


C Models

HDL Sim.HDL Sim.

BUS

IP1

SRAM Model

IP3

Processor Model

IP2

FPGA Board

PCI/USB




64/69

Introduction ( 64 )




Test-Bench

Individulal IP



Verification



FPGA Prototyping

Synthesis

PnR


Post PnR Simulation

RT

-Level

Gate-Level

FPGA BoardOpenIDEAOpenIDEA

PCI/USBJTAG

DebugWindows


BUS

IP1

SRAM Model

IP2

IP3

Processor Model

5. HW Prototyping with SW Debugging

System-Level HW/SW Co-Verification (Gate-Level)


65/69

Introduction ( 65 )




Test-Bench

Individulal IP



Verification



FPGA Prototyping

Synthesis

PnR


Post PnR Simulation

RT

-Level

Gate-Level

OpenIDEAOpenIDEA

Socket

DebugWindows


C Models

HDL Sim.HDL Sim.

BUS

IP1

SRAM Model

IP2

IP3

Processor Model


OpenIDEATM OpenRISC Development Toolkit

OpenIDEA ASIC In-Circuit EmulationWith ASIC


66/69

(): 02) 556-0020 Fax: 02) 556-2252 E-mail: [email protected] http://www.dynalith.com

Software DevelopmentProcessor Architecture SimulationSource-Level Debugging

iNSPIRE-LiteGraphical Architecture CompositionAutomatic Hardware GenerationVarious Open-Source Library

iNCITE

3rd-Party HDL Simulator HW/SW Co-SimulationWith Third-Party HDL SimulatorSource-Level SW DebuggingSignal-Level HW Debugging

HW/SW Co-EmulationWith FPGA Prototype Board (iNCITE )Source-Level SW DebuggingSignal-Level HW Debugging Using BILAFast USB 2.0 Connection to PCVarious Peripherals Supporting

Source-Level SW DebuggingJTAG Connection to PC

OpenIDEA OpenRISC SoC-.,/.

Design and verification steps using OpenIDEA

ISS-based software simulation


67/69

Introduction ( 67 )

ISS based software simulation

It uses OpenRISC ISS to run software

and pure-functional hardware model for

hardware.

ISS-HDL co-simulation

It uses OpenRISC ISS to run software

and RTL hardware model running on top

of HDL logic simulator.

HDL-based simulation

It uses a whole system including Open-

RISC core running on top of HDL

simulator and the core is controlled by

debugger.

FPGA-based emulation

It uses OpenRISC core to run software

and hardware blocks in FPGA.

Recommended design and verification steps

1 ISS-based software simulation using


68/69

Introduction ( 68 )

1. ISS based software simulation using

OpenIDEA.

2. Building system hardware model using

iNSPIRE-Lite.3. ISS-HDL co-simulation using

OpenIDEA and HDL simulator.

4. Building system hardware for FPGA

using iNSPIRE-Lite.

5. FPGA-based emulation using

OpenIDEA and iNCITE.

UART example

Example system


69/69

Introduction ( 69 )

Example system

OpenRISC 1200 processing core

Memory controller

UART (Universal Asynchronous Receiveand Transmit)

WISHBONE bus

The user application program will be

loaded into the SSRAM after cross-

compilation, and run by the OpenRISC

processing core.The user application program simply

controls the UART in order to get and put

character data through the serial cable,

which is connected through the Line

Driver and UART.

vlsi_lecture02_openidea(정무경).ppt

Documents