Voice over IP

Voice, Video, Data Convergence

Agenda

• VoIP technology, protocols & issues• VoIP variations: VoDSL, VoCable, FoIP• Other networks for packet voice transport• VoIP gateway & IP phones• Xilinx solutions for VoIP products

VoIP Issues, Technologyand Protocols

Quality of Service (QoS) Issues

• Network needs to provide a guarantee of service level– Delay– Jitter (delay variability)– Packet loss

• This must be negotiated up front– Client requests resource– Network determines if request can be fulfilled– Network signals yes or no to request– If yes it reserves resources to meet need– Client begins transferring data

VoIP QoS Issues: Delay• Delay causes 2 problems

– Echo• Caused by the signal reflections of the speaker’s voice from the far-end

telephone equipment back to the speaker’s ear• Significant quality problem when the round-trip delay becomes greater

than 50ms• Must be addressed by VoIP systems - echo control & echo cancellation

mechanisms– Talker overlap

• Problem of one talker stepping on the other talker’s speech• Significant issue if one-way delay becomes greater than 250ms• Reducing end-to-end delay through the VoIP network is needed

Sources of Delay in a VoIP Call

• Accumulation (algorithmic) delay– Caused by the need to collect a frame of voice samples to be processed by

the voice coder• Processing delay

– Caused by actual process of encoding & collecting the encoded samples into a packet for transmission over the packet network

• Function of both the processor execution time & type of algorithm used• Network delay

– Caused by the physical medium, protocols used to transmit voice/data & by receive side buffers used to remove packet jitter

Delay Issues• Problems

– Echo if delay > 50 msec• Solution: Echo cancellation

– Speaker overlap if delay > 250 msec• Solution: Keep total delay < 250 msec

• Delay components– Algorithmic - Due to voice coding (125 usec to 30 msec)– Processing - Due to packetization (up to 30 msec)– Network - Transmission delays due to

• Speed of light ( New York to LA: 15 msec)• Delays through routers (10 usec)• Jitter buffering (70 to 100 msec)

Echo Cancellation

• Caused by reflections from far-end hybrid• Becomes objectionable if loop delay > 50 msec

– Needed in most cases• Echo canceller

– Performance requirements defined in ITU G.165– Components

• Correlator - To determine loop delay• FIR filter - To remove echo• Speech Detector - to suppress coefficient updates when

there is no speech

VoIP QoS Issues: Jitter

• Variable inter-packet timing caused by the network a packet transverses

• Removing jitter– Requires collecting packets & holding them long

enough– Allows the slowest packet to arrive in time to be

played in the correct sequence - causes additional delay

Conflicting Goals

• Minimize delay• Remove jitter

VoIP QoS Issues: Packet Loss

• IP networks cannot provide a guarantee that packets will be delivered at all or in an order– Packet losses greater than 10% are generally not tolerable

• Packets will be dropped under peak loads & during periods of congestion

• Normal TCP-based retransmission schemes are not suitable– Time sensitivity of voice transmissions

• Approaches for compensating packet loss– Interpolation of speech by re-playing the last packet– Sending of redundant information

How to Deliver QoS• Can be merged at different layers of stack

– Layer 1 - The old way• Separate circuits for voice and data traffic• Inefficient use of bandwidth• Cumbersome to configure

– Layer 2 - The ATM vision• Multiplex traffic using ATM cells• Exploit ATM QoS features• There is resistance to the Cell Tax (10% ATM overhead)• Must manage ATM and IP network

– Layer 3 - The IP Vision• Multiplex traffic over IP• Manage a single IP network• Exploit Layer 2 & Layer 3 QoS features

IP QoS Technologies (contd.)• Resource ReSerVation Protocol (RSVP)

– General purpose signaling protocol providing end to end reservation of network resources

• True reservation setup-and-control protocol• Designed to achieve characteristics similar to circuit-switched networks

on an IP network– Reserved for a connectionless data stream based on receiver

controlled requests• Suitable for “quantitative” QoS requirements in which the application

can discretely identify its quality requirements and parameters• Issue: Not scalable because it handles QoS requests on a per-flow

basis– Defined in IETF RFC 2205-2209

IP QoS Technologies (contd.)

• Real-time Transport Protocol (RTP)– Uses Unix Datagram Protocol (UDP)– Real-time end-to-end protocol utilizing transport layers for data that has

real-time properties– Provides time reconstruction, loss detection, security and content

identification– Defined in IETF RFC 1889

• Real-time Transport Control Protocol (RTCP)– Protocol used for control to monitor the QoS and to convey information

about the participants in an ongoing session• Provides feedback on total performance & quality so that modifications

can be made– Defined in IETF RFC 1889, 1890

IP QoS Technologies (contd.)

• Resource Allocation Protocol (RAP)– How routers talk to each other to reserve resources – Still in definition

• Differentiated Services (DiffServ)– Uses IP TOS (type of service) field to prioritize traffic

• Assigns QoS qualification to traffic-based on service-level agreements between users and service providers

• Defines assured & premium service levels that can be applied network traffic according to predetermined policy criteria

• More scalable than RSVP but offers no fine-grained QoS classifications

– Evolving standard defined in RFCs 2474, 2475, 2597, 2598

IP QoS Technologies (contd.)

• Real Time Streaming Protocol (RTSP)– Provides "VCR-style" remote control for streaming network

audio/video– Defined in RFC 2326

• Common Open Policy Service (COPS)– How network boxes communicate policy information– Protocol defined in RFC 2748

VoIP Protocol Structure

H.323

RTP, RTCP, RSVP

UDP / TCP

Network Layer (IPv4, IPv6, IPM)

Data Link Layer

Physical Layer

H.323

• Part of the H.32x family of recommendations specified by ITU-T• Specifies components, protocols & procedures that provide

multimedia communication services - real-time audio, video & data over packet networks– Packet based networks include IP-based LANs, enterprise

networks, MANs, WANs• Protocols specified by H.323

– Audio CODECs; video CODECs; H.225 registration, admission, and status (RAS); H.225 call signaling, H.245 control signaling, real-time transfer protocol (RTP), real-time control protocol (RTCP)

H.323 Protocol Stack

VoIP Software Architecture

VoicePacket Module

Telephony Signaling

Module

Signaling

Voice

DSP MICROPROCESSOR

Voice & SignalingPacketsNetwork

Protocol Module

RemoteManagement

Module

VoIP Software Architecture

• Partitioned to provide interface to the DSP software usable overmultiple voice packet protocols & applications– Provides a clean interface between the generic voice-

processing functions• Compression• Echo cancellation• Voice-activity detection• Application specific signaling• Voice protocol processing

VoIP Software Architecture• DSP

– Processes voice data– Passes voice packets to the microprocessor with generic voice headers

• Microprocessor is responsible for – Moving voice packets– Adapting generic voice headers to specific VoIP protocol as defined by the

application• Such as real-time protocol (RTP), voice over frame relay (VoFR) &

voice telephony over ATM (VToA)– Processes signaling information & converts it from telephony-signaling

protocols to the packet network signaling protocol• Such as H.323, frame relay, ATM signaling

Voice Packet Software Module

• Also known as voice-processing module– Runs on a DSP– Prepares voice samples for transmission over the VoIP

network– Components perform

• Echo cancellation• Voice compression• Voice-activity detection• Jitter removal• Clock synchronization• Voice packetization

Telephone-Signaling Gateway Software Module

• Interacts with telephony equipment– Translates signaling into state changes used by the

packet protocol module to set up connections– Supports

• Ear, mouth, earth, and magneto (E&M) Type I, II, III, IV & V• Loop or ground start foreign exchange station (FXS)• Foreign exchange office (FXO)• ISDN basic rate interface (BRI) & primary rate interface

(PRI)

VoIP Telephony Signaling

Packet Protocol Module

• Processes signaling information– Converts it from the telephony-signaling protocols to

the specific packet-signaling protocol– Used to set-up connections over the packet network

• Q.993 & voice-over-frame relay signaling– Adds protocol headers to both voice & signaling

packets before transmission into the packet network

Network-Management Module

• Provides voice-management interface to configure & maintain the other modules of the VoIP system– Management information is defined in ANSI– Complies with SNMP (signaling network-management

protocol)– Supports proprietary voice packet management

information base (MIB)

Voice Packet Module

• Consists of– PCM interface– Tone generator– Echo canceller– Voice activation detector / idle noise measurement– Tone detector– Voice codec software– Fax software– Voice play-out unit

VoIP Voice Processing Voice Packet Module

Voice Coding

• Several CODECs are used that trade off– Data Rate– Processing requirements– Processing delay– Audio quality (MOS)Standard Description Data Rate

(Kbps)Delay(mS)

MOS

G.711 Pulse Code Modularion (PCM). 64 0.125 4.4G.721, G.723, G.726 Adapt ive Differential PCM (ADPCM). 16, 24, 32 & 40 0.125 4.2G.728 Low-Delay Code Excited Linear Predictors (LD-CELP). 16 2.5 4.2G.729 Conjugate-Structure Algebraic CELP (CS-ACELP). 8 10 4.2G.723.1 Another CS-ACELP codec 5.3 & 6.3 30 3.5 & 3.98

VoIP Gateway Technologies

VoIP Variations

FoIP - Fax over Internet ProtocolVoDSL - Voice over Digital Subscriber LineVoCable - Voice over Cable

Fax over IP (FoIP) Technologies

• Uses same technology as VoIP• Unlike voice calls FAX transmissions can be

buffered– Allows non-realtime distribution across Internet

• FoIP service vendors provide– Servers for buffering– Distribution– FoIP gateways across the country

Voice over DSL (VoDSL)

• Leverages the copper infrastructure– Provides both quality voice services – Supports wide variety of data applications over the

same existing line to customer’s sites

Voice over DSL (VoDSL)• VoDSL has 2 basic components

– Voice gateway• Voice packets are de-packetized & converted to a standards-based

format (GR-303, TR-08, V5.X) for delivery to a Class-5 voice switch– IAD (Integrated Access Device) / CPE (Customer Premise Equipment)

• Serves as a DSL modem• Interfaces between a DSL network service & customer’s voice & data

equipment• Packetization of voice traffic takes place on this unit utilizing standards-

based technology• CPE prioritizes the voice packets over data calls to ensure toll-quality

voice delivery & then sends the packet over the DSL line

How Does VoDSL Work?

• Uses VoIP across a DSL connection– Specialized VoIP gateway

• Lets CLECs provide bypass voice services

Standards Groups Involved with VoDSL

• ANSI• ETSI• Digital Audio Video Council (DAVC)• ATM Forum• ITU• ADSL Forum

Voice over Cable (VoCable)• Cable-based IP telephony

– Delivering Internet & voice service over the cable spectrum• Half-duplex vs. full-duplex cable infrastructure

– Half-duplex• Capable of broadband transmission in the downstream (from the head

end to the subscriber) direction only– Makes it cumbersome for premium TV services such as pay-per-view that

require upstream communication– Internet service is extremely inconvenient as e-mail messages and HTTP

requests have to be sent via the phone– Cable companies have upgraded buried cables from half to full duplex to

provide two-way high-bandwidth video, voice & data communications

VoCable Issues

• Direct connect– Cable networks were originally designed to broadcast one

signal to many recipients• Security

– Prioritization of packet traffic with QoS & security features for voice communication are not completely addressed in even the 2nd generation DOCSIS standard

– Despite supporting data-encryption & authentication algorithms cable-based IP telephony is susceptible to illegal wire tapping & inadvertent chat conditions

VoCable Issues • Power consumption

– Telephones draw power from POTS lines, providing life-line service even in case of power outages

– VoIP phones connected to the cable, must have at least 4 hours of battery back-up - hence be powered by under 3W

• Billing– While most cable TV customers receive the same bill every

month, telephone billing is very complex– Cable billing has special billing for pay-per-view requests only– Telephone bills include monthly service fees, long distance &

international charges, charges based on time & day, premium services, pay per-use services

Other Networks for Packet Voice Transport

VoATM - Voice over ATMVoFR - Voice over Frame Relay

Packet Voice• All packet systems follow a common model

– Regardless of the transport network (IP, ATM or FR)– Voice agents

• Devices / components at the edge of the network• Change voice information from its traditional telephony form to a form

suitable for packet transmission– Network forwards the packet data to a voice agent serving the destination

(party)• Issues in packet voice networking

– Voice coding - the ability of voice information to be transformed into packets& recreation of voice from packets

– Signaling associated with identifying who the calling party is trying to call and where the called party is in the network

Basic Model for Integrating Voice and Data

• Transport– Transparent support of voice over existing data

networks

• Translate– Translation of traditional voice functions by the data

infrastructure

VoATM - Voice over ATM

• ATM - Asynchronous Transfer Mode– High-speed/high bandwidth, low-delay, connection-

oriented, packet-like switching and multiplexing technique

– Requires byte fixed sized cells• Uses 53-byte cells (5-byte header, 48-byte payload) to

transmit different types of simultaneous data, voice and video traffic

• Specified by ITU and ATM Forum

VoATM

• Designed primarily for voice communications– Constant bit rate (CBR) & variable bit rate (VBR) classes

• Have provisions for passing real-time traffic & are suitable for guaranteeing a certain level of service

– CBR allows the amount of bandwidth, end-to-end delay and delay variation to be specified during the call setup

• Designed primarily for data communications (bursty traffic)– Unspecified bit rate (UBR) & available bit rate (ABR)– Makes no guarantee about the delivery of the data traffic

ATM Adaptation Layer (AAL)

• Set of standard protocols adopted by the ATM Forum for a class of service called High Speed Data Transfer

• Perform segmentation, assembly and re-assembly (SAR)– Translate user traffic into a size and format that can be

contained in the payload of an ATM cell (53 bytes)– User traffic is returned to its original form at the destination

• All AAL functions occur at the ATM end-station rather than at the switch

Transporting Voice Through ATM Networks

• Depends on the nature of the traffic• Different ATM adaptation types have been

developed for different traffic types– Dependent on advantages & disadvantages

• ATM Adaptation Layer 1 (AAL1)– Most common adaptation layer used with CBR

services

Transporting Voice Over ATM

• Unstructured AAL1– Takes a continuous bit stream and places it within ATM cells

• This is a common method of supporting a full E1 byte stream from end-to-end

• Issue: A full E1 may be sent regardless of the actual number of voice channels in use

• Structured AAL1– Contains a pointer in the payload that allows the DS0 (digital

signal level 0) structure to be maintained in subsequent cells– Provides network efficiency by not using bandwidth for unused

DSOs

VoATM Signaling

• Transport method in which voice signaling is carried through thenetwork transparently

• Permanent Virtual Circuits (PVCs)– Created for both signaling and voice transport– Signaling message is carried transparently over the signaling

PVC from end station to end station– Coordination between end systems allow the selection of a

PVC to carry the voice communication between end stations– Some solutions are capable of understanding CAS (channel

associated signaling) & can prevent the sending of empty voice cells when the end stations are on-hook

VoATM Signaling

• In the VoATM signaling translate model the ATM interprets the signaling from both non-ATM and ATM network devices

VoIP Gateway

IP Phones

High Capacity VoIP Gateway

• VoIP gateways support– Now: 10s to 100s of lines– Soon: 100s to 1000s of lines

• MIPs required for voice processing become significant– Typical solution is arrays of high performance DSPs– A 100 MHz TMS320C5421 supports up to 12 channels

• Typically implemented with Compact PCI• Separate cards for

– Voice processing– Signaling processor– Ports

VoIP Gateway Block Diagram

Voice Processing Card

• Multiple high performance DSPs– 8 x 250 MHz DSPs– Each with 16 MB SDRAM

• Dual RISC management processors– 80 MHz PowerQUICCs– Provide Fast Ethernet

connectivity• > 192 Voice channels per

board

Voice Processing Card contd.

IP Phones

• Consist of– VoIP Gateway– Network interfaces usually

Fast Ethernet– CODEC– User interface hardware

• Usually include two processors– DSP for voice processing– RISC processor for signaling and

system management

IP Phone Block Diagram

VoIP Market Segments

• Enterprise VoIP gateways– CPE deployed between BPX and LAN

• Service provider VoIP gateways– Deployed in central office

• VoIP routers– Routers with gateways built-in

• VoIP enabled Remote Access Servers (RAS)– Used by ISPs to provide gateway services

• VoIP end stations– IP Phones

Convergence ASSPs

Xilinx Solutions for VoIP Products

VoIP Today

• Growing chaos in this emerging technology– Solutions are just coming to market– Leading players are showing indecisiveness towards

different varying technologies• Building independent solutions• Participation in multiple consortiums• Different wireless standards for same frequency band

• Interoperability is a key factor to market success• Future revisions already in the works

Implications of this Chaos...

• Brings about an Environment That Guarantees Unanticipated Problems– Bugs– Incompatibilities– The Great Unknown about what is going to be the changes

• Translates to a Steep Learning Curve– Virtually mandates a “Ready, Fire, Aim” development model

• Plan products for the longest life cycles• Get a product to market “now”• Rapidly integrate refinements and enhancements

Where Does Xilinx Fit In the Electronics Industry

• Processor• Memory• Logic

Xilinx is the Leading Innovator of

Complete Programmable Logic Solutions

Xilinx is the Leading Innovator of

Complete Programmable Logic Solutions

Key components of an electronics system:

Strategic Business Model Ensures Focus

• “Fabless” strategy– Leading edge IC process technology– Wafer capacity at competitive prices– Fastest, lowest cost, densest parts

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• Focus on key strengths– Product design– Marketing– Applications & Technical Support

CoolRunner-II RealDigital CPLD• RealDigital design methodology

– 180nm, 1.8V, digital core – 3.0ns TPD, 385MHz FMAX (32mc device)

• I/O– HSTL, SSTL, LVTTL, LVCMOS – Multiple I/O banking on larger devices

• Clocking– DualEDGE– Clock Divider and CoolCLOCK

• Low power– 28.8µW at 1.8V, even lower power possible with DataGATE

Xilinx PLA Architecture is Superior to PAL

• Better pin locking– PLA architectures offer better use of existing logic with programmable

AND & programmable OR structures• More logic left for design changes

– PAL architecture only offers programmable AND structures• Duplication of logic to achieve the same results• Waste logic resources• Fitter software is more complex

• Better use of logic resources– Product term sharing instead of duplication

• Reduces p-terms and saves logic

• Traditional CPLDs - bipolar sense amp product terms– Always consumes power

– Even at standby– Performance is traded for

power consumption as devices get larger

• CoolRunner-II RealDigitaldesign uses 100% CMOS for product terms– Virtually no standby current– Combines high performance &

ultra low power– No power limits on device size

RealDigital Design Advantage

RealDigital: CMOS Everywhere - Zero Static Power

CBA

D

Sense amplifier 0.25mA each - Standby Higher ICC at Fmax

A B C

Turbo vs Non TurboLarger R = slower response

& less powerVcc

CoolRunner-II Highest Performance at 1.8V & Beyond

* Relative performance at 5V = 1 & Icc constant

RealDigital Technology

Sense amp Technology *

5.0V 3.3V 2.5V 1.8V 1.5V 1.2V0

1

2

RelativePerformance

Note: Sense amp based CPLDsincrease Icc to achieve faster speeds

Industry Lowest Power CPLDdynamic

power (mW)

300

200

100

* Estimated 128 macrocell dev ice witheight 16-bit counters @ 50MHz

Sense ampbased CPLDs

typical standby power3.3V X 100uA = 330µW typical standby power

1.8V X 20uA = 28.8µW

typical standby power > 300,000uW

dynamic power 66mW*

dynamic power360mW*

dynamic power12mW*

Solving Signal Integrity Challenges

• Noisy, slow analog signals• Hall Sensor• R/C Oscillator• XTAL input• RFI, EMI effects

Inputhysteresis

• With input hysteresis• Analog signals function as digital inputs• Saves power by non-linear operation• Added noise immunity

Divide by 4

Divider

System ClockSync Reset

Div_clock Phase bit = 0

Div_clock Phase bit = 1

Clock Divider: Power Efficient• 128, 256, 384 & 512

macrocell• 2,4,6,8,10,12,14 or 16 digital

clock divide• Reduce external oscillators• 50% duty cycle• Reduces cross talk

Capability

Logic Cells

Significant increasein densityand lower logic cost

60K 80K

Spartan-IIE Family (Nov 2001)

Unprecedented Spartan Density RangeOpens Up New Opportunities

Spartan-3 Family (April 2003)

Increase in Density from 300K to 5M gates in 5 Months

Spartan-IIE Family Extensions (Nov 2002)2S50

20K 40K

0%

20%

40%

60%

80%

100%

Less than200,000

200,000 -399,999

400,000 -799,999

800,000 -1,999,999

2,000,000 -3,999,999

4,000,000 -9,999,999

10,000,000 -19,999,999

20,000,000 -40,000,000

Spartan-3 Addresses The “Sweet Spot” of Mid-Range ASICs

Source: Gartner Group/Dataquest

Spartan-IIESpartan-IIE

Cell-Based IC (CBIC)

Cell Based Design Starts by Average Transistor Count Cumulative

The Spartan-3 Platform:A New Class of Spartan FPGAs

High Performance Sync Dual-Port™

RAM

SelectIO™-Ultra Technology

Advanced FPGA Logic with Staggered

Pad Technology 90 nm90 nmEmbedded XtremeDSP Functionality

DCM

DCM™ Digital Clock

Management

18 Bit18 Bit 36 Bit

Z

VCCIO

Z

Z

ImpedanceControl

XCITE Digitally Controlled Impedance

Migration with Staggered PadsMigration with

Staggered Pads

Maximizing I/O AdvantagesDelivering minimum die size, maximum I/Os

Die size reduced

IO pads preserved

Die size reduced

IO capability lost

Conventional Process Migration

Conventional Process Migration

Lowest Cost Parallel Interconnect Solutions

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* Based on pricing for 2004, 250K units

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Ideal for Bridge Functions

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Embedded DSP CapabilityUp to 104 18bit Multipliers! Simple and Familiar DSP Design Flow

18 Bit

18 Bit

36 Bit

Digita l Signal Processing (Voice

processing, system control, caller ID,

V.34/V.42 Modem)

System Processor (Signaling &

Network Management)

FlashRAM

10/100 Base-TX Ethernet MAC

MII 10/100 Base-TX Transceiver

Analog Front End (AFE)

SRAM

Voice CODEC (Handset & speakerphone CODEC (ADC, DAC) with Audio

Filters

RJ-45

Non-Voice User Interface Logic(LCD, LED, IR Remote, USB,

Keyboard Controller)

Speaker MIC

Keyboard,Keypad

LCD, LED

USB

RJ-11Voice Interface

Non-

Voice

Use

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Indica

tor,

Key P

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Serial Port

Data Serv ices

Handset

To/From PC

To/From Network

VoIP Phone

HomePNAMAC

Spartan-II Solutions for VoIP Products

• I/O control– Multiple front end interfaces– Multiple back end interfaces

• Hard disk drive interface• Clock distribution

– DLLs• MPEG decoder• Ethernet MAC • Error correction

– Reed-Solomon, Viterbi• PCI

• Memory solutions– On-chip Distributed memory,

BlockRAM– Memory controllers

• CPU / microcontroller• HDLC controller• ADPCM• Color Space Converters• Glue logic & system integration

– LCD controllers, UARTs, DMA controllers

Programmable Solutions Advantages

Xilinx Programmable Solutions Provide Several Benefits

• Time to market– Consumer devices require fast time-to-market– ASICs & ASSPs take 12-18 months to spin out

• Flexibility– Product customization to meet customer needs– Accommodate multiple standards & spec updates/changes– Feature upgrades

• Testing and verification– Re-programmable allows risk aversion – Your solutions are built on a proven FPGA technology with

pre-verified silicon and IP that guarantees performance

Xilinx Programmable Solutions Provide Several Advantages

• Xilinx On-line - field upgradability – Remote update of software and hardware– Results in increased lifetime for a product (time-in-market) and

allows new, interesting applications– Enable product features per end-user needs

• Issues in creating a stand-alone ASIC/ASSP– Choosing the right solution– Product customization– Development cost and amortization

• Low Cost

Lifecycle Component Logistics

• Xilinx is an assured source of supply– Spartan FPGAs are high volume standard parts– Xilinx is a Strategic customer to our fab partners– If a device is retired, designs are quickly portable

• Xilinx’s solutions reduce exposure to component supply issues– Designs can be quickly adapted to efficiently address

component supply problems• NAND to NOR type Flash support for example

– Gives latitude in maintaining a cost effective BOM in dealing with the allocation, end of life & generational migration realities of today’s component market

The Xilinx Play in QoS Infrastructure

• Complex glue between ASSPs– Network Processor to switch fabric– Network Processor to port interface

• Supporting Network Processors by accelerating complex algorithms– Traffic classification– Traffic scheduling & policing– Complex wire speed policies– Queue management