zhanwei zhong-wallace tree multiplier-final term
TRANSCRIPT
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8 Bit Wallace Tree Multiplier
ECE 539 Course ProjectZhanwei Zhong
12/15/2016
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205/01/2023
Vertical Sliced Schematic
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305/01/2023
Original Block DiagramA7A6A5A4A3A2A1A0
B7B6B5B4B3B2B1B0
A1B1A1B0A0B0
A7B7A6B7A6B6
............
1 2 3 4 5 6 7 8
Partial Products
Partial Products Addition
Final Addition
C15C14C13C12C11C10C9C8C7C6C5C4C3C2C1C0
64
44
35
27
20
17
16
14
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405/01/2023
Horizontal Sliced Schematic
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505/01/2023
Revised Block DiagramA7A6A5A4A3A2A1A0
B7B6B5B4B3B2B1B0 A1B1
A1B0A0B0
A7B7A6B7A6B6......
......
S15S14S13S12S11S10S9S8S7S6S5S4S3S2S1S0
S1-S3
S4S5S6S7S8
S9S10S11
S12-S15
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605/01/2023
Half Adder
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705/01/2023
Half Adder
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805/01/2023
Full Adder
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905/01/2023
Full Adder
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1005/01/2023
S1-S3
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1105/01/2023
S1-S3
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S4
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S4
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S5
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S5
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S6
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S6
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S7
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1905/01/2023
S7
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2005/01/2023
S8
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2105/01/2023
S8
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2205/01/2023
S9
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2305/01/2023
S9
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2405/01/2023
S10
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2505/01/2023
S10
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2605/01/2023
S11
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2705/01/2023
S11
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2805/01/2023
S12-15
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2905/01/2023
S12-15
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3005/01/2023
Wallace Multiplier with Latches
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3105/01/2023
Wallace Multiplier with Latches
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3205/01/2023
DRC Result
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3305/01/2023
LVS Result
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3405/01/2023
SpecificationArea
The estimated area is:
Power ConsumptionSuppose average swithcing capacitance is 15pF/mm2, V=3.3V, =0.1, f = 200MHz,
then the dynamic power consumption is:
2 14 2 6 5( ) 0.1 7.695 10 3.3 200 10 1.67 10dynamicP CV f W
501unit 319unit=90 m 57 mA
12 3 3 1415 10 90 10 57 10 7.695 10totalC F
6( ) 4.8 10simulationP W
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Test Pattern and Two Phase Clockingtest case 1: 1111 1111 0000 0000 = 0000 0000 0000 0000test case 2: 1111 1111 0000 1111 = 0000 1110 1111 0001test case 3: 1111 1111 1111 0000 = 1110 1111 0001 0000test case 4: 1111 1111 1111 1111 = 1111 1110 0000 0001
𝐴7 𝐴0 𝐵7 𝐵0 𝑆15 𝑆0
5ns
1.5ns
1.5ns
2.5ns
input latch clocking
output latch clocking
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Testing Circuit
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Testing Result: A7-A0
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Testing Result: B7-B0
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Testing Result: S15-S12
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4005/01/2023
Testing Result: S11-S8
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Testing Result: S7-S4
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4205/01/2023
Testing Result: S3-S0