中華大學電機系田慶誠 1 active devices and s-parameters session 1

1中華大學電機系田慶誠

Active Devices andS-Parameters

Session 1


RF Amplifier Block Diagram

Transistor

InputMatchingNetwork

OutputMatchingNetwork

50

50

DC BiasCircuit


Microwave and RF Active Devices

Bipolar TransistorsBJT: Bipolar Junction TransistorHBT: Heterojunction Bipolar Transistor

Field Effect TransistorMESFET: Metal Semiconductor FETHEMT: High Electron Mobility TransistorPHEMT: Pseudomorphic HEMTJFET: Junction FETMOSFET: Metal Oxide Semiconductor FET


Silicon BJT Cross Section

Wb Base lengthCollectordepletion layer

Collectorsubtrate

C

EB B

0.1um

1.5um

125um

Cbe=bgm Diffusion capacitor


Silicon BJT Top Views

Emitter

Base

Emitter

Base

Power BJT

Emitter width0.5-2um

EmitterPeriphery(length)

1um


Discrete BJT Package


AlGaAs/GaAs HBT MMIC

AlGaAs/GaAs Heterojunction


Heterojunction Combinations

Emitter(n+

)Base (P) Substrate

AlGaAs GaAs GaAs

InAlAs InGaAs InGaAsInGaP GaAs GaAs

Si SiGe SiGe


HBT MMIC Layout

Isolation implant

Collector contact

Base pedestal

Base contact

Emitter mesa

Emitter contact


HBT MMIC Layout


BJT v.s. HBT

相同點：縱向電流，提供雙載子電流不同點 BJT HBT

B-E 接面同質 (silicon) 異質Base doping 5x108 cm-3 Higher 4x109

rb’e or re VT / IB, VT / IE Lower

VSat(e-) 0.7x107 cm/s Higher 2x107

Gain (gm) IC/ VT Higher

Base thickness

0.1um Small 0.06um

fT, fmax fT=gm/2Cb’e Higher

Substrate Lossy High resistance


Bipolar Transistor Linear (Small Signal) Model

Intrinsic model(Bias dependent)

Extrinsic model

Serenade 8.0


Nolinear Gummel-Poon Model


BFP420 Spice Parameter Example

BFP420 data sheets


Model Keywords and Equations

Serenade 8.0


Transistor Package effect


BFP420 Package Model Example

BFP420Package Model


DC Characteristics of BJT

BFP420IBIC

VCE

hfe=IC/IB

Active Region


Principle of Amplification(Biased at Active Region)

VBE

IC Slope = gm

Exponential gm

Input signal

Output signal

)1e(II TBE V/VSC Emitter

T

C

BE

Cm A

VI

VI

g


Simplified Hybrid- Model

rb’e gm Cb’e Cb’c hfe will be changed by DC bias and large AC signal!


H parameters of Bipolar Transistor

2

1

2221

1211

2

1

V

I

hh

hh

I

V

h11h22h21

h12V2

+ -

Calculate or measure h21 or hfe

0VwhenII

hh 21

221fe (Port 2 is shorted!)

I1 I2

V1V2

+ +

- -


Parasitic Effect of Transistor

ib’

ibhfeDC*ib’

只有真正的載子電流被電晶體放大

rb’e

iC

Cb’e+Cb’c

Leakage

頻率越高，電晶體寄生電容漏電越嚴重，被放大的電流越少！因此，電晶體等效電流增益 hfe(f)=ic/ib 會形成低通頻率響應。

hfe(f): forward short circuit current gain (h21)


Lowpass Response of hfe

e'bc'be'b

DC

e'bc'be'b

DC

bbc'be'be'b

e'bDC'bDCC

r)CC(2/1fwhere

f/jf1hfe

r)CC(j1hfe

)f(hfe

i)f(hfei)CC(jr/1

r/1hfeihfei

1f/jf1

hfe)f(hfe

T

DCT

)CC(2g

fhfefe'bc'b

mDCT

fT: transition frequency


fT : Gain-Bandwidth Frequency

hfe(f)(dB)

Log f0dBf fT

hfeDC

f: Beta cut-off frequency (hfe roll off 3dB)

hfe(f)=1

-20dB/decade

2b

Tn

ece'bc'b

mDCT

W2

V22

1)CC(2

gfhfef

ec: charge transit delay from emitter to collector


Transit Delay Time ec

Base length

Collectordepletion layer

Collectorsubtrate

C

EB B

0.1um

1.5um

125um c

bd

bc

ebe

ec= e+ eb+ bc+ b+ d +c


Question

If you need a BJT with at least 10dB current gain (20log|hfe|) at 300MHz, what is the minimum fT of the transistor?

hfe(f)(dB)

Log f0dBf=300MHz

fT=?

hfeDC

-20dB/decade

10dB


Answer

hfe(f)(dB)

Log f0dBf=300MHz fT=?

hfeDC

10dB


Question

If the transistor collector output port is connected with a load resistance RL

>0, the gain-bandwidth frequency fT will be decreased or increased?

hfe(f)(dB)

Log f0dB

fT=?

hfeDC

??


Miller Effect

RL

rb’e iCCb’e Cb’cCM RL

CM=(1+gmRL)Cb’c

等效寄生電容增加， fT, f 均下降


Field Effect Transistor (FET)

Channel

Substrate

Source Gate Drain

(W/WO)

Depletion Mode

DepletionRegion

Lg

tCH


Metal Semiconductor FET (GaAs MESFET)

S G D

Depletionregion

Schottkybarrier

GaAs0>VGS>VP


High Electron Mobility Transistor(AlGaAs/GaAs HEMT)

Heterojunction

VGS>VP VGS>0


Heterojunction Combinations

UndopedBuffer layer

UndopedChannel

Substrate

GaAs HEMTf<30GHz

AlGaAs GaAs GaAs

PM HEMTf<60GHz

AlGaAs InGaAs GaAs

InP HEMTmm-Wave

InAlAs InGaAs InP


Junction FET (JFET)

0>VGS>VP(-1~-3V)2

CHP tV

tCH


Metal Oxide Semiconductor FET(Depletion-mode NMOS)


Linear Empirical FET Model

Intrinsic model(Bias dependent)


Curtice-Ettenberg Intrinsic Model

Materka-KacprzakIntrinsic Model

MESFET and HEMT Nonlinear Model


Curtice-Ettenberg Cubic 　Intrinsic Model

Curtice Quadratic Intrinsic Model


Extrinsic Model


Package Model


JFET Nonlinear Model


DC Characteristic

CLY5 Materka modelID VGS

VDS

Saturation (Pinch-off) Region


Principle of Amplification(Biased at Saturation Region)

VGS

IDS Slope = gm

Input signal

Output signal

GS

DSm V

Ig

VP

2

P

GSDSSDS )

VV

1(II

IDSS


Depletion FET Transconductance gm

VGS

gm

VP

PHEMT

IDS=0.5IDSS

gCH

gDS

P

GS

P

DSS

GS

DSm Lt

WI)

VV

1(VI2

VI

g

Linear gm


Field Effect Transistor (FET)

Channel

Substrate

Source Gate Drain

(Insulator)

Enhancement Mode


Metal Oxide Semiconductor FET(Enhancement-mode NMOS)

VGS>VT (Threshold Voltage)


Enhancement-Mode MOSFET Circuit Symbols

PMOS

NMOS


MOSFET Nonlinear Model(Enhancement-Mode NMOS)


Principle of Amplification(Biased at Saturation Region)

VGS

IDS Slope = gm

Input signal

Output signal

GS

DSm V

Ig

Vt

2tGS

g

g

ox

oxnDS )VV(

L

W

t2I


MOSFET Transconductance gm

VGS

gm

Vt

g

gDStGS

g

g

ox

oxn

GS

DSm L

WI)VV(

L

W

tVI

g

Linear gm


Comparisons of FETs

相同點：橫向電流，只提供單一載子電流不同點 MESFET (P)HEMT JFET MOSFE

T

n ,vS Higher Highest Low Low

fT, fMAX Higher Highest Medium

Low

Gain (gm)

Higher Highest Medium

Low

Noise Low Lowest Low High

Substrate

High resistanc

e

High resistance

Lossy Lossy

Process III-V compoun

d

III-V compoun

d

BipolarBiCMOS

CMOS

Cost Higher Highest Medium

Cheep


Simplified Linear FET Model

ri

iDS=gmvgs’=hfe(f)*iIN

Cgs

Cgd

S S

G D

iIN

vgs’+

-

When ri are neglected at lower frequency,h21(f)=iOUT/iIN|(v2=0)=gm/jf(Cgs+Cgd)

iOUT


fT : Gain-Bandwidth Frequency

h21(f)(dB)

Log f0dBfT

h21(f)=1

-20dB/decade

D2g

n

g

S

gdgs

mT I

LL2v

21

)CC(2g

f

: charge transit delay from source to drain= channel length Lg/ electron drift velocity vS


Electron Drift Velocity v.s. Electric Field

OUTMAXTmSgdsS PGfgvL/1Iv

Shortened channel length maximizes the fT

vS

Electric Field

Ev nS


Short Channel Effects of FET

Shortening channel length Lg => fT=vS/2Lg1/Lg

GaAs FET : Let Lg large than 1umMOSFET: Modify nonlinear model

vS

Electric Field

Short channel effects (Lg<1um)

n decreased


1/f Low frequency Noise of Transistor

HEMTHBT

1/f NoiseThermal Noise


High Frequency Noise of Transistor

HBT

HEMT


Applications of Transistors

BJT HBT MESFET

(P)HEMT

JFET CMOS

LNA 5th 4th 2nd 1st 2nd 6thPA 3rd 1st 2nd 3rd 5th 6th

OSC 2nd 1st 5th 4th 2nd 6thf<6GH

z2nd 3rd 5th 5th 4th 1st

f<30GHz

4th 2nd 3rd 1st 4th X

f>30GHz

X 2nd 3rd 1st X X

Cost 2nd 5th 4th 5th 2nd 1st


Review of S Parameters

Power Wave Definition (Z0=50):

50

2221

1211

SS

SS

2

1

2221

1211

2

1

a

a

SS

SS

b

b

a1

b1 a2

b2

Port 1 Port 250


Complex Power Waves

0

11

Z

Va

0

22

Z

Va

0

11

Z

Vb

0

22

Z

Vb

2

11 aP

2

22 aP

2

11 bP

2

22 bP

IncidentWave

ReflectedWave

IncidentPower

ReflectedPower


Calculations of S Parameters

0a1

111 2a

bS

0a1

221 2a

bS

50

50

a1

b1 a2=0

b2

Port 1Port 2Matched

S11

S21

= Port 1 reflect coefficient when Port 2 is matched

= Port 1 to Port 2 transmission coefficient when port 2 is matched (gain or insertion loss)


Interpretation of Matched Port

50

50

a1

b1 a2=0

b2

Port 1Port 2Matched

S11

S21

各接面可視為由虛擬 50 傳輸線 ( 長度視為 0)連接，因此傳輸線內形成入射波 a1 and a2 與反射波 b1 and b2 。當 port 2 接上 50 負載 (matched) ， b2 直接從 50 傳輸線進入 50 負載，因此沒有反射波產生，即 a2=0 。

50 50


Calculations of S Parameters

50

50

a2

b2a1=0

b1

Port 2Port 1Matched

S22

S12

0a2

222 1a

bS

0a2

112 1a

bS

= Port 2 reflect coefficient when Port 1 is matched

= Port 2 to Port 1 transmission coefficient when port 1 is matched (reverse gain or isolation)


Calculations of S Parameters(Using Voltage Waves Definitions)

50

50Port 1 Port 2

Matched

S11

S21

+

-

++

--VS V1 V2

50

50Port 1 +

-

+

-VS

V1=V1+

Let V1-=0

V1+=V1=VS/2

STEP 1


STEP 2

50

50Port 1 Port 2

Matched

S11

S21

+

-

++

--VS V1 V2

V1=V1++V1

- => V1-=V1- VS/2

1VV2

V

Vab

SS

1

1

1

1

111

Calculations of S Parameters (Using Voltage Waves Definitions)


STEP 3

50

50Port 1 Port 2

Matched

S11

S21

+

-

++

--VS V1 V2

S

2

1

2

1

221 V

V2

V

Vab

S

V2=V2++V2

- => V2-=V2

同理可求出 S12 及 S22

V2+=0

Calculations of S Parameters(Using Voltage Waves Definitions)


Measurement of S Parameters Using Vector Network Analyzer (VNA)

Bias 1 Bias 2

VNA

Sampler

DirectionalCoupler


S parameters of BJT

Transistor

50

50

DC BiasCircuit

Example: Siemens BFP420


S11 and S22 of BFP420

IC=5mAVCE=4Vf=0.05GHz-7.68GHz

Calculated from Gummel-Poon model(Serenade 8.0)

fLOW

fHIGH


Input and Out Equivalent Circuits

Look into Base

Look into Collector


S21 and S12 of BFP420

fLOW fHIGH


S Parameters of MESFET

Transistor

50

50

DC BiasCircuit

Example: HP ATF10136


S11 and S22 of ATF10136

IDS=4.6mAVGS=-0.3VVDS=2.5Vf=1GHz-17.32GHzCalculated from Materka model(Serenade 8.0)

fL

fL fHfH


S21 and S12 of ATF10136

fLOW

fHIGH


Tabular Form of S Parameters

#GHz S MA R 50 (Touchstone Format)


Power Gain v.s. Frequency

InsertionPower Gain

Maximum Stable Gain

Maximum AvailablePower Gain

-6dB/Octave

VDS=2VIDS=25mA


Isolation of Transistor

Isolation=|S21S12|fS=transducer cutoff frequency (|S21|=1)

-20dB/decade

20dB/decade


Maximum Available Power Gain Ga,max

量測到的 S 參數可直接經由電路理論公式轉換成 hfe 及 Gmax ，不需額外再進行量測。

-20dB/decade

Ga,max=0dB


Maximum Oscillation Frequency fmax

fmax= frequency of unity maximum power gain

c'b'bb

Tmax Cr8

ff

Bipolar Transistor Field Effect Transistor

i

dsTmax r

r2f

f


Question

If you use a microwave transistor to design an amplifier of 10dB power gain at 1GHz, what is the minimum fmax of this transistor?

Ga,max(f)(dB)

Log f0dBf=1GHz

fmax=?

-20dB/decade

10dB


Answer

Ga,max(f)(dB)

Log f0dBf=1GHz fmax=3.16GHz

10dB

GHz 16 . 3 10 GHz 1 f

decade 5. 0decade / dB 20dB 10

5. 0max


How to Choose a Proper Transistor?

單級電晶體放大器的 power gain 通常設計在 10-15dB ，以避免過高的增益引起放大器電路不穩定而產生振盪。電晶體放大器最高操作頻率即為 (1/3)fmax~(1/6)fmax

例如設計 2.4GHz amplifier 時，電晶體必須選擇 fmax=7.2~14.4GHz

中華大學電機系 田慶誠 1 active devices and s-parameters session 1

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中華大學電機系田慶誠 1 active devices and s-parameters session 1