線性穩壓器 (2) Linear Regulators (2)

Instructor: Po-Yu Kuo ( 郭柏佑 )

國立雲林科技大學電子工程系

2

A typical series regulator which consists of four main building blocks:

Structure of LDO

Vref +

-

A(S)

Vin

R1

R2

Re

Co

RL

Vo

Power Transistor

Vn1

Vfb

3

Voltage Reference (Vref): a very stable voltage with respect to temperature change and input voltage variations, usually of the bandgap type.

Error Amplifier (A(s)): a very high (dc) gain opamp to achieve a close to zero error signal Verr=V+ - V-.

Feedback Network: R1 and R2 define the feedback factor and generate Vfb to be compared with Vref to get the designed output voltage Vo.

Series Pass/Power Transistor (Q1): power transistor configuration to pass high current from the source to output. As it handles large current, the size of pass transistor dominates the area of the whole series regulator.

Structure of LDO

4

Dropout Voltage (Vdo) is the minimum voltage difference between the input and output under which the regulator still able to maintain the output within the specification.

With a Li-Ion battery as Vin, Vin varies from 2.7V to 4.2V.

Vdo,max =4.2-Vov,ML

Structure of LDO

Vref +

-

A(S)

Vin

R1

R2

Re

Co

RL

Vo

Power Transistor

Vn1

Vfb

5

Structure of LDO

6

Two Categories:

Regulating (accuracy) performance

Line regulation, load regulation, temperature dependence,

transient overshoot, transient recovery time, stability

Power Characteristics

Io, Quiescent current Iq, Vin & Vo ( )

Specifications of LDO

7

Current Efficiency : where Iq is the quiescent current of LDO

In LDO design for portable applications, Io is usually much larger than Iq with > 99% efficiency

When Io is 0, Iq should be minimized (I3 should be small by large values of R1 and R2)

Efficiency

I)/( qooI III

8

Smaller dropout voltage causes a higher power conversion efficiency especially Io >> Iq

In light-load condition (small Io), the efficiency is poorer as I1, I2, and I3 are close to Io

Efficiency

9

VSD must be always larger than Vov at different conditions Design at the worst case: largest Vov at Io(max) and μp(min)

at the maximum temperature By using minimum L (the smallest transistor and hence

parasitic capacitance), keep increasing W until meeting the dropout specification

IR at the routing metals increase VDO

Design margin by experience-generally the chosen W is 1.1-1.2 times of the theoretical W

Dropout Voltage and Power-Transistor Sizing

10

Load Regulation (R): closed-loop output resistance of LDO Ro is the open-loop output resistance of the pass transistor

as Rf1, Rf2 >> Ro

Better load regulation is achieved by smaller Ro (using minimum channel length of the pass transistor) and larger loop-gain magnitude

As Ro 1/Io, high Io range gives better load regulation

Load Regulation

11

gmp is the transconductance of power PMOS transistor Line regulation is independent of the gain of the power

transistor Line regulation can be improved by a high-gain error amplifier Other error sources on line regulation are voltage reference

and offset voltage of the error amplifier

Line Regulation

12

Gm and Ro can be found individually Input-Output voltage gain can be found by the product of

Gm and Ro

Review on Voltage Gain

13

Voltage gain of the error amplifier is not the only parameter to improve line regulation

Good designs on supply independence of Vref and reducing systematic offset of error amplifier are very important

Line Regulation Including Other Errors

14

Variation of Vo at different temperature depends on both voltage reference and error amplifier design

Rf1 and Rf2 must be made by the same material and closely placed

Temperature Coefficient

15

Load Transient Response

16

Better load transient response by tresp ↓, Co ↑, Re ↓ and Lc ↓ .

Load Transient Response

17

AC Design (1): Loop-Gain Analysis

18

AC Design (2): Loop-Gain Analysis

19

AC Design (3): Loop-Gain Analysis

20

AC Design (4): Loop-Gain Analysis

ze should cancel p2 within one decade of frequency for stability

Parasitic pole(s), ppar, must be far away from the unity-gain frequency (UGF)

Different UGFs are resulted from different Re values such as ze locating before or after p2

p2 locates at very low frequency as Cpa and ra are large

Required large Co and Re

Large Co is unfavorable in the cost consideration

Low-frequency pole-zero cancellation is unfavorable to load transient recovery time

21

LDO with Voltage Buffer

Smaller required Re can be achieved by inserting a low output-resistance (1/gmb) voltage buffer

One more pole (p3) is created but is located at high frequency due to small output resistance of the voltage buffer

p2 (with voltage buffer) locates at a higher frequency than the one without voltage buffer (Cb << Cg)

22

Effect of Load Currents on Stability

Loop gain is larger when Io is smaller due to gmpro 1/ √Io

p1 is lower when Io is

smaller due to larger ro of the power transistor (ro 1/Io)

Worst-case stability at maximum Io

Compensation at max. Io

23

Effect of Loop-Gain Magnitude on Stability

Larger loop gain by increasing ra of the error amplifier

p2 → p2’

A larger Re is needed to create a zero at lower frequency (ze → ze’)

Larger loop gain → more unstable as p3 may be below the UGF of loop gain

A larger Co is generally needed

24

Loop Gain Simulation

25

Summary of LDO Specifications

26

Circuit Implementations

Circuit of LDO consists of R1 and R2

Cin and Co

Vref

Error Amplifier Voltage Buffer Power Transistor

Vin,min = Vov,Me1 + Vgs,Mb2 + Vgs,Mp Low-voltage operation impossible!

27

Circuit Implementations

BJT has a small VBE drop (~0.7V) The circuit can operate at lower input supply compared

to the previous case Smaller input capacitance for small VBE Base current introduces larger offset voltage and hence

degrades accuracy of the output voltage