9

9.1 F240xEVAEVB 2GP33(QEP) EVAEVBEVA7400hEVB7500h

EVAEVB

CPUCPUCPU

9.1.1 A

B

9.1.2 EVA

EVB

EVA

EVB

EVA

EVB

EVA

EVB

9.1.3 13ABC EV

A(EVA)

B(EVB)

EV

21EVAIMRx1PIE

3CPU PIEPIVRISR1

4PIVRBACC 20CPU

25CPU 8CPU 16CPU

5EVxIFRx 160

EVAAEVAIFRA742Fh R = W1C = 1 _0 =

15~1110T1OFINT FLAG101019T1UFINT FLAG101018T1CINT FLAG101017T1PINT FLAG101016~4

3CMP3INT301012CMP2INT201011CMP1INT101010 0101

EVABEVAIFRB7430h

15~43T2OFINT FLAG201012T2UFINT FLAG201011T2CINT FLAG201010T2PINT FLAG20101

EVACEVAIFRC7431h

15~32CAP3INT FLAG301011CAP2INT FLAG201010CAP1INT FLAG10101

EVAAEVAIMRA742Ch

15~1110 T1OFINT ENABLE1 0 19 T1UFINT ENABLE1 0 18 T1CINT ENABLE1 0 17 T1PINT ENABLE1 0 1

6~43CMP3INT ENABLE3012CMP2INT ENABLE2011CMP1INT ENABLE1010 ENABLE01

EVABEVAIMRB742Dh

15~43T2OFINT ENABLE2012T2UFINT ENABLE2011T2CINT ENABLE2010T2PINT ENABLE201

EVACEVAIMRC742Eh

15~32CAP3INT ENABLE3011CAP2INT ENABLE2010CAP1INT ENABLE101

EVBAEVBIFRA752Fh

EVBBEVBIFRB7530h

EVBCEVBIFRC7531h

EVBAEVBIMRA752Ch

EVBBEVBIMRB752Dh

EVBCEVBIMRC752Eh

9.2 9.2.1 EVA12EVB34 CPUCPU1/4

QEPPWMPWM

9.2.2 x=24x=2y=1n=2x=4y=3n=4

1 CPU TCLKINA/BCPU1/4 TDIRA/B/ RESET

2 TxCMPx=1234 ADCA/D

3. 116TxCON 216TxCMPR 316TxPR 4 16/TxCNT5TDIRx 67prescaler 84

11TxCON TxCON 4 CPU 1/128~1 21EVA 43EVB

XTxCONx=1234 7404hT1CON7408hT2CON7504hT3CON7508hT4CON + T1CONT3CON R = W = -0 =

15~14FreeSoft0001101113012~11TMODE1TMODE000/01/1011//TDIRA/BTDIRA/BTDIRA/B

10~8TPS2TPS0000X/1001X/2010X/4011X/8100X/16101X/32110X/64111X/128X=CPU7T2SWT1/ T4SWT1240241T1CONT3CON6TENABLE01

5~4TCLKS1TCLKS000CPU0110112413SELT1PR=0

3~2TCLD1TCLD00000101011

1TECMPR01

0SELT1PR241301T1PREVAT3PREVB

2 GPTCONA/BAGPTCONA7400h

1514T2STAT20113T1STAT10112~11

10~9T2TOADC2000110118~7T1TOADC100011011

CPUFFFFh0000hCPU

6TCOMPOEPDPINTx0015~4

3~2T2PIN200011011

1~0T1PIN100011011

BGPTCONB7500h

2 GPTCONA/BADC 7402hT1CMPR7406hT2CMPR 7502hT3CMPR7506hT4CMPR

3GPTCONA/B32 // // ///

4 7403hT1PR7407hT2PR 7503hT3PR7507hT4PR

5 TxCMPRTxPR

TxCON 0 0TxCNT

0

4. QEP/24 41CPU1/4

5. 21EVA43EVB

1EVAT1CONTENABLE1 T2CONT2SWT11 12T2CONSELT1PR121

2EVBT3CONTENABLE1 T4CONT4SWT31 34T4CONSELT3PR143

9.2.3 4 / / /x/1TxCONTxCON[12~11]

1/0 2 1CPUTDIRA/B

1A/DCPUA/DA/D1GPTCONA/BA/D

2GPTCONA/BA/D0CPUA/DA/D

20000h~FFFFhFFFFh00000

TxPR+10

1LDP#DP_EVA7400h-7480hSPLK#41HGPTCONATCOMPOE=1 SPLK#5HT1PRSPLK#3HT1CMPRSPLK#0HT1CNTSPLK#0174EHT1CONTMODE=10 TPS=111 128TENABLE=1 TCLKS=00 TECMPR=1 1SELT1PR=0

3/TDIRA/B TDIRA/BTDIRA/BFFFFh0TDIRA/B0TDIRA/B0

0000h~FFFFhTDIRA/BFFFFh0TDIRA/B00

TDIRA/BCPUCPU TCLKINA/BCPU

/

1/LDP#DP_EVA7400h-7480hSPLK#41HGPTCONATCOMPOE=1 SPLK#5HT1PRSPLK#3HT1CMPRSPLK#0HT1CNTSPLK#01F4EHT1CONTMODE=11 /TPS=111 128TENABLE=1 TCLKS=00 TECMPR=1 1SELT1PR=0

4 ///TDIRA/BFFFFh0

0000h~FFFFhFFFFh0/00/00

2TxPR0 TCLKINA/BCPUTDIRA/B

/

1/LDP#DP_EVA7400h-7480hSPLK#41HGPTCONATCOMPOE=1 SPLK#5HT1PRSPLK#3HT1CMPRSPLK#0HT1CNTSPLK#0F4EHT1CONTMODE=01 /TPS=111 128TENABLE=1 TCLKS=00 TECMPR=1 1SELT1PR=0

/PWM PWM/24 PWM

9.2.4 TxCON.11 1CPU 1CPUGPTCONA/BPWM GPTCONA/BA/DA/D

PWMTxPWM 4PWMPWM PWM/PWM

PWM PWMTxPR TxCONPWM PWMTxCMPRTxCMPR

1PWM GPTCONA/B /

2 0 0001 PWM1

/PWMPWMPWM

0~100PWM 0100

3 0 00PWM

//PWM

0~100PWM0110100

2. PWM GPTCONA/BPWMPWMPWMPWM/PWM1/0

PWM 1

2/

PWM GPTCONA/B[6]0 PDPINx TxCON[1]0

9.2.5 GPTCONA/B01 0 0

9.2.6 11ms 6MHzDSP424MHz1641ms0177H

11T1CNT0177h1mSCPUCPU;INT2GISR2;GISR2PIVR0027h1T1PINT_ISR

INT20004HT1PINT0027H .include "F2407REGS.H" .def _c_int0 .sect".vectors"RSVECTB _c_int0PM 0 1INT1 B PHANTOMPM 2 1 4INT2 B GISR2PM 4 2 5INT3 B PHANTOMPM 6 3 6INT4 B PHANTOMPM 8 4 7INT5 B PHANTOMPM A 5 8INT6 B PHANTOMPM C 6 9RESERVED B PHANTOMPM E ()10SW_INT8 B PHANTOMPM 10 - SW_INT31 B PHANTOMPM 3E -

pvecs .sect".pvecs"PVECTORSBPHANTOM 00H BPHANTOM 01H BPHANTOM 26HBT1PINT_ISR 27H T1PINTBPHANTOM 28H BPHANTOM 41H

.text_c_int0 SETC INTM CLRC SXM CLRC OVMCLRC CNFB0 LDP #0E0H7000h-7080h SPLK #81FEHSCSR1 4CLKIN=6MLKOUT=24M SPLK#0E8HWDCRWDT LDP#0SPLK#02HIMRINT2SPLK#0FFFFhIFRLDP#DP_EVA7400h-7480hSPLK#80HEVAIMRAT1PINT SPLK#0FFFFhEVAIFRAEVASPLK#0GPTCONASPLK#177HT1PR1msSPLK#0T1CNTSPLK#0164CHT1CONTMODE=10 TPS=110 64TENABLE=1 TCLKS=00 TECMPR=1 1SELT1PR=0 CLRCINTM WAITNOP BWAIT

GISR2INT2LDP #0E0HLACC PIVR1PIVRADD #PVECTORSBACCT1PINT_ISR1LDP #DP_EVASPLK #0T1CNTGISR2_RETCLRC INTMRETPHANTOM KICK_DOG RETEND

2C1DSP2112INT2vectors.asmINT2132INT2111T1PINT FLAGEVAIFRA814

// vectors.asm .ref _nothing .ref _c_int0 .sect ".vectors"RSVECT B _c_int0 PM 0 1INT1 B _nothing PM 21 4INT2 B _T1INT PM 42 5INT3 B _nothing PM 63 6INT4 B _nothing PM 84 7INT5 B _nothing PM A5 8INT6 B _nothing PM C6 9

//// 11ms#include"register.h"// void inline disable() {asm(" setc INTM")}// void inline enable(){asm(" clrc INTM") }

// initial(){asm(" setcSXM")// asm(" clrcOVM")// asm(" clrcCNF")// B0*SCSR1=0x81FE// CLKIN=6MCLKOUT=4*CLKIN=24M*WDCR=0x0E8// SCSR2WDOVERRIDEWD1*IMR=0x0002// INT2*IFR=0x0FFFF// "10"WSGR=0X00// }

// 1int timer1int(){*EVAIMRA=*EVAIMRA|0X0080// 1*EVAIFRA=*EVAIFRA&0X0080// 1*T1CON=0X160C// Timer164*T1PER=0X0177// Timer11ms*T1CNT=0X00// Timer1}

// 1void interrupt T1INT(){int flag// flag=*EVAIFRA&0X0080if(flag!=0x0080){enable( )// return// 1}

// 11*T1CNT=0X00// 10*EVAIFRA=*EVAIFRA&0X0080// 1enable( )// return// }

// // voidinterrupt nothing(){enable( )// return// }

// main(){disable()// initial()// timer1int()// 1enable()// *T1CON=*T1CON|0X0040// Timer1while(1){// }}

9.3 EVA3123EVB3456 PWM PWM1EVA3EVB

316 EVACMPR1CMPR2CMPR3 EVB CMPR4CMPR5CMPR6 / / EVACOMCONA EVB COMCONB 16 EVAACTRA EVBACTRB / 6PWM EVAPWMyy=123456 EVBPWMzz=789101112

1/ 13T1CNTT3CNT

2COMCONx PWM

1ACTRAACTRA

1PWM

3

4 EVAIFRAEVBIFRA 1CPU 0

5 COMCONACOMCONB 1ACOMCONA7411h

15CENABLE0CMPRxACTRA114~13CLD1CLD0CMPRx00T1CNT=001T1CNT=0T1CNT=T1PR1011

12SVENABLEPWM0PWM1PWM11~10ACTRLD1ACTRLD000T1CNT=001T1CNT=0T1CNT=T1PR1011

2AACTRA7413h

15SVRDIRPWMPWM0CCW1CW14~12D2D0PWM11~10CMP6ACT1-0PWM6/IOPB3000110119~8CMP5ACT1-0PWM5/IOPB200011011

7~6CMP4ACT1-0PWM4/IOPB1000110115~4CMP3ACT1-0PWM3/IOPB0000110113~2CMP2ACT1-0PWM2/IOPA7000110111~0CMP1ACT1-0PWM1/IOPA600011011

3BCOMCONB7511h

4BACTRB7513h

9.4 PWM8PWM3632PWMGP

PWM 16 0~16sPWM 1CPU PWMPWM PWMPWM 4PWM CPU

9.4.1 PWM / DBU PWM

PWM

1 /16DBTCONx X/1X/2 X/4X/8X/16X/32 CPU 34

ADBTCONA7415h

15~1211~8DBT3DBT047EDBT333PWM5PWM6016EDBT222PWM3PWM401

5EDBT111PWM1PWM2014~2DBTPS2DBTPS0000X/1001X/2010X/4011X/8100X/16101X/32000X/32001X/321~0

2PH1PH2PH3123/DTPH1DTPH1_ DTPH2DTPH2_ DTPH3DTPH3_PH1PH2PH3

BDBTCONB7515h

3

Dead bandDBTCONx.11~8mDBTCONx.4~2x/ppmCPU DBTCONx

42PWM 1000 PWM

5PWMxx=1~12 PWMACTRx

PWM COMCONx[9] PDPINTxPDPINTx DTPH1DTPH1_DTPH2DTPH2_DTPH3DTPH3_ ACTRx

PWMxx=1~6EVA PWMyy=7~12 EVB

9.4.2 PWMPWMPWM 1PWM ACTRx DBTCONx T1PRT3PRPWM CMPRX COMCONx T1CONT3CON CMPRxPWM

1PWM11 21PWM 3COMCONAPWM PWM

4DBTCONA[11~8]4PWM5ACTRAPWMPWMPWM

1PWMPWMT1PRACTRA

2. PWM PWM PWMPWM/

PWM

9.4.3 PWM1PWM ACTRx COMCONxPWMCMPRx 13/

d-qUoutUoutPWM UxUx+60 T1T2T0 UxACTRx.14~121ACTRx.15Ux+60ACTRx.14~120ACTRx.15 T1/2CMPR1T1+T2/2CMPR2

2PWM PWMACTRx.14 ~12Uy CMPR113ACTRx.150PWMUy+60ACTRx.151PWMUyU0-60=U300U360+60=U60 CMPR213T1+T2/2 PWM0001111 CMPR213PWM CMPR113PWM

3PWMCMPR1CMPR203 PWMCMPR1CMPR2T1PR

4PWMPWMPWMPWM

9.4.4 PWMPWM7~PWM12PWM7PWM9PWM11PWMPWM8PWM10PWM12PWMEVB3

1.include "F2407REGS.H" .def _c_int01.sect".vectors"RSVECTB _c_int0PM 0 1INT1 B PHANTOMPM 21 4INT2 B GISR2PM 42 5INT3 B PHANTOMPM 63 6INT4 B PHANTOMPM 84 7INT5 B PHANTOMPM A5 8INT6 B PHANTOMPM C6 9RESERVED B PHANTOMPM E () 10SW_INT8 B PHANTOMPM 10 - SW_INT31 B PHANTOMPM 3E -

pvecs.sect".pvecs"PVECTORSBPHANTOM -00H BPHANTOM -01H BPHANTOM -2EHBT3GP_ISR -2FH T3PINTBPHANTOM -30H BPHANTOM -41H

2.text_c_int0 CALLSYSINITCALLPWM_INITEVBPWMWAITNOPBWAIT

3SYSINITSETC INTMCLRC SXM CLRC OVMCLRC CNFB0 LDP #0E0H7000h-7080h SPLK #81FEHSCSR1 4CLKIN=6MCLKOUT=24M SPLK#0E8HWDCRWDT LDP#0SPLK#0002HIMR2INT2SPLK#0FFFFHIFRRET

4EVBPWMPWM_INITLDP#DP_PF27080h-7100hLACLMCRCOR#007EHIOPE[1-6] PWM[7-12]SACLMCRCLDP#DP_EVB7500h-7580hSPLK#0FFFFHEVBIFRAEVB SPLK#0666HACTRBPWM12108 PWM1197 SPLK#00HDBTCONBSPLK#10HCMPR4 PWM750/60 10/60SPLK#20HCMPR5PWM910SPLK#30HCMPR6PWM1112SPLK#60HT3PR3PWM60CPUSPLK#0A600HCOMCONBSPLK#0T3CNTSPLK#41HGPTCONBTCOMPOE=1T3PIN=01SPLK#080HEVBIMRA3SPLK#0174EHT3CONTMODE=10 TPS=111 128,TENABLE=1 TCLKS=00 ,TECMPR=1 3 SELT3PR=0 CLRCINTMRET

53GISR2INT2LDP#0E0HLACCPIVR1PIVRADD#PVECTORSBACCT3GP_ISR3LDP#DP_EVBSPLK#0T3CNTGISR2_RETCLRCINTMRET

6PHANTOM KICK_DOGRETEND

Cvectors.asm// .ref_nothing.ref_c_int0 .sect ".vectors"RSVECT B _c_int0 // PM 0 1 INT1 B _nothing// PM 214 INT2 B _nothing// PM 4 25 INT3 B _nothing// PM 6 36 INT4 B _nothing // PM 8 47 INT5 B _nothing // PM A 58 INT6 B _nothing // PM C 69

// EVBPWM7PWM12#include"register.h"// void inline disable() {asm(" setc INTM")}

// int initial(){asm(" setcSXM")// asm(" clrcOVM")// asm(" clrcCNF")// B0*SCSR1=0x81FE// CLKIN=6MCLKOUT=4*CLKIN=24M*WDCR=0x0E8// SCSR2WDOVERRIDE // WD1*IMR=0x0000// *IFR=0x0FFFF// "10"WSGR=0X00// }

// EVBPWMint pwminitial(){*MCRC=*MCRC|0X007E// IOPE1-6PWM7-12*ACTRB=0X0666// PWM12108 PWM1197 *DBTCONB=0X00// *CMPR4=0X1000*CMPR5=0X3000*CMPR6=0X5000*T3PER=0X6000// 3CMPR4-6*COMCONB=0X8200// *T3CON=0X1000// 3}

// voidinterrupt nothing(){return// }

// main( ){disable()// initial()// pwminitial()// PWM*T3CON=*T3CON|0x0040// 3while(1){}}

9.5 9.5.1 CAPxEVAx123EVBx456GP2FIFO

EVA

116CPACONx/ 116FIFOCAPFIFOx 1/2EVA3/4EVB 6162FIFOCAPxFIFO 3EVACAP123EVBCAP456 6

CPUCPUCAP12CAP45 CAP1CAP2CAP312CAP1CAP2 CAP4CAP5CAP634CAP4CAP5

9.5.2 FIFOFIFOFIFOCAPFIFOxFIFO 2CPU

1 FIFOCAPFIFOx0 CAPCONx

21ACAPCONA7420h

15CAPRES000114 ~13CAPQEPN120012FIFO0112101112CAP3EN303FIFO13

1110CAP3TSEL302119CAP12TSEL1202118CAP3TOADC301CAP3INT

7 ~6CAP1EDGE1000110115 ~4CAP2EDGE2000110113 ~2CAP3EDGE3000110111 ~0

2FIFOACAPFIFOA7422h

15 ~1413 ~12CAP3FIFO3FIFO0001101111 ~10CAP2FIFO2FIFO00011011

9 ~8CAP1FIFO1FIFO000110117 ~0

3BCAPCONB7520h

4FIFOBCAPFIFOB7522h

3FIFO2FIFO EVACAP1FIFOCAP2FIFOCAP3FIFOEVBCAP4FIFOCAP5FIFOCAP6FIFOEVACAP1FBOTCAP2FBOTCAP3FBOTEVBCAP4FBOTCAP5FBOTCAP6FBOT

FIFOFIFOFIFO

FIFOFIFO101101FIFO0100

1 CAPFIFOxFIFO01FIFOFIFO00

2 CAPFIFOxFIFO10FIFOFIFO01

3 FIFOFIFO11

4 FIFOFIFOFIFO

9.5.3 4CAP4BEVB3

128 DSP F24073.3V3.3V

1CAP4TEMP.usect ".data0"1CAP4 .include "F2407REGS.H" .def _c_int0

.sect".vectors"RSVECTB _c_int0PM 0 1INT1 B PHANTOMPM 2 1 4INT2 B PHANTOMPM 42 5INT3 B PHANTOMPM 6 3 6INT4 B GISR4PM 84 7INT5 B PHANTOMPM A 5 8INT6 B PHANTOMPM C 6 9RESERVED B PHANTOMPM E() 10SW_INT8 B PHANTOMPM 10 - SW_INT31 B PHANTOMPM 3E -

pvecs.sect".pvecs"PVECTORSBPHANTOM-00H BPHANTOM-01H BPHANTOM-35HBCAP4_ISR-36H CAP4BPHANTOM-37H BPHANTOM-41H

.text_c_int0 LDP#5SPLK#00HCAP4TEMPCALLSYSINITCALLCAP_INITCAP4WAITNOPBLOOP

SYSINITSETC INTMCLRC SXM CLRC OVMCLRC CNFB0 LDP #0E0H7000h-7080h SPLK #81FEHSCSR1 4CLKIN=6MCLKOUT=24M SPLK#0E8HWDCRWDT LDP#0SPLK#0008HIMR4INT4SPLK#0FFFFHIFRRET

CAP_INITLDP#DP_PF27090H7100HLACLMCRCOR#0380H IOPE7 IOPF0 IOPF1 CAP[4-6]SACLMCRCSETC INTMLDP#DP_EVBSPLK #049HGPTCONBTCOMPOE=1 T4PIN=10T3PIN=01 SPLK#0T3CNTSPLK #01742HT3CON TMODE=10 TPS=111 128TENABLE=1 TCLKS=00 TCLD=00 TECMPR=1 3 SELT3PR=0

SPLK #0FFFFHT3PRSPLK #00HEVBIMRASPLK #00HEVBIMRBSPLK #22C0HCAPCONB CAP4SPLK #01HEVBIMRCCAP4 SPLK #0FFFFhEVBIFRA EVB SPLK #0FFFFhEVBIFRBSPLK #0FFFFhEVBIFRCCLRC INTM RET

GISR4INT4LDP#0E0HLACCPIVR1PIVRADD#PVECTORSBACCCAP4_ISR4LDP #DP_EVBLACLCAP4FIFOLDP#5SACLCAP4TEMPLDP#DP_EVBSPLK#0T3CNT T3 GISR2_RETCLRCINTMRET

PHANTOM KICK_DOGRETEND

2Cvectors.asm// .title"vectors.asm".ref_c_int0_nothing_capint.sect".vectors"reset:b_c_int0int1:b_nothingint2:b_nothingint3:b_nothingint4:b_capintint5:b_nothingint6:b_nothing

#include "register.h"// int result[10]// int k=0// DSPCAPTURETIMER1PWM CAP4CAP4PWM1010result[10]

// int initial(){ asm(" setc INTM")// asm(" setcSXM")// asm(" clrcOVM")// asm(" clrcCNF")// B0SCSR1=0x81FE// CLKIN=6MCLKOUT=4*CLKIN=24MWDCR=0x0E8// SCSR2WDOVERRIDEWD1IMR=0x0000// IFR=0x0FFFF// "10"}

// 4int CAP4INT() { T3PER=0X0FFFF// 30XFFFFT3CON=0X1400// 3T3CNT=0X00// 0 WSGR=0x0000// CAPCONB=0X0A440// 4 //TIMER3 asm(" clrc INTM")// IMR=0X08 // 4EVBIMRC=EVBIMRC|0X0001// CAPTURE4 EVBIFRC=EVBIFRC|0X0FFFF}

// 1PWMint timer1int(){MCRA=MCRA|0X1000// IOPB41MCRC=MCRC|0X0080// IOPE7GPTCONA=GPTCONA|0X0042T1PR=0X1FE// 1T1CON=0X1442 // TIMER1//TIMER1T1CNT=0X00// 10T1CMP=0X0FF// 1}

// main(){ initial()// timer1int()// 1PWMCAP4INT()// 4T3CON=T3CON|0X0040 // 3while(1){if(k==10) break// k}asm(" setc INTM")// 10}

// void interrupt nothing(){asm(" clrc INTM")// return}

// void interrupt capint(){ int flag flag=EVBIFRC&0X01// CAP4 if(flag!=0x01) {asm(" clrc INTM")// return// CAP4 } load()// CAP4 EVBIFRC=EVBIFRC|0x01"1"CAP4asm(" clrc INTM")// return// }

// int load(){result[k]=CAP4FIFO// // k++}

9.6 9.6.1 EVEVACAP1/QEP1CAP2/QEP2EVBCAP4/QEP3CAP5/QEP4

2EVB4/

9.6.2 900

1EV CAP1QEP1EVBCAP4QEP3CAP2QEP2EVBCAP5QEP4 424

/

2TDIRA/BTCLKINA/B;

3 1EVA 2 T2CON2/2 CAPCONA

2EVB 4 T4CON4/4 CAPCONB

9.6.3 F240xIOPE1IOPE2 IOPE1IOPE2QEP1QEP2

C 1vectors.asm// .title"vectors.asm".ref_c_int0_nothing.sect".vectors"reset:b_c_int0int1:b_nothingint2: b_nothingint3:b_nothingint4:b _nothingint5:b _nothingint6:b_nothing

2// F240XEVBQEP #include "register.h"// initial(){ asm(" setc INTM")// asm(" setcSXM")// asm(" clrcOVM")// asm(" clrcCNF")// B0SCSR1=0x81FECLKIN=6MCLKOUT=4*CLKIN=24MWDCR=0x0E8// SCSR2WDOVERRIDE WD1IMR=0x0000// IFR=0x0FFFF// "10"}

// QEPint QEPINT(){T4PR=0X0FFFF// 40XFFFFT4CON=0X1870// 4 T4CNT=0X00// 0 WSGR=0x0000// CAPCONB=0X0E000// EVBQEP}

// I/Oint IOINT(){MCRC=MCRC|0X0180// I/O PEDATDIR=PEDATDIR|0X0606// IOPE1IOPE2}

// int DELAY( ){ int k for(k=0k

// main(){initial()// IOINT()// I/OQEPINT()// QEPwhile(1){PEDATDIR=PEDATDIR&0xFFFB// IOPE2DELAY()// PEDATDIR=PEDATDIR&0xFFFD// IOPE1DELAY()// PEDATDIR=PEDATDIR|0X0004// IOPE2DELAY()// PEDATDIR=PEDATDIR|0X0002// IOPE1DELAY()// }}

// // void interrupt nothing( ){return}