“ Analyzer for 40Gbit Ethernet “(Bi-semestrial project)

Executers: ' נה מחאג Farid Mahajna 200619716פריד

Husam Kadan קעדאן 301461703חוסאם

אפיון מצגתCharacterization

Presentation

Instructor: Mony Orbach

Starting at semester: winter 2010/2011Date: 15-11-2010

AgendaWhat is a communication channel ?Our projects goalsWork environmentDevelopment – High level architectureDevelopment – Testing EvironmentGantt ChartQuestions

Communication ChannelA channel is used to convey an information

signal, for example a digital bit stream, from one or several senders (or transmitters) to one or several receivers.

Com. Channels are everywhere.

Two important parameters: speed bandwidth

What is the final Goal ?

Two stages:1. Building the physical layer (first semester)o Reaching a point we can send and receive data

2. Implements Ethernet protocol (second semester)

“Building a high speed communication channel - 40Gbit”

Work EnvironmentHardware side:Virtex-6 FPGA ML605 Evaluation Kit – the

boardMezzanine CardEthernet ProtocolAuroraSerDesSoftware side (tools):ISE 12.3 version

Work Environment

FPGA

The mezzanine card sets here

(HPC inputs)

DDR

Virtex-6 FPGA ML605 Evaluation Kit

Mezzanine Card

Work Environment

Work EnvironmentA Serializer/Deserializer (SerDes) is a pair of

functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each direction.

One By One

Aurora

Aurora takes a data packet (Bit stream) and divide it into several synchronized parallel channels.

Aurora is a block in the ISE library.

This is one of the most important parts of our project.

DevelopmentHigh level architecture on the FPGA

Transmitter receiver

MEM MEMMEM MNG MEM MNG

Aurora Aurora

Physical layer

SerDesSerDes

Development

Testing Env. - 2 PortsTesting Env. - One Port

The Board

FPGA

The Board

FPGA

Mezzanine CardOutput

Pin

Input Pin

Starting with one port channel…

SMA Connectors

Board A Board B

Mezzanine Card Mezzanine Card

FPGA

…ending with 4 parallel

Development

Testing Env. - 4 parallel ports

FPGA

Gantt Chart(Till the middle of the semester)

Questions