华人芯片设计 - icac workshop

4月10日至12日 | 中国.成都

会议WORKSHOP手册

PROGRAM

华人芯片设计技术研讨会

华人芯片设计技术研讨会 2019

Workshop on IC Advances in China (ICAC) 2019

1

目录 Contents

Welcome Letter 2

Organizations 3

Conference Agenda 4

Keynote Speakers 9

Regular Speakers 15

i. Session 1. Analog and Mixed-Signal 15

ii. Session 2. Power Management 19

iii. Session 3. Wireless and Wireline 23

iv. Session 4. Digital and Emerging Directions

dDdadadadDrddDDDDirections

27

v. Session 5. Wireless and Wireline 31

Conference Committees 36

Venue 37

Special Thanks 38

2019 年华人芯片设计技术研讨会


2

会议议题 Welcome Letter

On behalf of the ICAC 2019 Organizing Committee, it is our pleasure to welcome you to the Workshop on IC Advances in China (ICAC) 2019 held in Chengdu, China, from 10-12 April 2019. ICAC 2019 is to build a platform for the academia and industry people in China to have more open technical discussions, and to generate possible collaborations, and to brainstorm new ideas and directions. Therefore, we are gathering the top Chinese IC design scholars/engineers who published ISSCC and/or JSSC in the past two years, and try to attract more attendees from the IC industry. We hope the workshop speakers and audiences produce chemical reactions, as well as electrical resonances as our logo shows. We look forward to meeting you and hope that you will enjoy the conference and the vibrant city of Chengdu!

ICAC 2019 Organizing Committee



3

会议议题 Organizations

Organizers

电子科技大学

澳门大学

电子科技大学低功耗集成

电路与系统研究所

澳门大学模拟与混合信号

超大规模集成电路国家重

点实验室

Sponsored by

华为技术有限公司

海思半导体有限公司

Cooperation Media

Co-organizer

成都亚昂学术会议有限公司



4

会议议题 Conference Agenda

Conference Time：2019.4.10~2019.4.12.

2019.4.10

10:00~18:00 Participants check-in & Materials Collection(2nd floor of the hotel)

2019.4.11

8:15~8:20 Welcome Address & Conference

Opening Remarks

8:20~12:00 Technical Talks

12:00~14:00 Luncheon Talk


2019.4.12 8:20~12:00 Technical Talks

12:00~14:00 Luncheon Talk


※Note: The dinner time of Shunxing Tea House is from 7:00 to 21:00 p.m. We provide

chartered service from the lobby of Rhombus Park Aura Chengdu Hotel to Shunxing Tea House. The boarding time is 6:00 p.m. The dinner is only for participants registered at non-student prices.

2019.4.10 Venue

10:00~18:00 Participants check-in 2nd floor of Rhombus Park Aura

Chengdu Hotel

18:00~21:00 Welcome Reception Shunxing Tea House

（for non-student participant only）



5

会议议题 2019.4.11/Morning

Venue：4+5 Meeting Room（4th floor）

Welcome Address & Conference Opening Remarks

8:15~8:20 Qiang Li

Keynote Speech Chair：Yan Lu

Time Presenter Affiliation Presentation Title

8:20~9:10 Zhiliang Hong Fudan University The Development and

Application of SIMO Power Management

9:10~10:00 Nanjian Wu

Institute of Semiconductors,

Chinese Academy of Sciences

Vision Chips

10:00~10:20 Tea Break Venue: Outside the conference room

Session One. Analog and Mixed-Signal

Chair：Nan Sun


10:20~10:45 Huaqiang Wu Tsinghua University

Novel Security Chip Implementation with RRAM Using Intrinsic Randomness

Source

10:45~11:10 Sai-Weng Sin University of Macau The Design of High Linearity

Multi-bit Continuous-Time Sigma-Delta Modulator

11:10~11:35 Qiang Li University of Electronic

Science and Technology of China

Low-Voltage ADCs: Inverter-Based and

Time-Based Approaches

11:35~12:00 Chi-Hang Chan University of Macau More than Figure-of-Merit ADC Design Perspective

Luncheon Talk Chair: Nanjian Wu

Restaurant: 2nd floor of the hotel

12:00~14:00 Zhiliang Hong Fudan University Stories of China IC

Development in the Past Half Century



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会议议题 2019.4.11/Afternoon


Session Two. Power Management

Chair：Lin Cheng


14:00~14:25 Wenhui Qin Analog Devices,

Shanghai

An 800-mW Fully Integrated Galvanic Isolated Power Transfer System Meeting

CISPR 22 Class B Emission Levels with 6dB Margin

14:25~14:50 Yue Zhuo Analog Devices,

Beijing

A 52% Peak-Efficiency >1W Isolated Power Transfer System

Using Fully Integrated Magnetic-Core Transformer

14:50~15:15 Mo Huang South China University

of Technology Overview of Digital Low Dropout

Regulators

15:15~15:40 Yuan Gao Hong Kong University

of Science and Technology

AC Input Inductor-Less LED Driver for Efficient and Smart

Lighting

15:40~16:00 Tea Break

Venue：Outside the conference room

Session Three. Wireless and Wireline

Chair：Qiang Li


16:00~16:25 Baoyong Chi Tsinghua University Circuit Techniques for CMOS

Mm-Wave Radar Transceivers

16:25~16:50 Hongtao Xu Fudan University Energy-Efficient and

Area-Saving Techniques in Digital Power Amplifiers

16:50 ~17:15 Jun Yin University of Macau Waveform-Shaping CMOS VCO

for Wireless Communication

17:15~17:40 Kai Kang University of Electronic

Science and Technology of China

Wideband CMOS mm-Wave Circuits Design for 5G

Communications

17:40~18:00 Open Discussions

18:00~18:20 Group Photo

Venue: Lobby of the hotel

19:00~21:00 Banquet

Venue: 2+3 meeting room (The 4th floor of the hotel)



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会议议题 2019.4.12/Morning


Keynote Speech

Chair：Qiang Li


8:20~9:10 Xiaoyang Zeng Fudan University Gigapixel Camera: From the

System to Chip Level Solution

9:10~10:00 Pui-In Mak University of Macau Towards Energy-Autonomous Bluetooth-Low-Energy Radios

for IoT Applications

10:00~10:20 Tea Break


Session Four. Digital and Emerging Directions

Chair：Sai-Weng Sin


10:20~10:45 Shouyi Yin Tsinghua University Embedding AI in Everything: High Energy Efficient Neural Network Processor Design

10:45~11:10 Guoxing Wang Shanghai Jiao Tong

University

Intelligent and Low Power Integrated Circuits for

Bio-Applications

11:10~11:35 Yongpan Liu Tsinghua University Leveraging Varying Sparsity in

Energy Efficient Neural Network Accelerator Design

11:35~12:00 Zhuo Zou Fudan University Circuits Advances for Edge

Intelligence in IoT Applications

Luncheon Talk Chair: Nanjian Wu

Restaurant: 2nd floor of the hotel

12:00~14:00 Pui-In Mak University of Macau ISSCC and JSSC Writing Hints



8

会议议题 2019.4.12/Afternoon


Keynote Speech Chair: Pui-In Mak


14:00~14:50 Howard Cam

Luong,

Hong Kong University of Science and Technology

Wireless Devices - Recent Development and Future Trends

14:50~15:40 Nan Sun University of

Texas at Austin When SAR meets ΔΣ - A Tail of

Two ADC Architectures

15:40~16:00 Tea Break


Session Five. Wireless and Wireline Chair: Nan Sun


16:00~16:25 Liang Wu

Chinese University of Hong Kong, Shenzhen

A 312GHz Injection-Locked Radiator in 65-nm CMOS

16:25~16:50 Yong Chen University of

Macau

mm-Wave Multi-LC-Tank Oscillators Integrated in Silicon

Technology

16:50~17:15 Dawei Ye Fudan

University

Design of Interferer-Robust RX Link for IoT and Biomedical

Applications

17:15~17:40 Lin Cheng

University of Science and

Technology of China

A 6.78-MHz Single-Stage Wireless Power Receiver Using a 3-Mode

Reconfigurable Resonant Regulating Rectifier

17:40~18:05 Yan Lu University of

Macau Bidirectional (Reverse) Wireless

Charging

18:05~19:00 Farewell &Open Discussions



9

会议议题 Keynote Speakers

The Development and Application of SIMO

Power Management

洪志良，复旦大学

Zhiliang Hong, Fudan University

Abstract: The development of the architecture, control technique and performance achievement of single-inductor multiple-output (SIMO) power management (PM) will be presented in this keynote. Two application examples SIMO in telecommunication with error-based control and in TEG application using fly-back architecture are in detail introduced. Finally, the trend of hybrid architecture SIMO will be addressed. Biograpy: Professor Zhiliang Hong received the B.S. degree from Chinese University of Science and Technology, China, and the Ph.D. degree from the Swiss Federal Institute of Technology (ETHZ), Zurich, Switzerland. He was the leader of the Chinese Delegation in cooperation design with Venus System in TU Berlin in 1987, and an Associate Researcher in Berkeley in 1989. He was a Guest Professor with the University of Hannover, Germany, from 1992 to 1994, and a Guest Researcher at ETHZ in 2000. He is currently a Professor with Fudan University, Shanghai, China. He has authored books Computer Architecture and RISC Design (Fudan Press, 2005) and Analog

Integrated Circuit Analysis and Design (Science Press, 2009，2012). He has authored over 300

technical papers in analog, mixed signal, RF integrated circuits, and system-on-chip. He has supervised 50 PhDs, 150 Masters and 70 Engineering Masters. He serves as the Editor of the Journal of Research and Advance of Solid-State Electronics, the Program Chair of IEEE ASICON in 2005 and 2010, and the ISSCC-TPC member from 2016 to 2019. He is General Co-Chair of International Conference for ASIC (ASICON 2019), in October, 2019, Chongqing



10

会议议题

Vision Chips

吴南健，中科院半导体所

Nanjian Wu, Institute of Semiconductors, Chinese Academy of Sciences

Abstract: The vision chip integrates an imager and brain-inspired parallel-processors on a single Silicon die. It mimics the human visual system in a way that the image sensor and the processors perform functions as the retina and brain visual cortex, respectively. It can perform the high speed image capture and real-time image processing operations. This talk mainly focuses on two kinds of the vision chips: frame-driven (FD) and event-driven (ED) vision chips which are very different from each other in system architecture, image sensing, image information coding, image processing algorithm, design methodology, etc. The FD reconfigurable vision chip comprises a high speed image sensor, a processing element array and self-organizing map neural network. The FD vision chip has the advantages in image resolution, static object detection, time-multiplex image processing, and chip area. The ED vision chip system is based on address-event-representation image sensor and event-driven multi-kernel convolution network. The ED vision chip has the advantages in fast sensing, low communication bandwidth, brain-like processing, and high energy efficiency. Finally, it discusses the architecture and the challenges of the future vision chip and indicates that the reconfigurable vison chip with left- and right-brain functions integrated in the three dimensional (3D) LSI technology becomes a trend of the research on the vision chip. Biograpy: Nanjian WU was born in Zhejiang, China, in 1961. He received the B.S. degree in physics from Heilongjiang University, China, in 1982, the M.S. degree in electronic engineering from Jilin University, China, in 1985, and the D.S. degree in electronic engineering from the University of Electronic Communications, Japan, in 1992. In 1992, he joined the Research Center for Interface Quantum Electronics and the Faculty of Engineering, Hokkaido University, Sapporo, Japan, as a Research Associate. In 1998, he was an Associate Professor with the Department of Electro-Communications, University of Electronic Communications. Since 2000, he has been a Professor with the Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China. His current research interests include mixed-signal largescale integrated design and smart vision chip.



11

会议议题

Gigapixel Camera: From the System to Chip

Level Solution

曾晓洋，复旦大学

Xiaoyang Zeng, Fudan University

Abstract: A gigapixel camera captures images with more than 1 billion pixels in one shot. It finds wide applications in entertainment, security, medical, defense, and the ultra-high-altitude aerial photomapping or monitoring. The development of a gigapixel camera is an interesting but very challenging task for the academia and industry. How to design an effective gigapixel sensor array at reasonable cost, how to handle the computation and communication of massive data generated by gigapixel sensors? In this talk, we will discuss these design challenges and present the solutions to core components in gigapixel camera including: (1) a compact and very efficient optical subsystem with a new concentric composite scale solution; (2) The scalable ultra-massive vision/image mosaicking with a dedicated hardware solution to accelerate the speed of gigapixel scale imaging up to 25fps or more, which is a critical factor for real-time supervisory controlling; (3) The multi-channel and reconfigurable processor for image signal processing, which are critical for the conditions of dark light, high contrast, or haze environment, etc.; and (4) A high performance and energy efficient hardware accelerator with artificial intelligence (AI) algorithm to achieve the in-system target detection subsystem, which is capable of detection and recognition for massive objects such as the face, figure, and other special objects. Several gigapixel images will be shown to illustrate the advantages of gigapixel camera.

Biograpy: Prof. Xiaoyang Zeng received the B.Sc. degree in 1996 from Xiangtan University, and the Ph.D degrees from Chinese Academy of Sciences in 2001. Prof. Zeng has been with Fudan University as a faculty since 2001, where he is currently chair professor and Executing Director of State-Key Laboratory of ASIC and System. He also serves as Chair of the Shanghai Chapter of IEEE SSCS, Co-chair of the Circuit & System Division of Chinese Institute of Electronics, a member of the Steering Committee of ASP-DAC and the A-SSCC technical committee, and TPC Chair of ASICON 2009 and 2013. Recently, Prof. Zeng has received the National Science Fund for Distinguished Young Scholars in 2015, and the award of Distinguished professor of Yangtze River scholar in 2016, also the National Ten-thousand Talents Program as the Science and Technology Innovation Youth Leader. Prof. Zeng also won the award of Top Ten New IT Youth in Shanghai in 2009. And the award of Twilight scholar in Shanghai in 2011. Also, the award of Excellent academic leaders in Shanghai in 2015. Prof. Zeng‟s research fields include information security chips, base-band processing technologies for wireless communication; mixed-signal IC designs and ultra-low power IC Methodology. He has published over 200 papers on such international journals and conferences as IEEE ISSCC, IEEE JSSC, IEEE Trans. On CAS, IEEE Trans. On VLSI, IEEE VLSI Symposia, IEEE CICC, IEEE ESSCIRC, IEEE ASP-DAC, IEEE A-SSCC, etc., and applied for over 120 patents.



12

会议议题

Towards Energy-Autonomous

Bluetooth-Low-Energy Radios for IoT Applications

麦沛然，澳门大学

Pui-In Mak, University of Macau

Abstract: This talk overviews the motivation, challenges and solutions of realizing energy-harvesting Bluetooth Low-Energy (BLE) receiver and transmitter in 28-nm CMOS; both are the key enablers of energy-autonomous IoT devices. They feature a fully-integrated micropower manager to customize the internal supply and bias voltages for both active and sleep modes. Circuitries enabling sub-0.3V operation are introduced for the low-noise amplifier (LNA), voltage-controlled oscillator (VCO), phased-locked loop (PLL) and power amplifier (PA). Solely powered by solar energy, the BLE transmitter exhibits a FSK error of 2.84% and the frequency drift in a 425-µ s data packet is <5 kHz under open-loop modulation.

Biograpy: Pui-In (Elvis) Mak received the Ph.D. degree from University of Macau (UM), Macao, China, in 2006. He is currently Full Professor at UM Faculty of Science and Technology – ECE, and Associate Director (Research) at the UM State Key Laboratory of Analog and Mixed-Signal VLSI. His research interests are on analog and radio-frequency (RF) circuits and systems for wireless and multidisciplinary innovations. He is currently the Associate Editor of IEEE Journal of Solid-State Circuits (‟18-) and IEEE Solid-State Circuits Letters (‟17-). He is/was the TPC Member of A-SSCC (‟13-‟16), ESSCIRC (‟16-‟17) and ISSCC (‟17-‟19). He is/was Distinguished Lecturer of IEEE Circuits and Systems Society (‟14-‟15) and IEEE Solid-State Circuits Society (‟17-‟18). He was inducted as an Overseas Expert of the Chinese Academy of Sciences since 2018. He is a Fellow of the IET and IEEE.



13

会议议题

Wireless Devices - Recent Development and

Future Trends

梁锦和，香港科技大学

Howard Cam Luong, Hong Kong University of Science and Technology

Abstract: Recent advances in CMOS technologies have made it possible and attractive to realize sophisticated but affordable CMOS systems-on-chip for emerging wireless applications, not only for high-data-rate communications and ubiquitous Internet of Things (IoTs) but also for biomedical electronics, including implantables, wearables, and swallowables. In this talk, firstly, the motivations for these emerging wireless applications are reviewed. Secondly, recent development and status are high-lighted. Finally, the future trends together with the remaining challenges will be discussed in detail. Biograpy: Howard Luong received his BS, MS, and PhD degrees in Electrical Engineering and Computer Sciences (EECS) from University of California at Berkeley in 1988, 1990, and 1994, respectively. Since September 1994, he has joined the EEE faculty at the Hong Kong University of Science and Technology where he is currently a professor. In 2014, he was appointed as the MediaTek Endowed Visiting Professor in IC Design at Nanyang Technology University in Singapore. Professor Luong's research interests are in RF and mm-Wave integrated circuits and systems for wireless and medical applications. He was a co-author of the three technical books entitled

“Design Techniques for Transformer-Based VCOs and Frequency Dividers”, "Low-Voltage RF

CMOS Frequency Synthesizers", and "Design of Low-Voltage CMOS Switched-Opamp Switched-Capacitor Systems". Professor Luong is an IEEE Fellow. He is currently serving as a technical program committee member of IEEE International Solid-State Circuits Conference (ISSCC) and an Associate Editor of both IEEE Solid-State Circuits Letter (SSCL) and IEEE Virtual Journal on RFIC (VJ-RFIC). He was also an IEEE Solid-State Circuits Society Distinguished Lecturer from 2012 to 2014.



14

会议议题

When SAR meets ΔΣ - A Tail of Two ADC

Architectures

孙楠，德州大学奥斯汀分校

Nan Sun, University of Texas at Austin

Abstract: SAR is widely used for medium resolution applications due to its simplicity, scaling compatibility, and low-power consumption. However, its power efficiency degrades as the resolution increases due to its tight requirement on the comparator noise and the exponentially growing capacitor DAC array. By contrast, ADC is a popular architecture for high-resolution applications. Taking advantage of noise shaping, it can achieve high resolution with a low-resolution quantizer and DAC. However, it typically requires the use of op-amps that are power hungry and scaling unfriendly. This talk will present latest hybrid ADCs that aim to combine the merits of SAR and while simultaneously obviating their drawbacks. After providing a high-level review of published works, this talk will take a deep dive into two interesting noise-shaping SAR ADC architectures. The first one uses fully passive switched-capacitor filter to achieve 2nd-order noise shaping. It is fully dynamic and can be easily duty cycled. In addition, it is robust and calibration free. Thus, it is well suited for low-power sensor applications. The second one adopts an error-feedback structure, which simplifies the filter design. It consumes very low power by using a dynamic amplifier and address its process, voltage, and temperature (PVT) sensitivity via a fast-convergence background calibration loop. Biograpy: Nan Sun is Associate Professor at the University of Texas at Austin. He received the B.S. degree from Tsinghua University, China in 2006, where he ranked top in Department of Electronic Engineering. He received the Ph.D. degree from Harvard University in 2010. Dr. Sun received the NSF Career Award in 2013 and Jack Kilby Research Award from UT Austin in both 2015 and 2016. He holds the AMD Endowed Development Chair from 2013 to 2017. He serves in the TPC of IEEE Custom Integrated Circuits Conference and Asian Solid-State Circuit Conference. He is Associate Editor for IEEE Transactions on Circuits and Systems – I: Regular Papers since 2016, and Guest Editor for IEEE Journal of Solid-State Circuits since 2018. He also serves as IEEE Circuits-and-Systems Society Distinguished Lecturer from 2019 to 2020.



15

会议议题 Regular Speakers

Session 1: Analog and Mixed-Signal

Novel Security Chip Implementation with RRAM sing Intrinsic Randomness Source

吴华强，清华大学

Huaqiang Wu, Tsinghua University

Abstract: Physical Unclonable function (PUF) has been increasingly used as a promising primitive for hardware security with the wide applications in Internet of Things (IoT), such as authentication and encryption key generation. A reconfigurable 8Kb RRAM PUF macro is presented using (1) resistance differential comparison between two RRAM arrays for reliable PUF key generation; (2) RRAM‟s post-process randomness for robust reconfigurability; and (3) split resistance technique for low nature BER. For the first time, a reconfigurable PUF is presented with 47.29% reconfigure-Hamming distance. This work also achieved below 6E-6 BER and 49.99% Inter-HD, and low power consumption (~3.028pJ/bit). Biograpy: Prof. Wu is presently the deputy director of the Institute of Microelectronics, Tsinghua University and also served as the deputy director of Beijing Innovation Center for Future Chips. Dr. Wu received his Ph.D. degree in electrical and computer engineering from Cornell University, Ithaca, NY, in 2005. Prior to that, he graduated from Tsinghua University, Beijing, China, in 2000 with double B.S. degrees in material science & engineering and enterprise management. From 2006 to 2008, he was a senior engineer and MTS in Spansion LLC, Sunnyvale, CA. He joined the Institute of Microelectronics, Tsinghua University in 2009. His research interests include emerging memory and neuromorphic computing technologies. Dr. Wu has published more than 100 technical papers in Nature Electronics, Nature Communications, Advanced Materials, IEDM, ISSCC, VLSI, etc..



16

会议议题

The Design of High Linearity Multi-bit

Continuous-Time Sigma-Delta Modulator

冼世荣，澳门大学

Sai-Weng Sin, University of Macau

Abstract: Aggressive CMOS technology scaling has been driving the design of Continuous-Time Sigma-Delta Modulators (CTSDM) into a new wideband high-resolution era with smaller area and power consumption, with unavoidable degraded component matching in such a small area. Multi-bit quantization is an effective way to increase the resolution in the sigma-delta ADC, while the mismatch-induced DAC nonlinearity always limited the achieved SNDR and SFDR. The DAC nonlinearity is traditionally alleviated by Dynamic Element Matching (DEM) or DAC Calibrations, which impose power, area and the delay penalty. In this talk, a cascaded CTSDM with 1.5b and 4b quantizers in 1st and 2nd stages will be discussed. It renders a 4th-order 1.5b 1st stage effectively into an overall 4th-order 4b DSM. The noise coupling whitens the 1.5b quantization noise, while an FIR DAC reduces its out-of-band power. Together, this avoids any DAC calibration or DEM technique. Sampled at 1.2GHz, the 28nm CMOS prototype measures a 76.6dB SNDR and 87.9dB SFDR over a 50MHz BW. It achieves a Schreier FOM of 168.9dB and consumes 0.085 mm2 area. Biograpy: Sai-Weng Sin (Terry) is currently an Associate Professor with the Dept. of ECE, Faculty of Science and Technology and the Deputy Director (Academic) of the Institute of Microelectronics, as well as the Academic Coordinator of State-Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau. He has published 1 book entitled “Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters” in Springer, hold 7 US patents and 100 technical journals and conference papers in the field of high-performance data converters and analog mixed-signal integrated circuits. Dr. Sin is the member of the Technical Program Committee of 2013-2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), and the Local Organization Committee for 2019 IEEE A-SSCC. He was the Secretary of IEEE Solid-State Circuit Society (SSCS) Macau Chapter with 2012 IEEE SSCS Outstanding Chapter Award, and IEEE Macau CAS/COM Joint Chapter with 2009 IEEE CAS Chapter of the Year Award. He co-supervised the Ph.D student that got the 2015 SSCS Pre-Doctoral Achievement Award. He was the co-recipient of the 2011 ISSCC Silk Road Award, Student Design Contest Award in A-SSCC 2011 and the 2011 State Science and Technology Progress Award (second-class), China.



17

会议议题

Low-Voltage ADCs: Inverter-Based and

Time-Based Approaches

李强, 电子科技大学

Qiang Li, University of Electronic Science and Technology of China

Abstract: Ultra-low voltage ADCs are discussed with circuit-level approaches using inverter-based amplifiers and system-level approaches incorporating time-based comparison. An evolution process of implementing conventional structures with inverters is introduced, allowing ultra-low voltage operation with increased flexibility in adopting traditional circuit techniques. The number of oscillation cycles to reach a VCO-comparator decision is investigated, which is found an inherent coarse quantization in parallel with the normal comparison, and can be exploited for higher power efficiency and PVT robustness of VCO-based SAR ADCs. Biograpy: Qiang Li received the B.Eng. from the Huazhong University of Science and Technology (HUST), Wuhan, China and the Ph.D. from the Nanyang Technological University (NTU), Singapore, in 2001 and 2007, respectively. He is currently a full Professor at the University of Electronic Science and Technology of China (UESTC), heading the Institute of Integrated Circuits and Systems. Dr. Li was a recipient of the Young Changjiang Scholar award in 2015. He serves on the SRP committee of ISSCC, TPC of ESSCIRC and ASSCC.



18

会议议题

More than Figure-of-Merit ADC Design

Perspective

陈知行，澳门大学

Chi-Hang Chan, University of Macau

Abstract: In the pass few decays, ADC researchers have spent numerous efforts to push the energy efficiency toward the fundamental boundary based on Hartley-Shannon law. On the other hand, when looking at the ADC designs nowadays, it can be recognized that they already optimized enough where even 2x or 4x lower power does not make much difference in the system point of view. On the other hand, such low power designs often leave the burden to the peripheral circuits which eventually leads to diminish-returned. In this talk, several design examples and practical issues will be first overviewed, then followed by solutions and research possibility discussions. Biograpy: Chi-Hang Chan was born in Macau S.A.R., China, in 1985. He received the B.S. degree in electrical engineering from University of Washington (U.W. Seattle), USA, in 2008, and the M.S. degree and Ph.D. from the University of Macau, Macao, China, in 2012 and 2015, respectively. He currently serves as assistant professor at SKL-AMSV at University of Macau, Macao and Secretary of IEEE Solid State Macau Chapter. He received the Chipidea Microelectronics Prize and Macau Science and Technology Development Fund (FDCT) Postgraduates Award during his Master and PhD study. He has also received Macau FDCT Award for Technological Invention in 2014, 2016 and 2018 for his outstanding academic and research achievements in microelectronics. He is the recipient of the 2015 Solid-State-Circuit-Society (SSCS) Pre-doctoral Achievement Award and co-recipient of ESSCIRC 2014 best paper award. He has authored and co-authored 9 Journal Solid State Circuit (JSSC) and 7 International Solid State Circuit Conference (ISSCC) papers in the data converter and clock circuit design field. His research interests include high speed Nyquist, noise shaping ADCs and low jitter clock circuits.



19

会议议题 Session Two. Power Management

An 800-mW Fully Integrated Galvanic Isolated Power Transfer System Meeting CISPR 22 Class B Emission Levels with 6dB Margin

秦文辉，亚德诺半导体（上海）

Wenhui Qin, Analog Devices, Shanghai

Abstract: Employing galvanic isolation in the industrial field transceivers is an essential requisite to guarantee safety and better reliability. Delivering >500mW output power while suppressing excessive emissions present challenges for a fully-integrated isolated solution. In this work, an 800-mW isolated power transfer system is implemented using on-chip coreless transformer. Various circuit techniques reduce emissions to meet EMI standard CISPR 22 Class B with 6dB margin. Biograpy: Wenhui Qin received the B.S. degree in micro-electronics from University of Electronic Science and Technology of China, Chengdu, China, in 2013. Then in 2016, he received the M.S. degree in micro-electronics from Fudan University, Shanghai, China. He has been joining the ISO team in ADI and taking part in the design of the low-EMI isoPower products and isolated amplifier for about 3 years, now he has 4 US Patents about analog circuit.



20

会议议题

A 52% Peak-Efficiency >1W Isolated Power

Transfer System Using Fully Integrated Magnetic-Core Transformer

卓越，亚德诺半导体（北京）

Yue Zhuo, Analog Devices, Beijing

Abstract: This work presents an isolated power transfer system using fully-integrated transformer with magnetic core. A full-bridge LLC topology is adopted, and a fully-symmetric power stage is utilized to minimize the radiated emissions. A multi-mode control approach combining PWM control and frequency control enables optimal efficiency and >1W output power. The isolated power transfer system in a single package achieves peak efficiency of 52%, output power of 1.1W and passes CISPR 22 EMI limit by 5.8dB. Biograpy: The author is a design engineer from ADI ISO Group, based in Beijing, China. He focuses on IsoPower® converter design. The author joined ADI in Mar. 2015. He received B.S. degree in EE from NanKai University in 2006 and M.S. degree in Microelectronics from the institute of microelectronic, Naikai University in 2009. Before ADI He had worked as an analog designer in PMP field for more than 6 years



21

会议议题

Overview on the Design Trends of Digital Low

Dropout Regulators

黄沫，华南理工大学

Mo Huang, South China University of Technology

Abstract: Digital Low Drop-out Regulator (D-LDO) has recently drawn significant attention due to its process scalability and low-supply-voltage application. This talk firstly overviews the motivation and design targets of D-LDO. Then, the design strategies are comprehensively presented in circuit level, aiming at a high transient speed, reduced power consumption, low limit cycle oscillation (LCO), and high power supply rejection (PSR), respectively. Finally, a D-LDO design guideline is drawn. Biograpy: Mo Huang received the B. Sc., M. Sc., and Ph. D degree in microelectronics and solid-state electronics from Sun Yat-sen University, Guangzhou, China, in 2005, 2008, and 2014, respectively. From 2008 to 2014, he was an IC design engineer and a project manager with Rising Microelectronics, Guangzhou, China. He was a research associate with Nanyang Technological University, Singapore, in 2014. From 2015 to 2016, he was a postdoctoral fellow with the State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China. In October 2016, he joined the school of Electronic and Information Engineering, South China University of Technology, Guangzhou, China, as an associate professor. His current research interests include analog and mixed-signal IC design, power management IC design and wireless power transfer. He holds 17 patents. Dr. Huang is the founding secretary of the IEEE Solid State Circuits Society Guangzhou Chapter. He was a recipient of the IEEE ISSCC 2017 Takuo Sugano Award for Outstanding Far-East Paper and the IEEE TENCON 2015 Professional Award. He served as a Technical Program Committee Member of the IEEE APCCAS 2018, ICTA 2018 and ASICON 2017 and a reviewer for many journals/conferences.



22

会议议题

AC Input Inductor-Less LED Driver for Efficient

and Smart Lighting

高源，香港科技大学

Yuan Gao, Hong Kong University of Science and Technology

Abstract: Light-emitting diodes (LEDs), as an emerging lighting source with a combination of low energy consumption, long lifetime and improved physical robustness, are edging out the conventional incandescent and fluorescent lights. In addition to providing efficient illumination, LEDs can be powered up immediately and can be switched on and off frequently without affecting their lifetime. In this talk, an AC-powered inductor-less light LED driver will be introduced. It can simultaneously provide efficient illumination and data transmission capability by modulating light output. The proposed driver does not have passive components speed limitation compared to the conventional switching converter based driving solutions for visible light communication (VLC). Besides this, harmful low-frequency flicker is mitigated with an accurate 1/x circuit and the dimming compensation method. In addition, the digitalized power stage and controller utilized in the proposed driver can achieve smooth transitions among multiple current paths, while the keep-and-restore technique and auxiliary turn-on switch help to further increase the VLC data rate. Biograpy: Dr. Yuan GAO received the B.Eng. and M.Eng. degrees from Xi‟an Jiaotong University, China, in 2009 and 2012, respectively, and the Ph.D. degree from the Hong Kong University of Science and Technology (HKUST), Hong Kong, China in 2017. He is currently working as a Post-Doctoral Fellow with HKUST. His research interests include high voltage integrated circuit design for LED lighting, Gallium Nitride driving and wireless power transfer systems. He has authored/coauthored 20 journal and conference papers, including JSSC, ISSCC and VLSIC.



23

会议议题 Session 3: Wireless and Wireline

Circuit Techniques for CMOS Mm-Wave Radar

Transceivers

池保勇，清华大学

Baoyong Chi, Tsinghua University

Abstract: The demand for driving safety grows rapidly in modern society. The automotive radar plays an important role in avoiding traffic accidents. Different sensing technologies based on laser, infrared, ultrasonic and millimeter-wave (mm-wave) have been proposed for automotive radars. Among those technologies, mm-wave attracts much attention due to its superior robustness against various environments, such as extreme temperature, rain, frog or snow. The operation frequency of mm-wave automotive radars mainly locates at frequencies near 24 GHz or 77 GHz. Recently, there is a tendency to move from 24 GHz to 77 GHz due to smaller wavelength, smaller antenna size and therefore more compact size at 77 GHz. Along with its rapid development, CMOS process has become promising for low cost mm-wave automotive radar chips, even though great challenges still exist. This talk mainly focuses on the challenges on the circuit implementation of CMOS mm-wave radar transceivers. Biograpy: Baoyong Chi (M'05, SM'18) received the B.S. degree in microelectronics from Peking University, Beijing, China, in 1998, and the Ph.D. degree from Tsinghua University, Beijing, in 2003. From 2006 to 2007, he was a Visiting Assistant Professor with Stanford University, Stanford, CA, USA. He is currently a full Professor and Deputy Director with the Institute of Microelectronics, Tsinghua University. He has authored over 180 academic papers and two books. He holds more than 20 patents. His current research interests include RF/millimeter-wave integrated circuit design, analog integrated circuit design, and monolithic wireless transceiver chips for radar and communication. He has won the Distinguished Design Award in A-SSCC 2018. He was selected as China National Funds for Outstanding Youth Scientists in 2012 and Chang Jiang Scholars Program-Chang Jiang Youth Scholars in 2015. Dr. Chi has been a TPC Member of A-SSCC since 2005 and Editor Board Member of Science China information Sciences Since 2016 .



24

会议议题

Energy-Efficient and Area-Saving Techniques in Digital Power Amplifiers

徐鸿涛，复旦大学

Hongtao Xu, Fudan University

Abstract: In this presentation, a few energy-efficient and area-saving techniques in digital power amplifier are presented. With a fusion of highly reconfigurable switched-mode amplifier and power combiner architectures, die size and efficiency can be improved simultaneously. Biograpy: Prof. Hongtao Xu received the M.A. in economics in 2003 and Ph.D. degrees in electrical and computer engineering in 2005, both from the University of California at Santa Barbara (UCSB). Since 2005, he has been with Intel Labs, Hillsboro, Oregon. In 2015, he joined Fudan University as a professor in School of Microelectronics. His technical interests include RFICs and system in advanced CMOS, ultra-low power SoC and high-performance mm-wave circuits. He has published more than 50 journal and conference papers, 2 book chapter and 15 patents. He currently serves as TPC and steering member for IEEE RFIC conference.



25

会议议题

Waveform-Shaping CMOS VCO for Wireless

Communication

殷俊，澳门大学

Jun Yin, University of Macau

Abstract: A low-phase-noise VCO is highly demanded in the emerging wireless communication systems that support sophisticated modulation scheme for high data-rate such as 5G cellular and WiFi 802.11ac/ax standards. This presentation discusses the performance limitation of a traditional class-B VCO regarding its phase noise, power efficiency, and supply pushing at first. Then various emergent low-phase-noise CMOS oscillator architectures that employ the waveform shaping techniques, e.g., common-mode resonance, and inverse Class-F will be analyzed and compared to show how these architectures are evolved, and their performance is improved step by step. Biograpy: Jun Yin received the B.Sc. and the M.Sc. degrees in Microelectronics from Peking University, Beijing, China, in 2004 and 2007, respectively, and the Ph.D. degree in Electronic and Computer Engineering (ECE) from Hong Kong University of Science and Technology (HKUST), Hong Kong, China, in 2013. He is currently an Assistant Professor at the State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau (UM), Macao, China. His current research interests include the analog/digital PLL and integrated oscillator for wireless communication and sensing systems. Dr. Yin has co-authored more than 30 peer-reviewed papers including 10 papers in IEEE Journal of Solid-State Circuits (JSSC) and 6 papers in IEEE International Solid-State Circuit Conference (ISSCC). He is also the associate editor of the Integration, the VLSI journal. .



26

会议议题

Wideband CMOS mm-Wave Circuits Design for

5G Communications

康凯，电子科技大学

Kai Kang, University of Electronic Science and Technology of China

Abstract: Since mm-wave frequency bands are adopted in 5G communications, CMOS mm-wave circuits and systems attract tremendous attentions because of its low cost and high integration capability. However, circuits designers have to face to many challenges of CMOS process, such as the high loss substrate, low Q passive devices, high noise, and limited gain and output power. This paper will introduce technique to overcome these difficulties to design high performance wideband building blocks as well as transceiver chipsets for 5G communication. Biograpy: Kai Kang (M‟08) received the B. Eng degree from the Northwestern Polytechnical University, China in 2002, and the joint Ph.D. degree from the National University of Singapore, Singapore and Ecole Supérieure D‟électricité, France in 2008. From 2006 to 2011, he was successively with the Institute of microelectronics, A*STAR, Singapore as a Senior Research Engineer, with National University of Singapore as an adjunct assistant professor and with Global foundries as a Principle Engineer, respectively. Since June 2011, he has been a professor at the University of Electronic Science and Technology of China. His research interests are RF and RF & mm-Wave integrated circuits design and modeling of on-chip devices. Dr. Kang serves as the chapter chair of IEEE Solid State Circuits Society Chengdu Chapter. He was co-recipient of several best paper awards or best student paper awards in IEEE conference including Silkroad award in ISSCC 2018. He has authored and co-authored over 150 international referred journal and conference papers.



27

会议议题 Session 4: Digital and Emerging Directions

Embedding AI in Everything: High Energy

Efficient Neural Network Processor Design

尹首一，清华大学

Shouyi Yin, Tsinghua University

Abstract: Deep neural networks (DNNs) have achieved great success in many applications of artificial intelligence (AI). To enable always-on and pervasive AI applications in mobile and IoT devices, ultra-low power neural network processors are required. With the progresses of both neural network algorithms and computing architectures, it is possible to design μW-level neural network processors. In this talk, we introduce Thinker processors which have the potential to embed AI in everything. Biograpy: Dr. Shouyi Yin is associate professor (Tenured) and vice director of Institute of Microelectronics in Tsinghua University. His research interests include reconfigurable computing, domain-specific reconfigurable architecture design and high level synthesis. He has published more than 100 journal papers and more than 50 conference papers. He has received Second Prize of China‟s State Technological Innovation Award (2015), China‟s Patent Golden Award (2015), First Prize of Technological Innovation Award of Ministry of Education, China (2014), Second Prize of Science and Technology Advancement Award of Jiangxi Province, China (2014) and Best Paper Award in China Communications IC Technology and Application Conference (2011). Dr. Shouyi Yin is the Secretary-General of EDA Chapter in Chinese Institute of Electronics. He is also the technical committee member of Asia Pacific Signal and Information Processing Association. Dr. Shouyi Yin has been served as program committee member and organizer in the tops VLSI and EDA conferences such as A-SSCC, DAC, ICCAD and ASPDAC. He is the associate editor of Integration, the VLSI journal and editorial board member of Journal of Low Power Electronics.



28

会议议题

Intelligent and low power integrated circuits for

Bio- applications

王国兴，上海交通大学

Guoxing Wang, Shanghai Jiao Tong University

Abstract: Integrated electronics have been improving the quality of life for the human beings over decades. With the advancement of many emerging technologies, especially artificial intelligence, this trend will keep going, and maybe even in a faster pace. As a result, the interface circuits between electronics and human beings is becoming more and more complicated. In particular, sensing physiological signals of human body is pivotal in biomedical applications. In this talk, I will review some of the past achievements and on-going work on low power and intelligent integrated circuits design towards fully autonomous wireless sensor networks, including our work of an electrical impedance tomography SoC which was presented in ISSCC2019. The chip used several techniques including borrowing the concept of frequency division multiplexing from communication and early demodulation, achieving the lowest power to date, about 1/10 of the best reported results. Biograpy: Guoxing Wang received his Ph.D. degree in electrical engineering from University of California at Santa Cruz, US, in 2006. Currently, he holds a Professorship in School of Microelectronics, Shanghai Jiao Tong University, Shanghai, China and serves the vice head for the School of Microeletronics. He heads the research group of Bio- Circuits and Systems Lab (www.bicasl.org) whose research interests include biomedical electronics, artificial intelligence, human machine interactions. Dr. Wang is a senior member of IEEE, and a member of the IEEE Biomedical Circuits Systems Technical Committee (BioCAS). Currently he serves as the Deputy Editor-in-Chief for IEEE Transactions on Biomedical Circuits and Systems and Vice President for IEEE Circuits and Systems Society.



29

会议议题

Leveraging Varying Sparsity in Energy Efficient

Neural Network Accelerator Design

刘勇攀，清华大学

Yongpan Liu, Tsinghua University

Abstract: Neural Networks (NNs) have emerged as a fundamental technology for machine learning. The sparsity of weight and activation in NNs varies widely from 5%-90% and can potentially lower computation requirements. However, existing designs lack a universal solution to efficiently handle different sparsity in various layers and neural networks. This work, named STICKER, first systematically explores NN sparsity for inference and online tuning operations. This talk will first discuss the overview of neural network processors supporting sparsity. After that, the new design consisting of three major contributions is illustrated: 1) Autonomous NN sparsity detector that switches the processor modes; 2) Multi-sparsity compatible Convolution (CONV) PE arrays that contain a multi-mode memory supporting different sparsity, and the set-associative PEs supporting both dense and sparse operations and reducing 92% memory area compared with previous hash memory banks; 3) Online tuning PE for sparse FCs that achieves 32.5x speedup compared with conventional CPU, using quantization center-based weight updating and Compressed Sparse Column (CSC) based back propagations. Peak energy efficiency of the 65nm STICKER chip is up to 62.1 TOPS/W at 8bit data length. Finally, some open problems are given out for future research.

Biograpy: 刘勇攀，博士，清华大学电子工程系长聘副教授，电路与系统研究所所长，

IEEE 高级会员，清华-罗姆研究中心和未来芯片研究中心核心成员。研究兴趣主要

包括高能效人工智能芯片、非易失计算和大面积传感系统等。在 ISSCC、VLSI Sym、

JSSC、ACM/IEEE Trans.发表了 120 多篇论文，包括世界首款非易失处理器芯片

THU10XX 系列和高能效人工智能芯片 STICKER 系列。2017 年入选国际电子设计自

动化领域40岁以下发明创新奖，ASP-DAC 2017最佳论文，IEEE Micro Top Pick 2016，

HPCA2015 最佳论文以及 ISLPED2012-2013 设计竞赛奖等。担任 IEEE Trans. CAD、

CAS2 和 IET Cyber-physical 理论和应用杂志的编委，以及 DAC、ASP-DAC、ISLPED、

A-SSCC、ICCD、VLSI-D、VLSI-DAT 等国际会议的技术委员会委员。担任 NVMSA19

技术委员会主席、IWCR18 大会主席、ICCD15、ESWEEK15 以及 ASSCC15 的会议

联合主席，是亚洲智能传感器系统研讨会 AWSSS 的创始人；2018 年通过技术转移

创立湃方科技公司, 获顶级风投主攻工业智能物联网芯片及应用系统。



30

会议议题

Circuits Advances for Edge Intelligence in Iot

Applications

邹卓，复旦大学

Zhuo Zou, Fudan University

Abstract: In recent years, Artificial Intelligence (AI) has been widely deployed in a variety of business sectors and industries, yielding numbers of revolutionary applications and services that are primarily driven by high-performance computation and storage facilities in the cloud. On the other hand, embedding intelligence into edge devices is highly demanded by other emerging applications such as autonomous systems, human-machine interactions, and the Internet of Things (IoT). In these applications, it is advantageous to process the data near or at the sensor interface for improved energy and spectrum efficiency and decreased latency. However, it remains challenging to perform sophisticated intelligent algorithms in these resource-constrained edge devices, which not only calls for not only circuits advances, but also for innovative architectures for energy-efficient information processing, as well as for architecture-circuit co-design. Time-based signal processing that encodes the signal information in time instead of conventional voltage/amplitude representations, has received increasing attention in recent years. It exhibits several advantages in hardware implementations, including benefitting from increased time resolution and high resilience to PVT variations in deeply-scaled CMOS processes, and low-area and power-efficient analog and mixed-signal processing due to the mostly-digital design. In this talk, we will review our recent work on smart sensor-to-cloud interconnection for IoT applications. A time-domain interface, incorporating an ultra-low power impulse radio ultra-wideband (IR-UWB) is employed. The analog signal from the sensor is compared with a triangular waveform, resulting in a pulse-position modulation signal to trigger spiking pulses. Thanks to the high time-resolution IR-UWB radio, time intervals of the impulses can be used to represent the original input value, which is measured remotely by a time-of-arrival estimator. Such a sensor-radio interconnection co-design approach not only eliminates the analog-to-digital converter (ADC) but also significantly reduces the number of bits to be transmitted for power saving. In addition, a brief discussion on embedding artificial intelligence into such a time-domain system exploiting time-domain deep neural networks will be provided. Biograpy: Zhuo Zou received the Ph.D. degree in Electronic and Computer Systems from KTH Royal Institute of Technology, Sweden, in 2012. Currently, he is with Fudan University Shanghai as a professor, where he is conducting research on integrated circuits and systems for IoT and ubiquitous intelligence. Prior to Fudan, he was the assistant director and a project leader at VINN iPack Excellence Center, KTH, Sweden, where he coordinated the research project on ultra-low-power embedded electronics for wireless sensing. Dr. Zou has also been an adjunct professor and docent at University of Turku, Finland, and is a senior member of IEEE.



31

会议议题 Session 5: Wireless and Wireline

A 312GHz Injection-Locked Radiator in 65-nm

CMOS

吴亮，香港中文大学（深圳）

Huaqiang Wu, Tsinghua University

Abstract: As one of the least tapped regions in electromagnetic spectrum, the terahertz (THz) band from 0.3 THz to 3 THz is gaining increasing research interest due to the numerous potential applications uniquely enabled by such short wavelengths including imaging, spectroscopy and high-speed wireless communications. In reality, a technology vacuum known as “terahertz gap” exists, inducing major challenges in implementing radiation sources with sufficient output power. This talk will present an injected-locked THz radiator integrating a half-quadrature VCO, four injection-locked frequency quadruplers, and a chip-and-package distributed antenna. At the system level, an architecture based on injection-locking is employed to allow individual optimization of the output power and the phase noise. At the circuit level, intrinsic-delay compensation and harmonic boosting techniques are proposed to optimize the phase noise of the HQVCO and the output power of the ILFQs, respectively. The proposed distributed antenna composed of four exciting elements on silicon chip and a primary radiator in LTCC package features a wide bandwidth of 13% and a gain of 3.8 dBi without using lens at 312 GHz. Implemented in a 65-nm CMOS process, the radiator achieves output frequency around 312GHz and maximum EIRP of 10.5 dBm while consuming 300 mW. The output phase noise measures –109.3 dBc/Hz at 10-MHz offset and the DC-to-THz efficiency is 0.42%. Biograpy: Dr. Liang Wu received the B.S. and M.S. degrees in materials science from Fudan University, China, in 2004 and 2007 respectively, and the Ph.D. degree in electronic and computer engineering from the Hong Kong University of Science and Technology in 2012. Currently he is an Assistant Professor in the School of Science and Engineering (SSE), Chinese University of Hong Kong, Shenzhen. His research interests include radio-frequency, millimeter-wave and terahertz CMOS integrated circuits and optical-and-wireless convergence systems for 5G and Internet-of-Everything applications.



32

会议议题

mm-Wave Multi-LC-Tank Oscillators Integrated

in Silicon Technology

陈勇，澳门大学

Yong Chen, University of Macau

Abstract: This tutorial briefs the latest evolution of the implicit and explicit harmonic oscillator in CMOS technology. We will show the challenges of the voltage-controlled oscillator (VCO) design from radio frequency to mm-wave band, and detail how to effectively combine the high-order harmonics in the multi-LC-tank VCOs to achieve better figure of merit and lower flicker noise corner. Two mm-wave VCOs prototyped in CMOS technology are illustrated. Finally, the state-of-the-art of the mm-wave VCO design is summarized and its tendency will be introduced as well. Biograpy: Yong Chen (S‟10-M‟11) received the B.Eng. degree in electronic and information engineering, Communication University of China (CUC), Beijing, China, in 2005, and the Ph.D. in Engineering degree in microelectronics and solid- state electronics, Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), Beijing, China, in 2010. From 2010 to 2013, He worked as Post-Doctoral Researcher in Institute of Microelectronics, Tsinghua University, Beijing, China. From 2013 to 2016, he was Research Fellow in VIRTUS/EEE, Nanyang Technological University, Singapore. Since March 2016, he is an Assistant Professor of the State Key Laboratory of Analog and Mixed-Signal VLSI (AMSV) of University of Macau, Macao, China. Dr. Chen focuses on IC design involving analog/RF/mm-wave/wireline, and reports 2 chip inventions at the 2019 IEEE International Solid-State Circuits Conference - ISSCC (Chip Olympics): mm-wave PLL („19) and VCO („19).



33

会议议题

Design of Interferer-Robust RX Link for IoT and

Biomedical Applications

叶大蔚，复旦大学

Dawei Ye, Fudan University

Abstract: With the fast growth of internet-of-things (IoT), the dilemma between usable frequency bands and deployment of massive wireless sensor nodes make a challenge to design an interferer-robust wireless link. This problem becomes even worse when the corresponding RX has very low power budget. To address this issue, we propose a 65nm CMOS 2.4GHz interferer-robust receiver using a novel technique to power-efficiently reject the interferer in the amplitude domain. Compared to the traditional frequency or phase filters, our amplitude filter has the smallest consuming power and die area and thus is suitable for the design of interferer-robust wireless systems which have limited power budget and system size. On the other hand, as a simplified case, the concept of amplitude filtering is successfully applied to a 65nm CMOS 13.56MHz wireless power and data transfer receiver, which achieves excellent effective power conversion efficiency when receiving the power and data simultaneously. Biograpy: Mr. Ye received the B.Sc. degree in optoelectronics from the Huazhong University of Science and Technology, Wuhan, China, in 2008, and the M.Sc degree in electrical engineering from Lund University, Lund, Sweden, in 2012. Since 2016 he has been a research associate in the Brain Chip Research Center (BCRC) at Fudan University. During 2012-2016, he has been a research assistant in the IC Design Group, University of Twente, The Netherlands. His current research interests include interferer-robust ultralow power transceiver, phase-lock loop (PLL), wireless power harvesting and RF front-ends.



34

会议议题

A 6.78-MHz Single-Stage Wireless Power Receiver Using a 3-Mode Reconfigurable

Resonant Regulating Rectifier

程林，中国科学技术大学

Lin Cheng, University of Science and Technology of China

Abstract: A 3-mode 1X/½ X/0X reconfigurable resonant regulating (R3) rectifier for wireless power receiver is proposed. The rectifier improves power conversion efficiency and reduces die area and off-chip components by achieving power conversion and voltage regulation in one stage, using only 4 on-chip power switches and 1 off-chip capacitor. The receiver regulates the output voltage at 5V and delivers a maximum power of 6W. It was designed in a standard 0.35µ m CMOS process with a die area of 4.77mm2, and the measured peak efficiency reaches 92.2%. Biograpy: Dr. Lin CHENG, received his B.Eng degree from Hefei University of Technology, M.S. degree from Fudan University, and Ph.D. degree from The Hong Kong University of Science and Technology (HKUST), in 2008, 2011 and 2016, respectively. He was a Postdoctoral Research Associate at HKUST from 2016 to 2018. He is currently a Professor with the School of Microelectronic, University of Science and Technology of China. His research interests include power management circuits and systems, wireless power transfer circuits and systems, switched-inductor power converters, and automotive ICs. Dr. Cheng is a recipient of the IEEE Solid-State Circuits Society Pre-Doctoral Achievement Award 2014-2015 and HKIS Young Scientist Award (Honorable Mention) 2018.



35

会议议题

Bidirectional (Reverse) Wireless Charging

路延，澳门大学

Yan Lu, University of Macau

Abstract: Bidirectional (reverse) wireless charging has been adopted recently by major mobile phone makers like Huawei and Samsung. In this talk, two reconfigurable wireless power transceivers, which reuse almost all of the hardware, will be briefly discussed. In particular, a novel cross-connected structure for the differential class-D power amplifier in the transmitter mode is proposed for reducing the switching losses. Fabricated in 0.35µ m standard CMOS process with 5V devices, over 78% battery-to-battery charging total efficiency and over 0.6A wireless charging current are demonstrated with two identical transceiver chips with printed coupling coils on board. Biograpy: Yan Lu received the PhD degree in Electronic and Computer Engineering from the Hong Kong University of Science and Technology (HKUST), Hong Kong, in 2013. Then, he joined the State Key Laboratory of Analog and Mixed-Signal VLSI of University of Macau as an Assistant Professor, in 2014. His research interests include wireless power transfer, fully-integrated voltage regulators From 2013 to present, Yan has contributed 9 ISSCC papers all in the power management IC area, including 3 as the first author and 5 as the principle investigator. In addition, Yan has authored/co-authored 30 SCI (mostly IEEE) journal papers, and filed two US patents. Dr. Lu also co-authored two books and three book chapters. Yan was a recipient/co-recipient of the 2018 Macao Science and Technology Award (2nd prize, with the 1st prize vacancy), the IEEE Solid-State Circuits Society Pre-doctoral Achievement Award 2013-2014, the IEEE CAS Society Outstanding Young Author Award 2017, and the ISSCC 2017 Takuo Sugano Award for Outstanding Far-East Paper. He is serving as the TPC member of CICC 2019, and the ITPC member of ISSCC 2020.



36

会议议题 Committee

Honorary Co-Chairs Zhihua Wang, Tsinghua University 王志华，清华大学 Rui P. Martins, University of Macau

马许愿，澳门大学

Conference Co-Chairs Qiang Li, University of Electronic Science and Technology of China

李强，电子科技大学 Pui-In Mak, University of Macau

麦沛然，澳门大学

Technical Program Co-Chairs Yan Lu, University of Macau

路延，澳门大学 Nan Sun, University of Taxes at Austin

孙楠，德州大学奥斯汀分校 Dixian Zhao, Southeast University

赵涤燹，东南大学



37

会议议题 Venue

Address: Xinian Square, 216 Xiadong Street, Jinjiang district, Chengdu, China

酒店地址：四川省成都市锦江区下东大街 216 号喜年

广场

Registration Desk: Registration desk is on the 2nd floor of Rhombus Park Aura Chengdu Hotel

会议注册在酒店二楼

Meeting Room: Meeting Room(4+5) is on the 4th floor of the Hotel

会议地点：4 楼 4+5 号厅

Restaurant information: Shunxing Tea House is next door to the Chengdu Century City International Conference Center Banquet Venue: 2+3 meeting room (The 4th floor of the hotel)

10 号晚餐：顺兴老茶馆（成都市武侯区世纪城国际

会展中心旁）

11 日午餐，12 日午餐：酒店二楼餐厅

11 日晚餐：4 楼 2+3 厅



38

会议议题 Special Thanks

深圳市海思半导体有限公司

华为核“芯”--海思致力于共建全联接世界。作为技术

的领导者，海思为全球网络和超高清视频技术的端到端

创新铺平了道路。倾听客户需求，联合产业链开放创新，

提升半导体设计和工程工艺能力，交付高性能、高质量

的芯片与光电解决方案，实现共赢是海思呈现给世界的

独特价值。

海思是全球产品线最宽的芯片公司，并在多个领域具有

全球领先的技术能力，集团总部设在中国深圳，在成都，

北京，上海，武汉，新加坡，韩国，日本，欧洲等地设

有办事处和研究中心，全球员工人数超过 8000 人。经过

20 多年的研发，海思已经建立了强大的 IC 设计和验证技

术平台，累计开发 200 多种类型的芯片，提交了超过 5000

项专利。海思的愿景是围绕客户需求持续改进与创新，

提供业界最具竞争力的半导体平台与解决方案（芯片+光

电），成就客户、助力华为成为 ICT 行业领导者。



39

会议议题



40

会议议题

华人芯片设计 - icac workshop

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