(MRAM)

(EOL/ITRI)

DTF 2008 Embedded World 2008/01/22

MRAM

Outline

MRAM

From Forbes.com, 2006

SRAM

DRAM

FLASH

MRAM ()

PCM

DRAM SRAM

Flash

Speed

Rea

d/W

rite

cycl

es

MRAM

MemoryStorage

~ 40GB

~ 2-4GB

MRAM

Magnetic RAM ?

- RAM

HardDisk Driver

Byte/

Memory

Byte/

MRAM

high R, 1 state

low R, 0 state

Free Layer

Pined Layer

Key Device: MagneticTunneling Junction (MTJ)

FM: Free LayerFM: Free Layer-- Fe, Co, Fe, Co, NiFeNiFe, , CoFeCoFe, , CoFeBCoFeB

AFM: Pinning LayerAFM: Pinning Layer-- NiONiO, , PtMnPtMn, , IrMnIrMn

Tunneling BarrierTunneling Barrier-- AlAl22OO33, , MgOMgO

FM: Pinned LayerFM: Pinned Layer-- Fe, Co, Fe, Co, NiFeNiFe, , CoFeCoFe, , CoFeBCoFeB

FM

FM

AFM

Tunneling Barrier

Substrate

Cap Cap: Capping LayerCap: Capping Layer-- Ta , Ta , RuRu

Magnetic TunnelingJunction (MTJ)

FixedMagnetic Layer

Digit Line

Bit Line

Isolation Transistor ON

Free Magnetic Layer, InformationStorage.

{Tunneling Barrier{

{

Sense Current

Source : Motorola

MRAM

Isolation Transistor OFF

Program CurrentHe

Program CurrentHh

SourceUS6545906B1, Motorola, 2003

Toggle Mode MRAM- (a) SAF Free Layers, (b) Time-delay waveform

and (c) 45 deg. rotated cell

PtMn

Top Pinned Layer

RuBottom Pinned Layer

X

Al2O3 Barrier

Free 2, NiFe

Top Electrode

Bottom Electrode

Ru

Free 1, NiFe

(b)

(a) SAF: Spin Flop

(c) 45 deg.:

MRAM MRAM MRAM

Outline

(SOC)

Instant on System

(SOC)(SOC)(SOC)

Instant on SystemInstant on SystemInstant on System

,10

Ref.Philips Xenium9@9~30

LSISRAM/mA RAM/100A10

0

500

1000

1500

2000

2500

3000

A

100 A

Case 1 Case 2 Case 3

Logic

Memory

RAM

Logi

c

Mem

ory

1) Flash

2) FeRAM(Re-writable)

RAM

(SOC)

Instant on SystemInstant on SystemInstant on System

LogicMemory

SOC50%

CPU

Block

2

Application Block

LCD

Camera

GPS

etc.

&

RAM FLASH

RAM

Interface

Interface

Memory Bus

CPU

Core

Bus

I cache

D cache

CPU

Memory

App

licat

ion

Con

trol C

PU

(SOC)(SOC)(SOC)

Instant on System

zz

Flash ~ s

MRAM ~ 10ns

~ 100

Samsung, ISSCC 2004Samsung, ISSCC 2004

Instant-on System

Core

REGISTER

Cache

Storage

CPU

SRAM

Memory

RAMInstant on System

DRAM SRAM

PC

HDD Flash

Conventional: Load data from NVM, then process in SRAMNew NVM (MRAM): data ready in NVM, then process in the same NVM

,10

LogicMemory

SOC50%

Flash ~ s

MRAM ~ 10ns

~ 100

Ref.Philips Xenium9@9~30

zz

IBM/Infineon(ISSCC 2006)

Freescale(VLSI 2005)(IEDM 2005)

Samsung(InterMag 2003)

(IEDM 2003)

Renesas(VLSI 2004)

Sony(IEDM 2005)Spin-RAM

Hitachi(ISSCC 2007)

Spin-RAM

Toshiba/NEC(ISSCC 2006)

ITRI(IEDM 2006)

MR ratio (%) 35 (300mV) 40 (300mV) 27 (400mV) 20 (350mV) 160 (0 mV) 200

0.08 x 0.16

0.01

2 Mb

0.2

100

40

1.8

Jc ~ 6E6(A/cm2)

> 30 (300mV)

TMR size (um2) 0.30 x 0.60~ 0.30 x 0.90~ 0.22 x 0.55

0.40 x 0.80 0.26 x 0.48 0.10 x 0.15

0.24 x 0.48

16 Mb

0.13

34

1.87 (111 F2)

79

1.8

0.36 x 0.60

Specific Resistance

(K Ohm-um2)2 ~ 5

2 ~ 5~ 1

11 ~ 13 ~ 3 0.02 2 ~ 5

Memory Capacity

(bits)16 Mb

4 Mb4 Kb

64 Kb 1 Mb 4 Kb 1 Mb

Design rule (um) 0.180.180.09

0.24 0.13 0.18 0.15

Writing time (ns) 30 ~ 40 25 45 10 2 50

Reading time (ns) 30 ~ 40 25 10 35

Cell area (um2) 1.42 (43 F2)1.55 (48 F2)0.29 (36 F2)

2.06 (36 F2) 0.81 (47 F2) 1.57 (48 F2)

Chip area (mm2) 7928

3.88 36

Voltage (V) 1.8 / 3.3 1.8 / 3.3 2.0 1.2 1.2 / 3.3

Power (mW)ReadWrite

(16 I/O)

(16 I/O)55 mA

105 mA

(16 I/O)60 @ 100 MHz

Jc ~ 2.5E6 (A/cm2)

(16 I/O)

(8 I/O)10 mA80 mA

Mb-level MRAM

http://tw.renesas.com/homepage.jsp

MRAM Debuthttp://www.eetimes.com/news/latest/showArticle.jhtml?articleID=190301247

http://www.mram-info.com/

Instant-on computer

Military and space app.

NV-SRAMBattery-backed SRAM

Applications

4 Mb MRAM Data Sheet

http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=190301247

Why MRAM: Reliability and Endurance

Target Application

Automotive-use MCUs

Motorola RIZR Z8

,Motorola RIZR Z8Motorola--MRAM,Symbian RIZR Z8,(:)

(MRAM inside)

2007/12/20 http://news.sina.com.tw/tech/sinacn/cn/2007-12-20/101638218698.shtml

Source: Toshiba/NEC, ISSCC 2006

Toshibas 100 MHz Synchronous MRAM

Hybrid mode:- Asynchronous (34 ns)- Synchronous (100 MHz)- Burst mode (Latency:4)

4 Mb0.13um CMOS1.8V Vdd

D a t a / P r o g r a m M e m o r yM R A M

+MCU Embeded MRAM

GPS

MRAM

MRAM for

MRAM+MCU Pre-Crash

---

Source: NEC/ NNVM 2006

Source: NEC/ NNVM 2006

Die Size: 8.82 x 9.04 mm2

MTJ Size: 0.36x0.72 um2

Technology: TSMC 0.15LV1P5M + EOL MTJ BEOL

8 bit I/O, SRAM-Like Write 10mA (max.) Sensing Scheme (diff. amp.)

Power: 3.3V (Writing, I/O), 1.2V (Sensing) Access time < 50ns

1Mb MRAM (ITRI)

MRAM Demonstration- ARM9 MRAM Media

---

Source: http://www.dmatek.com.tw/

100 101 102 1030

8192

16384

24576

32768

Endurance Count (#)

Bit

Cou

nt (#

)

0

10

20

30

40

50

60

70

80

90

100

Bit Yield (%

)64 Kb

100 101 102 1030

8192

16384

24576

32768

Endurance Count (#)

Bit

Cou

nt (#

)

0

10

20

30

40

50

60

70

80

90

100

Bit Yield (%

)

93.9%

74.3%

99.8%

DNP Toggle

99.9%

Submitted to VLSI 2008

100 101 102 103 104 105 106 107 108 109

0

1

Tog

gle

Succ

ess

Cycles (#)

0 2 4 6 8 10 12 14 16 18 20

0

1

Tog

gle

Succ

ess

Cycles (#)

Typical150

DNP150

True

False

True

False

Submitted to VLSI 2008

ITRI Robust MRAM- (Obtuse + DNP) 64 Kb

High Speed Capability for Embedded Memory Application ?

Source: NEC, VLSI 2006

Single pulse waveformenables a fast writing and a wide margin

Fast Writing of 2T1MTJ Structure

Source: NEC, VLSI 2006

5T2MTJ Cell Structure

Source: NEC, VLSI 2006

MRAM Cell Technologyfor Over 500 MHz SoC

MRAM MRAM MRAM

Outline

0%

20%

40%

60%

80%

100%

1999 2002 2005* 2008* 2011* 2014*

20%52%

72%83%

90%94%

MRAMMTJ

Spin-transfer MRAMMTJ

Spin-transfer MRAM

Conventional MRAM

MTJ short side length (nm)

Prog

ram

cur

rent

(m

A)

100 1000

0.01

0.1

110

Scalable Spin-RAM

Spin-transfer MRAMCMOS

MRAM 65nm Spin-transfer MRAMeDRAM

- Spin-RAM 65 nm

MRAM Scalability

Spin-Torque-Transfer Switching

T

The atom receives a torque by absorbinga net spin angular momentum of electrons:the spin torque can be used for spintronics

Mp M

( )

/

J P

eJ B s

dM a M M Mdt

a PJ eM

=

=

rv v v

J. C. Slonczewski, 1996

Angular momentum transfer

Sony: Spin-RAM

0.18um CMOS MTJ Size: 100x150nm (tailored MTJ)

Writing current : 300 A (2.5 E6 A/cm2) MR% > 160%, RA=20 Ohm-um2

Sony, IEDM 2005/12

- Sony : Spin-RAM (Spin Torque Transfer Magnetization Switching)

~ M. Hosomi et al. IEDM 2005

Sony: Spin-RAM

Sony, IEDM 2005/12

Exhibits great endurance characteristic Data retention could be a problem

~7 sec

Race-track Memory

Race-track Memory

- Low Cost(Density)

- Performance(Random Access)

- Reliability(Endurance)

- 3D Solid-State Memory

- Spin-Torque DW motion

- TMR Sense Circuitry

- HD on a Chip

- Flash, HD replacement

Hard Disk

MRAM

Source: Parkin, IBM

Features:

Source: Hitachi

Vision of Race-Track Memory

- Performance- Reliable- Anti Shock

- Low Cost- Less Reliable- Very Slow

MRAM

(SOC)90%

MRAM50%

(MCU)

Ultra-high Speed SRAM

High Speed SRAM

Low power SRAM

eDRAM

eFlashFlash

DRAM

Cell Size(m2)

Clock Frequency (M

Hz)

1000

100

10

1.0 0.5 0.1

1st Gen. of MRAM

Ne