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EDA Summer Training Slide 1

Course Outline 1. Introduction to front-end design automation 2. Modeling 3. Scheduling 4. Resource binding 5. Two-level logic optimization 6. Multi-level logic optimization 7. Sequential logic optimization 8. Technology mapping 9. FPGA synthesis 10. Introduction to back-end design automation 11. Partitioning 12. Floorplanning 13. Placement 14. Global Routing 15. Detailed Routing 16. Clock and Power Routing 17. Emerging topics

YZU & NTUST Joint Lab


Design a Grading System

5 homework assignments (25%) 6 in-class quizzes (ignore lowest score) (25%) 1 midterm examination (25%) 1 final-term examination (25%) 1 extra term project Some bonus – class participation

Can you design a grading system?



Overall Data Flow Graph (DFG)

Final

HW Quiz Midterm Final-term Project Bonus 25% 5%



Homework DFG

HW1 HW2 HW3 HW4 HW5

Homework



Quiz DFG

Q1 Q2 Q4 Q5 Q6 Q3

—

Quiz

— MUX

A B

min



Overall DFG

Final

HW Quiz Midterm Final-term Project Bonus 25% 5%



Overall DFG HW1 HW2 HW3 HW4 HW5 Q1 Q2 Q4 Q5 Q6 Q3 Midterm Final-term Project Bonus

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Final

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Control Steps HW1 HW2 HW3 HW4 HW5 Q1 Q2 Q4 Q5 Q6 Q3 Midterm Final-term Project Bonus

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8 Control Steps HW1 HW2 HW3 HW4 HW5 Q1 Q2 Q4 Q5 Q6 Q3 Midterm Final-term Project Bonus

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7 Control Steps HW1 HW2 HW3 HW4 HW5 Midterm Final-term Project Bonus Q1 Q2 Q4 Q5 Q6 Q3

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6 Control Steps HW1 HW2 HW3 HW4 HW5 Midterm Final-term Project Bonus Q1 Q2 Q4 Q5 Q6 Q3

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Single-cycle Implementation HW1 HW2 HW3 HW4 HW5 Midterm Final-term Project Bonus Q1 Q2 Q4 Q5 Q6 Q3

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Multi-cycle Implementation HW1 HW2 HW3 HW4 HW5 Midterm Final-term Project Bonus Q1 Q2 Q4 Q5 Q6 Q3

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Final

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Resource Binding HW1 HW2 HW3 HW4 HW5 Midterm Final-term Project Bonus Q1 Q2 Q4 Q5 Q6 Q3

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Register Binding HW1 HW2 HW3 HW4 HW5 Midterm Final-term Project Bonus Q1 Q2 Q4 Q5 Q6 Q3

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Resource Allocation HW1 HW2 HW3 HW4 HW5 Midterm Final-term Project Bonus Q1 Q2 Q4 Q5 Q6 Q3

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FF FF FF FF FF FF FF FF FF



Resource Allocation HW1 HW2 HW3 HW4 HW5 Midterm Final-term Project Bonus Q1 Q2 Q4 Q5 Q6 Q3

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Final

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FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF



Cell Connectivity

FF FF FF FF FF FF FF FF FF



Floorplan

2-row height

3-row height

4-row height 5-row height

6-row height



Cell Placement in 2 Rows

FF

FF

FF FF

FF

FF

FF FF FF

FF FF FF FF FF FF

FF

FF FF



Cell Placement in 3 Rows

FF FF

FF FF FF

FF

FF

FF FF

FF

FF

FF FF

FF

FF

FF

FF

FF



Cell Placement in 4 Rows FF FF FF

FF

FF FF

FF

FF

FF

FF FF

FF FF

FF

FF

FF

FF

FF



Routing

FF FF

FF FF

FF

FF

FF

FF

FF


High Level Synthesis



High Level Synthesis (HLS) A process of converting high-level description of a design to a netlist

– Input: • High-level languages (ex: C) • Behavioral hardware description languages (ex: Verilog, VHDL) • Structural HDLs (ex: Verilog, VHDL) • State diagrams / logic networks

– Tools: • Parser • Library of modules

– Constraints: • Area constraints (ex: # modules of a certain type) • Delay constraints (ex: set of operations should finish in λ clock

cycles) – Output:

• Operation scheduling (time) and binding (resource) • Control generation and detailed interconnections



High-Level Synthesis Compilation Flow

Lex

Parse

Compilation front-end

Behavioral Optimization

Intermediate form

Arch synth Logic synth

Lib Binding HLS backend

x = a + b × c + d

+

+

×

a b c d

+

+ ×

a d b c

Tree-height reduction



Behavioral Optimization Techniques used in software compilation

– Expression tree-height reduction – Constant and variable propagation – Common sub-expression elimination – Dead-code elimination – Operator strength reduction (ex: *4 << 2)

Typical Hardware transformations – Conditional expansion

• If (c) then x=A else x=B compute A and B in parallel, x=(C)?A:B

– Loop expansion • Instead of three iterations of a loop, replicate the loop

body three times (unrolling)

A

B x

c



Architectural Synthesis Deals with “computational” behavioral descriptions

– Behavior as sequencing graph (aka dependency graph, or data flow graph DFG)

– Hardware resources as library elements • Pipelined or non-pipelined • Resource performance in terms of execution delay

– Constraints on operation timing – Constraints on hardware resource availability – Storage as registers, data transfer using wires

Objective – Generate a synchronous, single-phase clock circuit – Might have multiple feasible solutions (explore tradeoff) – Satisfy constraints, minimize objective:

• Maximize performance subject to area constraint • Minimize area subject to performance constraints


Modeling



Model Classifications Abstraction levels

– Architectural – Logic – Geometrical

Views – Behavioral – Structural – Physical

Media – Language – Diagram – Mathematical model



Abstraction Levels

... PC = PC + 1; FETCH(PC); DECODE(INST); ...

Architectural level

Logic level

Geometrical level



Views and Abstraction Levels

architectural-level

logic-level

geometrical-level

physical-view

structural-view behavioral-view



Levels of Abstractions and Corresponding Views

Logic Level

Architectural Level

Views Levels

Structural View Behavioral View

state0

state1

state2

state3

... PC = PC + 1; FETCH(PC); DECODE(INST); ...

MULT

ADD CONTROL

RAM

a b c

d

x

y



Synthesis

Synthesis – A set of transformation between two views

Synthesis tasks

– Architectural-level synthesis • High-level synthesis, structural synthesis

– Logic-level synthesis • Gate-level structure, library binding (mapping)

– Geometrical-level synthesis • Physical design



Synthesis Tasks

architectural-synthesis

logic-synthesis

physical-design

architectural-level

logic-level

geometrical-level

physical-view

structural-view behavioral-view



Gajski’s Y-chart



Y-chart Domain Mapping



Y-transformations



Top-down Design



Levels Revealed



Synthesis Levels and Tasks System level synthesis

– Clustering – Communication synthesis

High-level synthesis – Resource or timing constrained scheduling – Resource allocation – Binding

Register transfer level synthesis – Data-path synthesis – Controller synthesis – Logic-level synthesis – Logic minimization – Optimization, overhead removal – Library mapping

Physical level synthesis – Placement – Routing



Abstract Models

Abstract models for different circuit views – Structure – Logic network

• Combinational logic network • Sequential logic network

– State diagram – Data-flow and Sequencing Graph



Abstract Models – Structure

Module, net, pin Incidence matrix Hypergraph Bipartite graph

M1 M3

M2 N1

N2

N3

M1

M2 M3

M1

M2

M3

N1

N2

N3

110011111

N1

M1

M2

M3

N2 N3



Abstract Models – Logic Network

Combinational logic network

Sequential logic network

Ma

Mb

v1

v2

v3

v4

v5

Ma

v1 Mb

Mc Md

Me v3

v2



Abstract Models – State Diagram



Abstract Models – Data-flow and Sequencing Graph

× +

<

–

×

×

× ×

×

–

+

u1

dx3 x 3 y u dx x dx

1 2 6

3 7 9 11

108

4

5

dxy

x1 a

cy1u

u

× +

<

–

×

×

× ×

×

–

+

1 2 6

3 7 9 11

108

4

5

NOP

NOP

0

n

Data-flow Graph Sequencing Graph



Traditional Waterfall Model



Spiral SOC Design Flow



Spiral SOC Design Flow Characteristics

– Parallel, concurrent development of hardware and software – Parallel verification and synthesis of modules – Floorplan, placement, and routing are included in the

synthesis process – Modules developed only if a pre-designed hard or soft

macro is not available – reusability – Planned iteration throughout

The engineers are addressing all aspects of hardware and

software design concurrently: functionality, timing physical design, and verification



Waterfall vs. Spiral Traditional ASIC development follows so called waterfall model

– Project transitions from phase to phase in step – Never returning to the activities of the previous phase – “Tossing” project over the wall from one team to the next

However… – Complexity increases – Geometry shrinks – Time-to-market pressure increases

In the spiral model, the design teams work on multiple aspects

of the design simultaneously, incrementally improving in each area as the design converges on completion


Scheduling



Synthesis in Temporal Domain

Scheduling and binding can be done in different orders or together

Scheduling: – Mapping of operations to time slots (cycles) – A scheduled sequencing graph is a labeled graph

+

NOP

× × × ×

× × + <

-

-

NOP

1

2

3

4

+

NOP

×

×

× ×

×

×

+

<

-

-

NOP

1

2

3

4



Schedule in Spatial Domain Resource sharing

– More than one operation bound to same resource – Operations have to be serialized – Can be represented using hyperedges (define vertex

partition)

+

NOP

× × × ×

× × + <

-

-

NOP

1

2

3

4



Scheduling and Binding Resource constraints:

– Number of resource instances of each type {ak : k=1, 2, ..., nres}

Scheduling: – Labeled vertices φ (v3)=1

Binding: – Hyperedges (or vertex partitions) β (v2)=adder1

Cost: – Number of resources ≈ area – Registers, steering logic (mux, bus), wiring, control unit

Delay: – Start time of the “sink” node – Might be affected by steering logic and scheduling (control

logic) – resource-dominated vs. control-dominated

Resource dominated

Control dominated



How Is the Datapath Implemented?

Assuming the following scheduling and binding – Wires between

modules? – Input selection? – How does binding /

scheduling affect congestion?

– How does binding / scheduling affect steering logic?

+

×

×

× ×

×

×

+

<

-

-

1

2

3

4



Min Latency Unconstrained Scheduling

Simplest case: no constraints, find minimum latency Given set of vertices V, delays D, and partial order ≻

on operations E, find an integer labeling of operations φ: V Z+, such that: – ti = φ (vi) – ti ≥ tj + dj ∀ (vj, vi) ∈ E – λ = tn – t0 is minimum

Solvable in polynomial time Bounds on latency for resource constrained

problems ASAP algorithm used: topological order



ASAP Scheduling Schedule v0 at t0=0 While (vn not scheduled)

Select vi with all scheduled predecessors Schedule vi at ti = max {tj+dj}, vj being a predecessor of vi

Return tn

+

NOP

× × × ×

× × + <

-

-

NOP

1

2

3

4



ALAP Scheduling (Latency Constrained)

Schedule vn at t0=λ While (v0 not scheduled)

Select vi with all scheduled successors Schedule vi at ti = min {tj-dj}, vj being a successor of vi

Return tn

+

NOP

×

×

× ×

×

×

+ <

-

-

NOP

1

2

3

4



Resource Constraint Scheduling

Constrained scheduling – General case NP-complete – Minimize latency given constraints on area or

the resources (ML-RCS) – Minimize resources subject to bound on latency (MR-LCS)

Exact solution methods – ILP: Integer Linear Programming – Hu’s heuristic algorithm for identical processors (operations)

Heuristics – List scheduling – Force-directed scheduling


Resource Allocation



Allocation and Binding

Allocation: – Number of resources available

Binding: – Relation between operations and resources

Sharing: – Many-to-one relation

Optimum binding/sharing: – Minimize the resource usage



Compatibly and Conflicts Operation compatibility:

– Same type – Non concurrent

Compatibility graph: – Vertices: operations – Edges: compatibility relation

Conflict graph: – Complement of compatibility graph

t1 x=a+b y=c+d 1 2

t2 s=x+y t=x-y 3 4

t3 z=a+t 5

1 2

3 4

5

Compatibility graph

Conflict graph

1 2

3 4

5



Compatibility and Conflicts

Compatibility graph: – Partition the graph into a minimum number of

cliques – Find clique cover number κ( G+ )

Conflict graph: – Color the vertices by a minimum number of colors – Find the chromatic number χ( G_ )

NP-complete problems: – Heuristic algorithms



Example t1 x=a+b y=c+d 1 2

t2 s=x+y t=x-y 3 4

t3 z=a+t 5

Conflict

1 2

3 4

5

1 2

3 4

5

Compatibility

Partitioning Coloring

ALU1: 1,3,5 ALU2: 2,4



Comparability Graph Example

TIME 1

TIME 2

TIME 3

TIME 4

*

*

+

<

-

-

* *

*

*

+

NOP

NOP

0

1 2

3

4

5

6

7 8

9

10

11

n

3 1 8

7 6 2

4 10

5 11

9



Interval Graph Example

TIME 1

TIME 2

TIME 3

TIME 4

*

*

+

<

-

-

* *

*

*

+

NOP

NOP

0

1 2

3

4

5

6

7 8

9

10

11

n

1

4

5 9

10 2

3 6

7 8

11



Left-edge Algorithm

Input: – Set of intervals with left and right edge – A set of colors (initially one color)

Rationale: – Sort intervals in a list by left edge – Assign non overlapping intervals to first color

using the list – When possible intervals are exhausted,

increase color counter and repeat



Example 0 1 2 3 4 5 6 7

1

6

4

7

8

2

3

5

1

0 1 2 3 4 5 6 7 8

2 3

6 7 5

4

1 6

7 4

2

3

5

Conflict graph

Intervals 6

7 4

2

1

3

5

Colored conflict graph Coloring



Register Binding Problem

Given a schedule: – Lifetime intervals for variables – Lifetime overlaps

Conflict graph (interval graph): – Vertices ↔ variables – Edges ↔ overlaps – Interval graph

Compatibility graph (comparability graph): – Complement of conflict graph



Register Sharing in Data-flow Graphs

Given: – Variable lifetime conflict graph

Find: – Minimum number of registers storing all the

variables Key point:

– Interval graph • Left-edge algorithm (polynomial-time

complexity)


EDA Lecture04 Slide 78

Example of DFG

* *

* *

* -

-

TIME 1

TIME 2

TIME 3

TIME 4

1 2

3

4

5

6

7

z1 z2

z3 z4

z5 z6

z1

z3

z5

z2

z4

z6

z1 z2

z3 z4

z5 z6

(a) (b) (c)



Register Sharing General Case

Iterative conflicts: – Preserve values across iterations – Circular-arc conflict graph

• Coloring is intractable Hierarchical graphs:

– General conflict graphs • Coloring is intractable

Heuristic algorithms


EDA Lecture04 Slide 80

Example of General Case

TIME 1

TIME 2

TIME 3

TIME 4

<

* *

*

*

+

*

*

+ -

-

3 x u dx

3

y u dx x dx

dx

y

u

u y

c

a

4

5

3

7

9

1 2

6

8

10

11

z1 z2

z3 z4

z5 z6 z7

x y

u

z1 z2

z3 z4

z5 z6

u y

u y

z7

x

x

(a) (b)



Example Variable-lifetimes and Circular-arc Conflict Graph

z1 z2

z3 z4

z5 z6

u

z7

x y

x

1

2

3

4

z5 z6

z7

z4 z3

z1

z2

u y



Module Selection Problem

Extension of resource sharing – Library of resources: – More than one resource per type

Example: – Ripple-carry adder – Carry look-ahead adder

Resource modeling: – Resource subtypes with

• (area, delay) parameters



Example

Multipliers with: – ( Area, delay ) = ( 5,1 ) and ( 2,2 )

Latency bound of 5

*

*

+

<

-

-

*

*

*

*

+

NOP

NOP

0

1

2

3

4

5

6

7

8

9

10

11

n

TIME 1

TIME 2

TIME 3

TIME 4

TIME 5

(1,1) (1,2)

(2,1)

(2,2)

Slow multipliers save area



Example 2

Latency bound of 4 – Fast multipliers for { v1 , v2 , v3 } – Slower multiplier can be used elsewhere

• Less sharing Minimum-latency design uses fast multipliers only

– Impossible to use slow multipliers

*

*

+

<

-

-

* *

*

*

+

NOP

NOP

0

1 2

3

4

5

6

7 8

9

10

11

n

TIME 1

TIME 2

TIME 3

TIME 4

(1,1) (1,2) (2,1)

(2,2)



Data Path Synthesis

Applied after resource binding Connectivity synthesis:

– Connection of resources to multiplexers busses and registers

– Control unit interface – I/O ports

Physical data path synthesis – Specific techniques for regular datapath design

• Regularity extraction



Example

* ALU

DATA-PATH CONTROL-UNIT

r2 r1 u y x

dx 3 a

REGISTERS

enable

Mux control

ALU control (+,-,<)

c



Control Synthesis

Synthesis of the control unit Logic model:

– Synchronous FSM Physical implementation:

– Hard-wired or distributed FSM – Microcode



Example

* *

*

-

-

*

*

* +

+ <

NOP

NOP

1 2

3

4

5

6

7

8

9

10

11

0

n

TIME 1

TIME 2

TIME 3

TIME 4

4

s1

s4 s3

s2

reset’

reset’ reset

5

reset reset

reset’ 1,2,6,8,10 3,7,9,11



Summary

Resource sharing is reducible to vertex coloring or to clique covering: – Simple for flat graphs – Intractable, but still easy in practice, for other graphs – Resource sharing has several extensions:

• Module selection Data path design and control synthesis are conceptually simple

but still important steps – Generated data path is an interconnection of blocks – Control is one or more finite-state machines


Logic Synthesis



Why Logic Level? Logic-level synthesis is the core of today's CAD flows for IC

and system design – course covers many algorithms that are used in a broad

range of CAD tools – basis for other optimization techniques – basis for functional verification techniques

Most algorithms are computationally hard – covered algorithms and flows are good example for

approaching hard algorithmic problems – course covers theory as well as implementation details – demonstrates an engineering approaches based on

theoretical solid but also practical solutions • very few research areas can offer this combination



What is Logic Synthesis?

D

X Y λδ

Given: Finite-State Machine F(X,Y,Z,λ,δ) where:

X: Input alphabet Y: Output alphabet Z: Set of internal states λ : X × Z → Z (next state function) δ : X × Z → Y (output function)

Target: Circuit C(G, W) where G: set of circuit components g (Boolean gates flip-flops, etc} W: set of wires connecting G



Typical Synthesis Scenario

- Read Verilog/VHDL - Control/data flow analysis

- Basic logic restructuring - Crude measures for goals

- Use logic gates from target cell library

- Timing optimization - Physically driven optimizations

RTL to Network Transformation

Technology Independent Optimizations

Technology Mapping

Technology Dependent Optimizations

Test Preparation - Improve testability - Test logic insertion



Objective Function for Synthesis

Minimize area – in terms of literal count, cell count, register count, etc.

Minimize power – in terms of switching activity in individual gates, blocks, etc.

Maximize performance – in terms of maximal clock frequency of synchronous

systems, throughput for asynchronous systems Any combination of the above

– combined with different weights – formulated as a constraint problem

• Ex: minimize area for a clock speed > 300MHz



Boolean Function

Let B = {0,1} Y = {0,1,2} – A logic function f in n inputs x1, x2, ...xn and m

outputs y1,y2, ...ym is a function

– m=1 a single output function – m>1 a multiple output function

f : Bn Ym

mm

nn

YyyyYBxxxX

∈=

∈=

],...,,[

],...,,[

21

21 is the input is the output



Basic Definitions

For each component fi, i = 1,2, ...,m, define – ON_SET: set of input values x such that fi(x) =1 – OFF_SET: set of input values x such that fi(x) = 0 – DC_SET: set of input values x such that fi(x) = 2

Completely specified function: DC_SET = φ, ∀ fi Incompletely specified function: DC_SET ≠ φ , for

some fi



Boolean Representations Truth table representation Full adder X Y Cin Sum Cout

A multiple output function Sum

– on-set = – off-set =

A completely specified function

Truth table representation Full adder X Y Cin Sum Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

– {(0 0 1), (0 1 0), (1 0 0), (1 1 1)} – {(0 0 0), (0 1 1), (1 0 1), (1 1 0)}



Boolean Representations

Geometrical representation

0 1 2 variables

00 01

10 11

3 variables

000 100 110

111 011 001 101

010 010

1 variable

sum : on-set ={(0 0 1),(0 1 0),(1 0 0),(1 1 1)}

off-set ={(0 1 1),(1 0 1),(1 1 0),(0 0 0)}




Algebraic representations – Canonical sum of product

• Cout = x’yCin + xy’Cin + xyCin’ + xyCin

– Reduced sum of product • Cout = yCin + xCin + xy • = yCin + xCin + xyCin’

– Multi-level representation • Cout = Cin (x + y) + xy




Logic gate representations

a

b

c

a

b

c




A Binary Decision Diagram (BDD) is a directed acyclic graph – Graph: set of vertices connected by edges – Directed: edges have direction – Acyclic: no path in the graph can lead to a cycle

– Often abbreviated as DAG



BDD Example

F = (a + b) c

0 1 a

0 0

0 1

b b

0 1

0 1

c c

c b

1 1 0 0

0 1 0 1 0 1 0 1

a b c F

0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1

1. Each vertex represents a decision on a variable 2. The value of the function is found at the leaves 3. Each path from root to leaf corresponds to a row in the truth table



A Few Simple Functions

x

1 0

0 1

0 1

F = 0 F = 1

F = x

0 1 a

0 1 b

c

1 0

0 1

F = c

F = (a+b)c

F = bc

F = 1



A Network Example

a 1 0

0 1

c 1 0

0 1

b 1 0

0 1

a 0 1

b 1 0

0 1

b 0 1

c 1 0

0 1

0 1 a

0 1 b c

1 0 0 1



Variable Ordering Algorithms

Problem: given a function F, find the variable order that minimizes the size of its ROBBDs

Answer: problem is intractable Two heuristics

– Static variable ordering (1988) – Dynamic variable ordering (1993)



Static Variable Ordering

Variables are ordered based on the network topology – How: put at the bottom the variables that are

closer to circuit’s outputs – Why: because those variables only affect a small

part of the circuit – Disclaimer: it’s a heuristic, results are not

guaranteed

a b

c good order: a < b < c



Dynamic Variable Ordering

Changes the variable order on-the-fly whenever ROBDDs become too big

How: trial and error – SIFTING ALGORITHM 1. Choose a variable 2. Move it in all possible positions of the variable

order 3. Pick the position that leaves you with the

smallest ROBDDs 4. Choose another variable …



Dynamic Variable Ordering

Tiny example: F=(a+b)c – we want to find the optimal position for variable c

0 1 a

0 1 b c

1 0 0 1

0 1 c

0 1 a b

1 0 0 1

0 1 c b

1 0 0 1

a 0 1

c 0 1

initial order: a < b < c

Swap (b, c): a < c < b

Swap (a, c): c < a < b

Final order: c<a<b



Summary

BDDs – Very efficient data structure – Efficient manipulation routines – A few important functions don’t come out well – Variable order can have a high impact on size

Application in many areas of CAD

– Hardware verification – Logic synthesis


Two-level Logic Synthesis


EDA Slide 113

f2

001 101

111

f1

c b a 000

001

110

101

Cubical Representation of Minterms and Implicants

f1 = a'b'c' + a'b'c + ab'c + abc +abc' f2 = a'b'c + ab'c

α

β γ

δ β

Summer Training


EDA Slide 114

Representations

Visual representations – Cubical notation – Karnaugh maps

Computer-oriented representations – Matrices

• Sparse • Various encoding

– Binary-decision diagrams • Address sparsity and efficiency

Summer Training


EDA Slide 115

Two-level Minimization

Assumptions – Primary goal is to reduce the number of

implicants – All implicants have the same cost – Secondary goal is to reduce the number of literals

Rationale – Implicants correspond to PLA rows – Literals correspond to transistors

Summer Training


EDA Slide 116

Example f1 = a'b'c' + a'b'c + ab'c + abc +abc'; f2 = a'b'c + ab'c

f1 f2 β

α

β δ

Minimum cover

α

γ δ

β

Irredundant cover

α

β γ δ

β

Minimal cover w.r.t. single implicant containment

Summer Training


EDA Slide 117

Definitions

Prime implicant – Implicant not contained by any other implicant

Prime cover – Cover of prime implicants

Essential prime implicant – There exist some minterms covered only by that

prime implicant – MUST be included in the cover

Summer Training


EDA Slide 118

Two-level Logic Minimization

Exact methods – Compute minimum cover – Often difficult/impossible for large functions – Based on Quine-McCluskey method

Heuristic methods – Compute minimal covers (possibly minimum) – Large variety of methods and programs

• MINI, PRESTO, ESPRESSO

Summer Training


EDA Slide 119

Example f = a'b'c' + a'b'c + ab'c +abc +abc' Primes:

Table:

α

β γ δ

Prime implicants of f

α

β δ

Minimum cover of f

Summer Training


EDA Slide 120

Minimum Cover Early Methods

Reduce table – Iteratively identify essentials – Save them in the cover – Remove covered minterms

Petrick's method – Write covering clauses in pos form – Multiply out pos form into sop form – Select cube of minimum size

Remark – Multiplying out clauses has exponential cost

Summer Training


EDA Slide 121

Example

pos clauses – (α) (α + β) (β + γ) (γ + δ) (δ) = 1

sop form: – αβδ + αγδ = 1

Solutions: { α β δ } { α γ δ }

α

β γ δ

Summer Training


EDA Slide 122

Matrix Representation

View table as Boolean matrix: A Selection Boolean vector for primes: x Determine x such that

– A x ≥ 1 – Select enough columns to cover all rows

Minimize cardinality of x

Summer Training


EDA Slide 123

Example

Summer Training


Multilevel Logic Synthesis



Example of General Network



Elimination



Decomposition



Extraction



Simplification



Substitution



Example – Sequence of Transformations

j = a’ + b + c k = c + d q = a + b s = ke + a’ + b’ t = kq + e u = q + c v = jd + ae’


Technology Mapping



Library Binding Given an unbound logic network and a set of library cells

– Transform into an interconnection of instances of library cells

– Optimize delay • Under area or power constraints

– Optimize area • Under delay and/or power constraints

– Optimize power • Under delay and/or area constraints

Library binding is called also technology mapping – Redesigning circuits in different technologies



Library binding: issues Matching:

– A cell matches a sub-network when their terminal behavior is the same

– Tautology problem – Input-variable assignment problem

Covering: – A cover of an unbound network is a partition into

sub-networks which can be replaced by library cells.

– Binate covering problem



Assumptions Network granularity is fine

– Decomposition into base functions: – 2-input AND, OR, NAND, NOR

Trivial binding – Use base cells to realize decomposed network – There exists always a trivial binding:

• Base-cost solution…



Example



Example

x = b + c y = ax z = xd

AND2 4 Cost

OR2

Library

OA21

4

5

v2

v3

v1

b

c

d z

y

x

a

b c

d

a

x

z

y m1: {v1,OR2} m2: {v2,AND2} m3: {v3,AND2} m4: {v1,v2,OA21} m5: {v1,v3,OA21}

x

v3

v2

v1



Example Vertex covering:

– Covering v1 : ( m1 + m4 + m5 ) – Covering v2 : ( m2 + m4 ) – Covering v3 : ( m3 + m5 )

Input compatibility: – Match m2 requires m1

• (m’2 + m1) – Match m3 requires m1

• (m’3 + m1 ) Overall binate covering clause

– (m1+m4+m5) (m2+m4)(m3+m5)(m’2+m1)(m’3+m1) = 1

x

v3

v2

v1



Decomposition



Partitioning



Covering



Tree-based matching Network:

– Partitioned and decomposed • NOR2 (or NAND2) + INV • Generic base functions

– Not much used • Subject tree

Library – Represented by trees – Possibly more than one tree per cell

Pattern recognition – Simple binary tree match – Aho-Corasik automaton



Simple library



Example

SUBJECT TREE PATTERN TREES

cost = 2 INV

cost = 3 NAND

cost = 4 AND

cost = 5 OR



Example: Lib

Match of s: t1 cost = 2

s

r

u

t

Match of u: t2 cost = 3

s

r

u

t

Match of t: t1 cost = 2+3 = 5

s

r

u

t

Match of t: t3 cost = 4

s

r

u

t

Match of r: t2 cost = 3+2+4 =9

s

r

u

t

Match of r: t4 cost = 5+3 =8


Physical Design Automation



Physical Design Automation Interlock

Automation Techniques

VLSI Physical Design

Graph algorithms Partition

Graph algorithms mathematical programming

Placement

Shortest path Mathematical programming

Greedy algorithm

Routing

The most important thing often is to find the right problem formulation



Basic Components in VLSI Circuits

Devices – Transistors – Logic gates and cells – Function blocks

Interconnects – Local signals – Global signals – Clock signals – Power/ground nets

Pad Metal1 Via Metal2

I/O Data Path

ROM/

RAM

PLA

A/D Converter

Random logic



Physical Design

Physical design converts a circuit description into a geometric description. This description is used to manufacture a chip. The physical design cycle consists of – Partitioning – Floorplanning and Placement – Routing – Compaction



Physical Design Process

Design Steps:

Partition & Clustering

Floorplan & Placement

clk

clk clk

a

a

a Pin Assignment

Global Routing Global Routing

Detailed Routing

Methodology:

Divide-and-Conquer



Physical Design Cycle Physical Design Circuit Design

(a)

(b)

(c)

(d)

Partitioning

Floorplanning Placement

Routing

Compaction

Fabrication

cutline 2

cutline 1



Complexities of Physical Design

More than 100 million transistors Performance driven designs Power-constrained designs Time-to-Market

Design cycle

High performance, high cost

……



History 101 of Physical Design

Born in early 60’s (board layout) Passed teenage in 70’s (standard cell place and

route) Entered early adulthood in 80’s (over-the-cell routing) Declared dead in late 80’s !!! Found alive and kicking in 90’s Physical Design (PD) has become a dominant force

in overall design cycle, – thanks to the deep submicron scaling – expand vertically with logic synthesis and

interconnect optimization, analysis…. => Design closure!



Why Physical Design is still HOT?

Many existing solutions are still very suboptimal – Ex: placement

Interconnect dominates – No physical layout, no accurate interconnect

More new physical and manufacturing effects pop up – Crosstalk noise, … – OPC (manufacturability), etc.

More vertical integration needed Physical design is the KEY linking step between

higher level planning/optimization and lower level modeling



Technology Trend and Challenges

Interconnect determines the overall performance In addition: noise, power => Design closure Furthermore: manufacturability => Manufacturing closure

Source: ITRS’03



Placement Challenge Placement, to large extend, determines the overall interconnect If it sucks, no matter how well you interconnect optimization

engine works, the design will suck Placement is a very old problem, but got renewed interest

– Mixed-size (large macro blocks and small standard cells) – Optimality study shows that placement still a bottleneck – Not even to mention performance driven, and coupled with

buffering, interconnect optimizations, and so on (all you name)



VLSI Global Placement Examples

Which one of the two placement results is better?



FloorPlacer (Mix-mode Placement)

Many macros data paths + dust logic I/O constraint (area I/O or wirebond)

(source: IBM)



Lithography



Optical Proximity Correction (OPC)



OPC-Aware Routing

More OPC friendly


Introduction to Partition



System Hierarchy



Levels of Partitioning

System Level Partitioning

Board Level Partitioning

Chip Level Partitioning

System

PCBs

Chips

Subcircuits / Blocks



Partitioning of a Circuit



Importance of Circuit Partitioning

Divide-and-conquer methodology – The most effective way to solve problems of high complexity – Ex: min-cut based placement, partitioning-based test

generation,… System-level partitioning for multi-chip designs

– Inter-chip interconnection delay dominates system performance. Circuit emulation/parallel simulation

– Partition large circuit into multiple FPGAs (e.g. Quickturn), or multiple special-purpose processors (e.g. Zycad).

Parallel CAD development – Task decomposition and load balancing

In deep-submicron designs, partitioning defines local and global interconnect, and has significant impact on circuit performance

…



Circuit Representation

Netlist: – Gates: A, B, C, D – Nets: {A,B,C}, {B,D}, {C,D}

Hypergraph:

– Vertices: A, B, C, D – Hyperedges: {A,B,C}, {B,D}, {C,D}

– Vertex label: Gate size/area – Hyperedge label:

Importance of net (weight)

A B

C D

A B

C D



Circuit Partitioning Formulation

Bi-partitioning formulation: Minimize interconnections between partitions

Minimum cut: min c(x, x’) Minimum bisection: min c(x, x’) with |x|= |x’| Minimum ratio-cut: min c(x, x’) / |x||x’|

X X’

c(X,X’)



A Bi-partitioning Example

Min-cut: Min-bisection cut: Min-ratio-cut:

a

b

c e

d f

mini-ratio-cut min-bisection

min-cut 9

10

100 100 100

100 100

100

4

Ratio-cut helps to identify natural clusters

cut size = 13 cut size = 300 cut size = 19



Circuit Partitioning Formulation

General multi-way partitioning formulation: – Partition a network N into N1, N2, …, Nk such that

• Each partition has an area constraint

• Each partition has an I/O constraint – Minimize the total interconnection:

∑ ∈

≤ i N v

i A v a ) (

i i i I N N N c ≤ − ) , (

) , ( i N

i N N N c i

− ∑



Problem Formulation

Input: A graph with – Set vertices V (|V| = 2n) – Set of edges E (|E| = m) – Cost cAB for each edge {A, B} in E

Output: 2 partitions X & Y such that – Total cost of edges cut is minimized – Each partition has n vertices

This problem is NP-Completeness!!!!!



A Trivial Approach

Try all possible bisections, find the best one If there are 2n vertices, # of possibilities =

For 4 vertices (A,B,C,D), 3 possibilities 1. X={A,B} & Y={C,D} 2. X={A,C} & Y={B,D} 3. X={A,D} & Y={B,C}

For 100 vertices, 5x1028 possibilities – Need 1.59x1013 years if one can try 100M

possibilities per second

22nnC = (2n)! / (2 × (n!2)) = nO(n)



-1

-2

-1

1

0

0

2

0

0

1

-1

-1

-2 0

FM Partitioning



-1

-2

-1

1

0

0

0

2

0

0

1

-1

-1

-2

FM Partitioning



-1

-2

-1

1

-2

-2

0

1

-1

-1

-2

-2

0

0

FM Partitioning



-1

-2

-1

1

0

-2

-2 0

0

1

-1

-1

-2

-2

FM Partitioning



-1

-2

-1 1

0

-2

-2 0

0

1

-1

-1

-2

-2

FM Partitioning



-1

-2

1 -1

0

-2

-2 0

-2

-1

-1

-1

-2

-2

FM Partitioning



-1

-2

1 -1

0

-2

-2 0

-2

-1 -1

-2

-2

-1

FM Partitioning



-1

-2

1 -1

-2

-2

-2

0

-2

-1

1

-1

-2

-2

FM Partitioning



-1

-2

1

-1

-2

-2

-2

0

-2

-1

1

-1

-2

-2

FM Partitioning



-1

-2

-1

-3

-2

-2

-2

0

-2

-1

1

-1

-2

-2

FM Partitioning



-1

-2

-3

-2

-2

-2

0

-2

-1

1

-1

-2

-2

-1

FM Partitioning



-1

-2

-3

-2

-2

-2

-2

-2

-1

-1

-1

-2

-2

-1

FM Partitioning


Partitioning: Multi-Level Technique



Multi-Level Partitioning



Coarsening Phase Edge Coarsening

Hyper-edge Coarsening (HEC)

Modified Hyperedge Coarsening (MHEC)


Introduction to Floorplan



Hierarchical Design

Several blocks after partitioning:

Need to: – Put the blocks together – Design each block

Which step to go first?

900

3000

4000

9000

5000



Hierarchical Design

How to put the blocks together without knowing their shapes and the positions of the I/O pins?

If we design the blocks first, those blocks may not be able to form a tight packing



Floorplanning

The floorplanning problem is to plan the positions and shapes of the modules at the beginning of the design cycle to optimize the circuit performance… – chip area – total wirelength – delay of critical path – routability – others, ex: noise, heat dissipation, …



Floorplanning vs. Placement

Both determines block positions to optimize the circuit performance.

Floorplanning: – Details like shapes of blocks, I/O pin positions,

etc. are not yet fixed (blocks with flexible shape are called soft blocks)

Placement: – Details like module shapes and I/O pin positions

are fixed (blocks with no flexibility in shape are called hard blocks)



Floorplanning Problem

Input: – n Blocks with areas A1, ... , An

– Bounds ri and si on the aspect ratio of block Bi

Output: – Coordinates (xi, yi), width wi and height hi for each

block such that hi wi = Ai and ri ≤ hi/wi ≤ si Objective:

– To optimize the circuit performance



Bounds on Aspect Ratios

If there is no bound on the aspect ratios, can we pack everything tightly?

Sure!

But we don’t want to layout blocks as long strips, so we require ri ≤ hi/wi ≤ si for each i



Bounds on Aspect Ratios

We can also allow several shapes for soft blocks:

For hard blocks, the orientations can be changed:



Dead space

Dead space is the space that is wasted:

Minimizing area is the same as minimizing dead space Dead space percentage is computed as

(A - ΣiAi) / A × 100%

Dead space



Slicing and Non-Slicing Floorplan

Slicing Floorplan: – One that can be obtained by

repetitively subdividing (slicing) rectangles horizontally or vertically

Non-Slicing Floorplan:

– One that may not be obtained by repetitively subdividing alone

Otten (LSSS-82) pointed out that

slicing floorplans are much easier to handle


Introduction to Placement



Problem formulation Input:

– Blocks (standard cells and macros) B1, ... , Bn

– Shapes and Pin Positions for each block Bi

– Nets N1, ... , Nm Output:

– Coordinates (xi , yi ) for block Bi. – No overlaps between blocks – The total wire length is minimized – The area of the resulting block is minimized or given a fixed

die Other consideration: timing, routability, clock, buffering and

interaction with physical synthesis



Different Wire Length



Different Routability/Chip Area



Optimal Relative Order

A B C



To spread ...

A B C



.. or not to spread

A B C



Place to the left

A B C



… or to the right

A B C



Optimal Relative Order

A B C

Without “free” space the problem is dominated by order



Placement can Make a Difference

MCNC Benchmark circuit e64 (contains 230 4-LUT). Placed to a FPGA

Random Initial Placement

Final Placement

After Detailed Routing



Importance of Placement Placement is a fundamental problem for physical design Glue of the physical synthesis Becomes very active again in recent years:

– Many new academic placers for WL min since 2000 – Many other publications to handle timing, routability, etc.

Reasons: – Serious interconnect issues (delay, routability, noise) in

deep-submicron design • Placement determines interconnect to the first order • Need placement information even in early design stages

(ex: logic synthesis) – Placement problem becomes significantly larger – Cong et al. [ASPDAC-03, ISPD-03, ICCAD-03] point out

that existing placers are far from optimal, not scalable, and not stable



Design Types ASICs

– Lots of fixed I/Os, few macros, millions of standard cells – Placement densities : 40-80% (IBM) – Flat and hierarchical designs

SoCs – Many more macro blocks, cores – Datapaths + control logic – Can have very low placement densities : < 40%

Micro-Processor (µP) Random Logic Macros(RLM) – Hierarchical partitions are placement instances (5-30K) – High placement densities : 80%-98% (low whitespace) – Many fixed I/Os, relatively few standard cells



Placement Footprints

Standard Cell

Data Path

IP - Floorplanning



Placement Footprints

Core

Control IO

Reserved areas

Mixed data path & sea of gates



I/O Impacts Placement Perimeter I/O

Area I/O



Unconstrained Placement



Floorplanned Placement



VLSI Global Placement Examples

bad placement good placement



Major Placement Techniques Simulated Annealing

– Timberwolf package [JSSC-85, DAC-86] – Dragon [ICCAD-00]

Partitioning-based Placement – Capo [DAC-00] – Fengshui [DAC-2001]

Analytical Placement – Gordian [TCAD-91] – Kraftwerk [DAC-98] – FastPlace [ISPD-04]

Hall’s Quadratic Placement Genetic Algorithm



A down-to-the-earth method Clustering (Select unplaced components and place them)

– SELECT: choose unplaced component that is most strongly connected to all (or any single) of the placed component

– PLACE: place the selected component at a slot such that a certain “cost” of the partial placement is minimized

– Simple and fast: ideal for initial placement



Recap of Partitioning

Objective: – Given a set of interconnected blocks, produce

two sets that are of equal size, and such that the number of nets connecting the two sets is minimized.



Algorithm list_of_sets = entire_chip; while(any_set_has_2_or_more_objects(list_of_sets)) {

for_each_set_in(list_of_sets) {

partition_it(); } /* each time through this loop, the number of */ /* sets in the list doubles. */

}

Initial Random Placement After Cut 1 After Cut 2



An Example

Circuit

Placement

Cutline



Quadrature Placement Procedure

Very suitable for circuits with high routing density in the center

1

2

3a

3b

4a 4b



Bisection Placement Procedure

Good for standard-cell placement

1

4

2a

2b

5a 5b

3a

3b

3c

3d

6a 6b 6c 6d



Outline

Wire length driven placement Main methods

– Simulated Annealing – Partition-based methods – Analytical methods

• Quadratic placement with Gordian-type method

• Force-directed method – Timing, congestion and other considerations

Global placement (rough location) Detailed placement (legalization)



Analytical Placement

Write down the placement problem as an analytical mathematical problem

Solve the placement problem directly Example:

– Sum of squared wire length is quadratic in the cell coordinates.

– So the wire length minimization problem can be formulated as a quadratic program.

– It can be proved that the quadratic program is convex, hence polynomial time solvable



Toy Example

x=100 x=200

x1 x2



Toy Example Interpretation of matrices A and B: The diagonal values A[i,i] correspond to the number of connections to xi The off diagonal values A[i,j] are -1 if object i is connected to object j, 0 otherwise The values B[i] correspond to the sum of the locations of fixed objects connected to object i

x=100 x=200

x1 x2



Solution of the Original QP



Partitioning

Find a good cut direction and position

Improve the cut value using FM



Applying the Idea Recursively Before every level of partitioning, do the Global Optimization

again with additional constraints that the center of gravities should be in the center of regions

Always solve a single QP (i.e., global)

Center of Gravities



Linear vs. Quadratic Objective Function

Differences between linear and quadratic objective function

A B C fixed movable fixed

α

β γ

A B C fixed fixed movable

γ

a) Quadratic objective function

b) Linear objective function



Linear vs. Quadratic Objective Function

Quadratic objective function tends to make very long net shorter than linear objective function does, and let short nets become slightly longer

row1

row2

row3

row4

row1

row2

row3

row4

A

B

A

B

Linear objective function Quadratic objective function



Force Directed Approach

Transform the placement problem to the classical mechanics problem of a system of objects attached to springs

Analogies: – Module (Block/Cell/Gate) = Object – Net = Spring – Net weight = Spring constant – Optimal placement = Equilibrium configuration



An Example

Resultant Force



Force Calculation

Hooke’s Law: – Force = Spring Constant × Distance

Can consider forces in x- and y-direction separately:

)(F

)(F

)()(F

Cost Net

)()( Distance

y

x

22

22

ijij

ijij

ijijij

ij

ijijij

yycxxc

yyxxc

c

yyxxd

−=

−=

−+−=

−+−=

(xi, yi)

(xj, yj)

F Fx

Fy



Timing Analysis

PO1

PO2

PO3

PI1

PI2

PI3

1

3

1

4

6

44

6

6

5

5

7

4

netlist with delay for each gate

arrival times

PO1

PO2

PO3

PI1

PI2

PI3

1

3

1

4

6

44

6

6

5

5

7

4

0

0

0

1

3

1

7

9

7

7

13

15

14

18

22

18



Timing Analysis

PO1

PO2

PO3

PI1

PI2

PI3

1

3

1

4

6

44

6

6

5

5

7

4

arrival time/required time

PO1

PO2

PO3

PI1

PI2

PI3

1

3

1

4

6

44

6

6

5

5

7

4

slack = required time - arrival time

4

0

8

4

0

8

2

0

8

6

2

0

4

4

0

4

0/4

0/0

0/8

1/5

3/3

1/9

7/9

9/9

7/15

7/13

13/15

15/15

14/18

18/22

22/22

18/22


Introduction to Routing



Routing in Design Flow

A C

B

Netlist

Routing AND

INV

Floorplan/Placement

OR



The Routing Problem Apply it after floorplanning/placement Input:

– Netlist – Timing budget for, typically, critical nets – Locations of blocks and pins

Output: – Geometric layouts of all nets

Objective: – Minimize the total wire length, the number of vias, or just

completing all connections without increasing the chip area. – Each net meets its timing budget



The Routing Constraints Examples:

– Placement constraint – Number of routing layers – Delay constraint – Meet all geometrical constraints (design rules) – Physical/Electrical/Manufacturing constraints:

• Crosstalk • Process variations, yield, or lithography issues?



Steiner Tree For a multi-terminal net, we can construct a spanning tree to

connect all the terminals together – The wire length will be large

Better use Steiner Tree: – A tree connecting all terminals and some additional nodes

(Steiner nodes) Rectilinear Steiner Tree:

– Steiner tree in which all the edges run horizontally and vertically

Steiner node



Routing Problem is Very Hard Minimum Spanning Tree Problem:

– Use Prim’s or Kruskal Algorithm – This is a P problem. Easy!

Minimum Steiner Tree Problem:

– Given a net, find the Steiner tree with the minimum length – This problem is NP-Complete!

May need to route tens of thousands of nets simultaneously

without overlapping Obstacles may exist in the routing region



General Routing Paradigm

Two phases:


Global Routing

Global routing is divided into 3 phases: 1. Region definition 2. Region assignment 3. Pin assignment to routing regions



Region Definition

Switchbox

Channel

Divide the routing area into routing regions of simple shape (rectangular): – Channel: Pins on 2 opposite sides – 2-D Switchbox: Pins on 4 sides – 3-D Switchbox: Pins on all 6 sides



Routing Regions



Routing Regions in Different Design Styles

Gate-Array Standard-Cell Full-Custom

Feedthrough Cell



Region Assignment

Assign routing regions to each net. Need to consider timing budget of nets and routing

congestion of the regions



Graph Modeling of Routing Regions

Grid Graph Modeling Checker Board Graph Modeling Channel Intersection Graph Modeling



Grid Graph

A terminal A node with terminals



Checker Board Graph

A terminal

1 1 1

1 1

1 1 1

2 2

A node with terminals

capacity



Channel Intersection Graph

A terminal A node with terminals

Routings along the channels


Maze Routing



Maze Routing Problem

Given: – A planar rectangular grid graph – Two points S and T on the graph – Obstacles modeled as blocked vertices

Objective: – Find the shortest path connecting S and T

This technique can be used in global or detailed routing (switchbox) problems



Grid Graph

X

X

Area Routing Grid Graph (Maze)

S

T

S

T

S

T X

Simplified Representation

X



Maze Routing

S

T



Basic Idea

A Breadth-First Search (BFS) of the grid graph Always find the shortest path possible Consists of two phases:

– Wave Propagation – Retrace



An Illustration

S

T

0 1

1

2

2

4

4 6

3

3

3

5

5 5



Wave Propagation

At step k, all vertices at Manhattan-distance k from S are labeled with k

A Propagation List (FIFO) is used to keep track of the vertices to be considered next

S

T

0 S

T

0 1 2

1 2

3 4 5

4 5 6

3

3 S

T

0 1 2

1 2

3

3

3

5 After Step 0 After Step 3 After Step 6



Retrace

Trace back the actual route Starting from T At vertex with k, go to any vertex with label k-1

S

T

0 1 2

1 2

3 4 5

4 5 6

3

3

5 Final labeling



How many grids visited using Lee’s algorithm?

S

T

1 1

1 1 2

2 2 2

2 2 3

3 3

3 3

3 3

3 4

4 4

4 4

4 4 5 5

5 5

5

5 5

5 5 6

6 6

6 6

6

6 6

6 6

6 6

6 6 7

7 7 7

7 7

7

7 7

7 7 7

7 7

7 7

7 8

8 8

8 8

8 8

8 8

8 8

8

8 8 9

9 9

9 9

9 9 9

9 9

9 9

9

9 9

9 9

9 10 10

10 10

10 10

10 10

10 10

10 10

10 10

10

10 10

10 10

11 11

11

11 11

11 11 11

11 11

11 11

11 11

11

11 11 12 12

12

12 12

12 12 12

12

12 12

12 12

12 12

12 13

13 13

13 13

13 13

13 13

13 13

13

13



Time and Space Complexity

For a grid structure of size w × h: – Time per net = O(wh) – Space = O(wh log wh) (O(log wh) bits are

needed to store each label.) For a 4000 × 4000 grid structure:

– 24 bits per label – Total 48 Mbytes of memory!



Multi-Terminal Nets

For a k-terminal net, connect the k terminals using a rectilinear Steiner tree with the shortest wire length on the maze

This problem is NP-Complete Just want to find some good heuristics



Multi-Terminal Nets

This problem can be solved by extending the Lee’s algorithm: – Connect one terminal at a time, or – Search for several targets simultaneously, or – Propagate wave fronts from several different

sources simultaneously



Extension to Multi-Terminal Nets

S

T

0 1 2

2

3

3

3 T

T 2 2 2

1 1 1

1st Iteration 2nd Iteration

0 0 0 0 S S S S



Maze Routing for Multi-Terminal Nets



Steiner Tree Based Algorithms

For multi-terminal nets Find Steiner tree instead of shortest path Construct a Steiner tree from the minimum spanning

trees (MST)


Channel Routing



Channel Routing Terminology

Upper boundary

Lower boundary

Tracks

Terminals Via

Trunks Branches

Dogleg



Routing Layer Models

HV model VH model

HVH model VHV model

Layer 1

Layer 2

Layer 3

Via

1 layer

2 layers

3 layers



Channel Routing Problem

1 3 0 0 2 1 1 0

3 0 1 2 0 3 0 0

Example: (13002110) (30120300) where 0 = no terminal



Constraint Graphs

0 1 6 1 2 3 5

6 3 5 4 0 2 4

Horizontal constraint graph

1 2

3 4

5

6

0 1 6 1 2 3 5

6 3 5 4 0 2 4

1 2 3

5 4 6

Vertical constraint graph

1

2

3 4

5

6



Constrained Left-edge Algorithm

0 1 6 1 2 3 5

6 3 5 4 0 2 4

4 5

0 1 6 1 2 3 5

6 3 5 4 0 2 4

1

2

3 5

4

6

1. Sort the left end points 2. Place nets greedily 0 1 6 1 2 3 5

6 3 5 4 0 2 4

VCG 1

2

3 4

5

6

6 2 3 1


Clock and Power Routing



Clock Trees

A path from the clock source to clock sinks

Clock Source

FF FF FF FF FF FF FF FF FF FF



An Example of MMM

centers of mass



DME:



Non-tree: Spine & Mesh

Applied in Pentium processor

Spines

Clock sinks or local sub-networks



Applied in IBM microprocessor Very effective, huge wire [Restle et. al, JSSC’01]

[Su et. al, ICCAD’01]

[Kurd et. al. JSSC’01]



P/G Routing Main Objectives

Routing resource – Need to balance the routing resource for P/G,

clock and signals Voltage drop

– Static (IR) and dynamic (L di/dt) voltage drops – More voltage drop means more gate delay – Usually less than 5-10% voltage drop is allowed – So you may need to size P/G wires accordingly

Electrical migration – Too big current may cause EMI problem

Others…



P/G Mesh (Grid Distribution) Power/Ground mesh will allow multiple paths from P/G sources

to destinations – Less series resistance – Hierarchical power and ground meshes from upper metal

layers to lower metal layers • All the way to M1 or M2 (stand cells)

– Connection of lower layer layout/cells to the grid is through vias



Using Two Metal Layers

One 2D-grid for VDD and another one for GND

VDD GND

M5 M4



Gate Array & Standard Cell Design

Inter-weaved combs

VDD GND


Emerging Topics



3D Integration

Heterogeneous integration Form factor

Architecture EDA Process / manufacture



Multi-core Integration

Parallel / distributed Heterogeneous / homogeneous Cache architecture Power / thermal Communication protocol



ESL Design

ESL – Electronic system level – C/C++ – Matlab – SystemC

Architectural synthesis Design space exploration



On-chip Communication

NoC – Network on a chip Multi-cycle communication



Reliability

Noise – IR drop – Ground bounce – Crosstalk – Decoupling capacitance

Aging



Manufacturing

Lithography – OPC – Optical proximity correction

OCV - On-chip variation (process variation) CAA – Critical area analysis

DFM – Design for manufacturing DFY – Design for yield

– Random yield – Systematic yield – Parametric yield



Design Bugs and Errors

Verification Testing

– Power – Speed – Coverage

Fault diagnosis Soft error



Engineering Change Order

ECO – Engineering change order – Metal-only – Spare cell



Reconfigurability

FPGA Reconfigurable hardware Adaptive architecture



Design Styles

Complexity of VLSI circuits

Full custom

Performance Size Cost Market time

Standard Cell Gate Array FPGA

Different design styles

Cost, Flexibility, Performance



Full Custom Design Style Pad Metal Via Metal 2

I/O Data Path

ROM/RAM

PLA

A/D Converter Random logic



Standard Cell Design Style VDD Metal 1

Cell Metal 2

Feedthrough GND

D C C B

A C C

D C D B

C C C B

Cell A

Cell C

Cell B

Cell D Feedthrough cell



Gate Array Design Style

A

B

C

A

B C

VDD Metal1 Metal2

Structured ASIC is essentially gate array



FPGA Design Style



Software Design Flow



VLSI Design Cycle

System Specification

Functional Design

Logic Design

Circuit Design

X=(AB*CD)+(A+D)+(A(B+C))

Y=(A(B+C))+AC+D+A(BC+D))



VLSI Design Cycle (cont.)

Physical Design

Fabrication

Packaging



Design of Integrated Systems

System Level

Register Transfer Level

Gate Level

Transistor Level

Layout Level

Mask Level



Resource

Official, lots of useful information for paper search and citation – IEEE Xplore: http://ieeexplore.ieee.org/ – ACM Digital Library: http://www.acm.org/dl/

GSRC Bookshelf – http://vlsicad.eecs.umich.edu/BK/Slots/

ITRS – Int’l Technology Roadmap for Semiconductor – http://www.itrs.net/reports.html



Resource

Please check the web site for a set of reference, papers and links (will be updated frequently) – EE Times (www.eetimes.com) for recent

trend/development Unofficial, but lots of useful information for paper

search and citation – http://citeseer.com/ – Google Scholar

MIT OpenCourseWare – If you need to make up some knowledge

(Cormen’s algorithm) – http://ocw.mit.edu/index.html



VLSI/CAD Conferences

DAC: Design Automation Conference ICCAD: Int'l Conference on Computer-Aided Design DATE: Design Automation and Test in Europe ASP-DAC: Asia and South Pacific DAC ISPD: Int'l Symposium on Physical Design ISCAS: Int'l Symposium on Circuits and Systems IWLS: Int'l Workshop on Logic Synthesis ISQED: Int'l Symposium on Quality Electronic

Design ISLPED: Int'l Symposium on Low Power Electronics

and Design



VLSI/CAD Conferences

ISCA: Int'l Symposium on Computer Architecture HPCA: Int'l Symposium on High Performance

Computer Architecture Micro: Int'l Symposium on Microarchitecture CODES+ISSS: Int'l Conference on

Hardware/Software Codesign & System Synthesis CASES: Int'l Conf on Compilers, Architecture, &

Synthesis for Embedded Systems



VLSI/CAD Related Journals

IEEE TCAD – IEEE Transactions on CAD of Integrated Circuits

and Systems ACM TODAES

– ACM Transactions on Design Automation of Electronic Systems

IEEE TVLSI – IEEE Transactions on VLSI Systems

Integration, the VLSI Journal IEEE TCAS (I and II)

– IEEE Transactions on Circuits and Systems


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