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Circuit Simulation and Analysis with HSPICE

國研院國家晶片系統設計中心July - 2005

林棋勝

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Ideal想法

Design設計

ROM DSP

I/OA/D

Vin

GND

Vref

D1

D4

Sign

ENB

A/D Converter

D

Q

QSET

CLR

Fabrication製作

Testing測試

Product產品

Product Development Process

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Circuit Design Background

Circuit/System Design :

A procedure to construct a physical structure which is based on

a set of basic component, and the constructed structure will

provide a desired function at specified time/ time interval under a

given working condition.

To be DefinedInput Stimuli Output Response

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FoundryManufacturing

?

Simulation : To predict the Circuit/System Characteristic after manufacturing

Depends on the component behavior, simulation categories include :

Complexity Capacity• Functional simulation• Logic/Gate Level Simulation• Switch/Transistor Level Simulation• Circuit Simulation• Device Simulation

What is Simulation

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Circuit Simulation Background

Physical Structure

Electrical characteristic

I

V

modeling

Circuit Simulation

Tool

f

gain

Behavior

+-

IN+

IN-

OUT

Circuit Structure

OUT

IN

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An Inverter Gate Circuit Design

* The file name : INV.sp

.lib ‘./rf018.l' TT

MP1 VDD IN OUT VDD pch w=2u l=0.18uMN1 GND IN OUT GND nch w=1u l=0.18u

VDD VDD 0 DC 1.8VVIN IN 0 pulse(0V 1.8V 0n 0.1n 0.1n 1n 2n)

.OP

.TRAN 0.1n 4n

.OPTIONS POST

.END

VDD

MP1

GND

IN OUT

MN1

Type “ hspice INV.sp ” to simulate inverter circuit

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Simulation Results of the Inverter

Type “ awaves & “ to view the simulation waveforms

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Schematic and Layout Views of the Inverter

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A 2-Input NAND Gate Circuit Design

* The file name : NAND2.sp

.lib ‘./rf018.l' TT

MP1 VDD A OUT VDD pch w=2u l=0.18uMP2 VDD B OUT VDD pch w=2u l=0.18u MN1 NET1 A OUT GND nch w=2u l=0.18u MN2 GND B NET1 GND nch w=2u l=0.18u

VDD VDD 0 DC 1.8VVA A 0 pulse(0V 1.8V 0n 0.1n 0.1n 1n 2n)VB B 0 pulse(0V 1.8V 0n 0.1n 0.1n 2n 4n)

.OP

.TRAN 0.1n 4n

.OPTIONS POST

.END

VDD

GND

A

OUT

B

MP1 MP2

MN2

MN1

NET1

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Simulation Results ofthe 2-input NAND

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Schematic and Layout Views of the 2-input NAND

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A 2-Input NOR Gate Circuit Design

• How to design a 2-input NOR Gate Circuit ?

* The file name : NOR2.sp

.lib ‘./rf018.l' TT

. . . .

VDD VDD 0 DC 1.8VVA A 0 pulse(0V 1.8V 0n 0.1n 0.1n 1n 2n)VB B 0 pulse(0V 1.8V 0n 0.1n 0.1n 2n 4n)

.OP

.TRAN 0.1n 4n

.OPTIONS POST

.END

VDD

GND

OUT

B

MN1 MN2

MP1

MP2

NET1

A

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Simulation Results ofthe 2-input NOR

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Schematic and Layout Views of the 2-input NOR

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Lab

• A 3-input NAND Gate Circuit Design

• A 3-input NOR Gate Circuit Design

CBAOUT

CBAOUT

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A layout diagram of Memory Circuit

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9

1026

27

43

44 60

68

61

13:1

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A Micrograph of Memory Chip