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Recursively Partitioned Static IP Router Table

Department of Computer Science and Information Engineering National Cheng Kung University, Taiwan R.O.C.

Authors ： Wencheng Lu, Sartaj Sahni

Publisher ： ISCC 2007

Present ： Kuang-Ying Ho 何冠穎

Date ： 2007/11/06(Tue.)

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Introduction

A method–recursive partitioning–to partition a static IP router table so that when each partition is represented using a base structure such as a multibit trie (MST) or a hybrid shape shifting trie (HSST).

Reduce both

Total memory required for router table.

Number of memory access.

Compare with popular front-end table methed.

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*Shape Shifting Trie

K: node size in STT

SBM Shape Bitmap 2K bit

IBM Internal Bitmap

(valid bit)

K bits

EBM External Bitmap (exit point)

K+1 bits

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Recursive Partitioning

R s : 3 R

First-level partitions of Tpartition L(R)the auxiliary partition

s : stride, 1 ≤ s ≤ T.height+1

s : 2

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Q(N) : bit stringIndex of ST(N)

Data structure

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Hash table - Entry types

R s : 2

For first levels : stride

ht : address of first hash table entry

h : perfect hash function

d : destination IP

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Lookup

q u

Incorporating Leaf Pushing

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R

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Lookup after leaf pushing

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Dynamic Programming Recurrence

B(N, l, r) be the minimum memory required to represent levels 0 through l of the subtree of T rooted at N by a base structure such as MBT or HSST take no more than r memory accesses.

H(N, l) be the memory required for a stride l hash table for the paths from node N of T to nodes in Dl(N)

C(N, l, r) be the minimum memory required by a recursively partitioned representation of the subtrie defined by levels 0 through l of ST(N).

r = 4, 5 0 < l ≤ N.height N

N

Q

N.height

l

Recurrences for B may be obtained from Sahni and Kim [12] for fixed- and variable-stride MBTs and Lu and Sahni [6] for HSSTs.

Optimization

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A. when auxiliary partitions L(R) are restricted to be resented by base structures, the memory requirement is reduced.

B. either a hash table or a simple array with 2l entries can be use when the partition stride is l.

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Implementation

For benchmarking purposes we assumed that the router table will reside on a QDRII SRAM (dual burst), which supports the retrieval of 72 bits of data with a single memory access. We considered two hash-table designs–36 bit and 72 bit.

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Implementation for IPv4

In the 36-bit design for IPv4, we allocated 36 bits to each hash entry with: 8 bits for Q(N), 2 bits for the stride of the next-level partition (5-8), 8 bits for the mask, 17 bits for the pointer.

In the 72-bit design for IPv4, we allocated 72 bits for each hash-table entry with17 bits for Q(N), 5 bits for the stride of the next-level partition (1-17),17 bits for the mask,19 bits for the pointer

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Implementation for IPv6

In the 36-bit design for IPv6, we allocated 36 bits to each hash entry with: 7 bits for Q(N), 2 bits for the stride of the next-level partition (4-7), 7 bits for the mask, 19 bits for the pointer.

In the 72-bit design for IPv6, we allocated 72 bits for each hash-table entry with17 bits for Q(N), 5 bits for the stride of the next-level partition (1-17),17 bits for the mask,19 bits for the pointer

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Performance for IPv4

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Performance for IPv6

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Contributions