16+ +ee109+dld+ +ch5 synchronous logic

8/13/2019 16+ +EE109+DLD+ +Ch5 Synchronous Logic

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Synchronous Logic

ECE 223

Digital Circuits and Systems


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Sequential Circuits

Combinational circuits

Output = f (present inputs)

Sequential circuits

Output = f (present inputs and past inputs)

Circuit remembers past history

Must contain memory

inputs k n outputs

present state next state

combinational

circuit

memorym m

state


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Synchronous Sequential Circuits

A synchronizing, periodic signal, Clock, facilitates

the transition from present state to next state

Memory is provided by flip-flops


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SR (Set Reset) Latches

NOR Latch

SR = 11 is avoided

Outputs are not complementary Input transition from 11 00 may cause circuit to: (i) fall

into either state, or become meta-stable


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SR (Set Reset) Latches

NAND Latch

SR = 00 is avoided

Outputs are not complementary Input transition from 00 11 may cause circuit to: (i) fall

into either state, or become meta-stable


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SR Latch with control Input

C = 0 Latch retains its state

C = 1 Allows propagation of SR inputs


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Data (D) Latch

Data latch eliminate, the need for complementaryinputs

Outputs are also complementary


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Flip-flop

Latch Is level sensitive to the control signal

Multiple data transition may cause problem while C =1

Flip-flop is edge triggered Flip-flop samples the data on Clock transition


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Edge Triggered Flip-flop

Efficient implementation

Multiple data transitions do not affect the output


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J-K Flip-flop

Versatile flip-flop

Can be Set, Reset, or Complement (toggle) its output


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J-K Flip-flop

Qn+1 = JQn + KQn = D

JK

Qn

00 01 11 10

0 1 1

1 1 1

Qn+1

J K Qn Qn+1

0 0 0 0

0 0 1 1

0 1 0 00 1 1 0

1 0 0 1

1 0 1 1

1 1 0 11 1 1 0


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Asynchronous Inputs

Ability to Reset (or Set)

irrespective of Clock

state Often needed in

computation


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State Table

Present State Input Next State Output

A

0

0

0

0

1

1

1

1

1 1 1 1 0

0 0 0 0 1

0 1 1 0 0

1 0 0 0 1

1 1 1 0 0

B x A B y

0 0

0

0

0

00

1 0

0 11

0

1

0


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Analysis with JK Flip-flop

JA = B, KA = Bx

JB = x KB = Ax + Ax = Ax


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State Table

Present State Input Next State Flip-flop Inputs

A JA KA JB

0 0

0

1

1

0

0

1

1

0

10

0

1

0

0

0

0

1

0

1

0

1

0

1

0

1

1

1

0 01

1 1 1 0 1

0 0 1 1 1

0 1 1 0 0

1 0 0 0 1

1 1 1 1 0

B x A B KB

0 0

0

1

0

01

0 1

1 01

0

1

0

A(t+1) = JA + KA

B(t+1) = JB + KB


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State Diagram


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Analysis with Toggle Flip-flop

The Characteristic EquationQ(t+1) = TQ

= TQ + TQ


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Analysis with Toggle Flip-flop

Present

State

Input Next State Output

A B y

01

1

0

0

1

1

0

00

0

0

0

0

1

1

00

0

1

1

1

1

0

A

00

0

0

1

1

1

B x

1

1 1

0 0

0 1

1 0

1 1

000 1

01


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Mealy and Moore Models (Machine)

Most general model of a sequential circuit has inputs,outputs, and internal states

Two different models (i) Mealy model, (ii) Moore Model

Difference is how output is generatedMealy Model Output is a function of present state & input

Moore Model Output is only a function of present state


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Mealy Machine

Observation

Output can change asynchronous to the clock

The output delay with respect to clock is unpredictable

Difficult to do the timing analysis


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Moore Machine

Observation

Output changes synchronously to the clock

The output delay with respect to clock is predictable

Easier timing analysis

inputs

outputs

combinatorialcircuit

flip-flops

currentstate

clock

next statefunction

combinatorialcircuit


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State Reduction

Sequential circuit analysis Circuit diagram state table (or state diagram)

Sequential circuit design

State diagram (state table) circuit diagram

Redundant state may exist in a state diagram (or table)

By eliminating them reduce the # of logic gates and flip-flops

Two states are equivalent if for each member of the set of inputs,they give exactly same state or an equivalent state

When two states are equivalent, one of them can be removed


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State Reduction - Example

PresentState

Next State Output

X=0 X=1

C

E

A

D

B

1

0

1

0

0

D

A

D

B

C

A

B

C

D

E

A/1 C/1 P/1

D/0 D/0

Q/0E/0B/0

0

0 0

0

0

0

0 0

1

1

1

1

1

1

1

1

0QPQ (B,E)

0DQD

P

X=1

1

Output

D

X=0

Next State

P (A,C)

Present

State


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State Reduction Home Work

Reduced the shown state

diagram

(Page 199 in the text book)


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State Assignment

States must be assigned

coded binary values

In order to realize withphysical components

Present

State

Next

State

Output

X=0 X=1 X=0

b 0

0

00

0

d

dd

d

X=1

0

0

01

1

a

c

ae

a

a

b

cd

e

State Assignment 1

Binary

Assignment 2

Gray code

Assignment 3

One-hot

ab

c

d

e

00001000000001

010

00010

011

001

011

010

00100

100 110

01000

10000


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Synthesis using D Flip-flops

Given the state diagram, design the circuit using D flip-flops

Present

State

Input Next State Output

A B y

0

1

0

0

0

1

01

0

0

0

0

0

0

11

0

0

0

1

0

1

01

A

0

0

0

0

1

1

1

B x

1

1 1

0 0

0 1

1 01 1

00

0 1

01


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0100

0

1

Bx

A 11 10

1

1 1

0100

0

1

Bx

A 11 10

1

1 1

0100

0

1

Bx

A 11 10

11

DA = Ax + Bx DB = Ax + Bx y = AB


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S th i i JK Fli fl


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Synthesis using JK Flip-flop

Given the state table, design the circuit using JK flip-flops

Present

State

Input Next State Flip-flop Inputs

A B JA KA JB

0 0

0

1

0

X

X

X

X

1

0X

X

X

X

0

0

0

0

1

X

X

0

1

X

1

0

1

1

1 X0

KB

X

X

1

0

X

X

0

1

0

0

1

0

1

1

1

0

A

0

0

0

0

1

1

1

B x

1

1 1

0 0

0 1

1 0

1 1

00

0 1

01


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S th i i JK Fli fl


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Synthesis using JK Flip-flop


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16+ +ee109+dld+ +ch5 synchronous logic

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