dld lecture 7

Upload: muhammad-ali

Post on 07-Apr-2018

229 views

Category:

Documents


0 download

TRANSCRIPT

  • 8/6/2019 DLD lecture 7

    1/11

    Registers and Counters

  • 8/6/2019 DLD lecture 7

    2/11

  • 8/6/2019 DLD lecture 7

    3/11

    A simplest possible register is one that consists of

    only flip flops without any external gates.

  • 8/6/2019 DLD lecture 7

    4/11

    Register with Parallel Load

    The load inputcontrols theoperation of theregister, by decidingon w c c oc

    pulses, data wouldload in register.

    When Load =0, bothR and S are zeroan no c ange ostate occurs withany clock pulse.

    When Load=1, bothRand S haverespect ve va uesfrom binary inputsIs and input istransferred intoregister.

    e c ear nput goesto special terminal toall flip flops andmake themasynchronously

    .

  • 8/6/2019 DLD lecture 7

    5/11

  • 8/6/2019 DLD lecture 7

    6/11

  • 8/6/2019 DLD lecture 7

    7/11

  • 8/6/2019 DLD lecture 7

    8/11

  • 8/6/2019 DLD lecture 7

    9/11

  • 8/6/2019 DLD lecture 7

    10/11

  • 8/6/2019 DLD lecture 7

    11/11