2013 06-ohkawa-heart-presen

RECONFIGURABLE AND

HARDWIRED ORB ENGINE ON FPGA

BY JAVA-TO-HDL SYNTHESIZER

FOR REALTIME APPLICATION

Takeshi Ohkawa, Daichi Uetake, Takashi Yokota,

Kanemitsu Ootsu, Takanobu Baba

Utsunomiya University, Japan

2013/6/13 HEART2013 @ Edinburgh, Scotland 1

Tokyo

Utsunomiya

Introduction

• FPGA (Field Programmable Gate Array) has become a

popular and standard platform to implement a desired

logic into a hardwired circuit.

• Problems

• Productivity of designing a complex FPGA system.

• Q) Can you make a whole GUI system like Android in HDL?

• A) I don’t think it is possible…

• Education of FPGA design

• Q) Would you like to use FPGA to accelerate your software?

• A) I am interested in GPGPU by CUDA, but FPGA is not…

• Software engineers want to use FPGAs, too!


Our Proposal:

Platform for networked FPGA design


FPGA

High

performance

IP

High performance

& Massively Parallel

IP Design

by dedicated

Hardware Description

Language (HDL)

Ex.) System Verilog,

Bluespec, etc.

High

performance

IP & I/F

Tight Control of

IP and Interface to

Cloud resource

Ex.) JavaRock, etc.

ORB Engine /

JavaRock

Resource Access on Cloud

Ex.) Database, JavaScript, etc.

Real world / Human Interaction

Proposal Summary

• In order to let software engineers use FPGAs…

• Do not • Educate software engineers to use HDL

• Let them use • High Performance Hardwired IP as a component on

FPGA to accelerate their software

• ORB to control the IP from software • The IP can be controlled by a message from software

through network

• JavaRock to write application specific logic in Java and convert it into HDL which works in FPGA.


What is ORB (Object Request Broker)?

- distributed object approach • Calling mechanism of a software object by a message.

• CORBA specification* defines common wire protocol

(GIOP: General Inter-ORB Protocol) and interface definition

(IDL) independent from programing languages.

• CORBA language mappings and implementations are available

for most of existing programming languages

(C/C++, Objective-C, Java, Python, Perl, Erlang...) FPGA?


Robot-Arm Object

Rotation Angle Detector(Rotary Encoder)

FPGA

A

B

Quad counter

PC

“Hi, Robot-Arm.What is your angle?”

“12.3 degrees”

ORBEngine

* Object Management Group http://www.omg.org/

http://www.omg.org/

http://www.omg.org/

Example GIOP message

(48 bytes) 0x47 0x49 0x4f 0x50 -> “GIOP”, the magic number

0x01 0x00 -> GIOP_version

0x00 -> Byte order (big endian)

0x00 -> Message type (Request message)

0x00 0x00 0x00 0x2c -> Message size (44)

0x00 0x00 0x00 0x00 -> Service context

0x00 0x00 0x00 0x01 -> Request ID

0x01 -> Response expected

0x00 0x00 0x00 0x24 -> Object key length in octets (36)

0xab 0xac 0xab 0x31 0x39 0x36 0x31 0x30

0x30 0x35 0x38 0x31 0x36 0x00 0x5f 0x52

0x6f 0x6f 0x74 0x50 0x4f 0x41 0x00 0x00

0xca 0xfe 0xba 0xbe 0x39 0x47 0xc8 0xf8

0x00 0x00 0x00 0x00 -> Object key defined by vendor

0x00 0x00 0x00 0x04 -> Operation name length (4 octets long)

0x61 0x64 0x64 0x00 -> Value of operation name ("add")

0x00 0x00 0x00 0x01 -> Parameter value (1)

0x00 0x00 0x10 0x00 -> Parameter value (2)

0x00 0x00 0x00 0xff -> Parameter value (3)


1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Example of

IDL (Interface Description Language)

• Communication programs are generated from the IDL

• Client-Stub: Message Generator

• Server-Skeleton: Message Parser)

• Optimized code can be generated for the target application • Cf) Message interpreter approach (Web service, SOAP)

• FPGA may have similar interface to software!

• What are the problems??


interface someCalculation {

long add(in long A, in long B, inout long C);

void anotherMethod(in short param);

};

Sub Problem 1: Latency

- Our previous work “ORB Engine” for FPGA • Software (C language) CORBA implementation on

MicroBlaze soft-core processor in FPGA • Small foot print/ stand alone (12KB)

• http://sourceforge.net/projects/orbe/

• Cf) PC CORBAs need Linux/Windows, huge memory footprint (8MB)

• Round-trip Performance • 1.5ms @ Spartan-3E, 50MHz

• 0.5ms @ Virtex6-LX, 100MHz

• Application • Good for Human Interface

(several 10ms)

• Big overhead for real-time application like robot (around 1ms-10ms)


0

0.5

1

1.5

2

2.5

3

1 2 3 4 5 6 7 8 9 10

Elap

sed

tim

e (m

s)

Method Call

Spartan3E - UDP PacketIn/Out

Virtex6LX - UDP PacketIn/Out

Measured latency of in/out

of UDP CORBA message packet

http://sourceforge.net/projects/orbe/

Sub Problem 2: Design Productivity

How to write object behavior on FPGA?

• Straight forward approach to minimize latency • Hardwired ORB Circuit

• Prismtech Ltd. : Spectra CDB/ICO (IP Core ORB)

• Objective Interface Systems, Inc. : ORBexpress

• Both aims Software Defined Radio (SDR) in FPGA

• Need to write HDL for object behavior

• Our approach • Write object behavior in software.

• Previously C language. In this time Java by JavaRock.


What is JavaRock?

Java-to-HDL synthesizer

• JavaRock is:

• A behavior level synthesis tool, which generates

HDL code from pure Java code.

• JavaRock does not:

• support the entire Java feature; however, a circuit

which behaves as the Java code behaves can be

synthesized with some grammatical limitation.

• Ex.1) method call only with primitive parameters, no

object passing

• Ex.2) floating point is not supported


Example JavaRock code:

Timer class for measurement


1. import net.wasamon.javarock.rt.*;

2.

3. @javarockhdl

4. public class Timer {

5. int counter = 0;

6.

7. @auto

8. public void run() {

9. while(true) {

10. counter++;

11. }

12. }

13.

14. public int getCounter() {

15. return counter;

16. }

17. public void resetCounter() {

18. counter = 0;

19. }

20. }

Remote-control FPGA system overview

using Hardwired ORB Engine/Javarock

• High-Performance IP on an FPGA can be controlled from software written in any programming language


Description

of IDL

Server Skeleton

Generated Java,

HDL by Javarock

Interface

Definition

(.IDL)

Client Stub

Generated Software

(Java/C++/Python)

FPGA Software on Remote System

Code generation

Object behavior

Java,

HDL by Javarock

Client

Application

Server Object

High Performance IP

or Real-world I/F

on FPGA

Message

Communication

ORB Engine

Platform

Application example: Remotely Controlled

FPGA System of Inverted Pendulum

• Example to show the real-time

capability of ORB engine

• Control the inverted pendulum

FPGA system by network

message using ORB engine

• Requirement

• 8.3ms feedback loop (120Hz)


Frame Angle [deg]

(Rotary Encoder)

Rotation

Angular Speed

[deg/sec]

(Gyro Sensor)

Inverted Pendulum Kit

used in the experiment • Product ： Beauto Balancer (Vstone Co., Ltd.)

• Robot kit with separated microcontroller board and

sensor board

• Circuit diagram and the source codes are available

• Microcontroller board： H8/36064G

• Clock Freq.: 14.7456MHz

• Sensor board：

• Gyro sensor to get frame angular speed

• Rotary encoder to get wheel rotation angle


Control Software (C language)

6.9ms (worst)

Sync

Kernel

Initialize

Loop

Start

Control loop 8.3ms (120Hz)

Sensor value input Gyro sensor value

average

Z value controll

Z calibration

Encoder average

Output calc

Overflow check

Irregular detection

PWM output

Start

End

Whole Control Flow

Control kernel


46%

<1%

7%

21%

17%

2%

<1%

7%

Processing Time

FPGA board used in this study • exStick (Developed by e-Trees Japan, Co., Ltd.)

• With UDP/IP IP core and sample design using JavaRock


Microcontroller system FPGA system

Environment Microcontroller

(H8/36064G)

FPGA

(Xilinx Spartan6

XC6SLX16)

Clock Freq. 14.5674MHz 50MHz

Picture of the FPGA system

• The microcontroller

board is replaced with

the FPGA board


FPGA

Board

(exStick,

Spartan6

LX16,

RJ45)

Battery

Sensor board

(Gyro sensor)

Base

board

(ADC,

motor driver)

Motor &

Wheel

Rotary

encoder

FPGA Remote System construction


FPGA board

Gyro

Sensor

& ADC

Rotary

Encoder

Sensor Board

Voltage 0-3.3V

Converted to 12bit value

Phase A H/L=0V/3.3V

PWM

output

UDP

TX

Gyro&

Average

Encoder&

Average

Motor

Driver

Phase B

PWM signal

Direction

Controller

UDP

RX

UDP

TX

Remote PC

UDP

RX

100

Base-

TX

Remote

Controller

Control

Logic

CORBA

protocol

ORBE

server

Java

IDL

Timer

IDL of the inverted pendulum controller


interface InvertedPendulum {

long setSyncPeriod(in short period);

long setPwmPrescaler(in short prescaler);

long setPwmPeriod(in short period);

long setPwmOutput(in short activePeriod, in boolean direction,

out short gyroValue, out short encValue);

};

Java code

For PC client

JavaIDL

(oracle JDK 1.7)

Manual (in this experiment)

Automation (future work)

JavaRock

ORB Engine

Code for

FPGA

Remote Control Sequence


Client

@PC

UDP Packet

Server Object

@FPGA

Time

Packet analysis

Get sensor values

Packet creation

(Synchronization)

Motor output

Packet analysis

Packet creation

Motor output

Calculation

Packet creation UDP Packet

Packet analysis

UDP Packet

Protocol Processing

By ORB Engine

I/O manipulation

On FPGA

RAW Protocol for the Inverted Pendulum

Controller in the experiment • Purpose

• Make comparison to CORBA

• Length: 40-200 bytes

• Measure the processing

overhead

• Communication Protocol

• Acceptable Message Format

• Length: 4 bytes

• Reply Message Format

• Length: 4 bytes


by

te

Field name Description

0 COMMAND 0: Specify PWM Period

1: Specify PWM Active period

2: Specify PWM clk division

3: Specify sync period

1 SIGN Motor Direction 0: +, 1: -

2 PERIOD_H 16 bits Period

3 PERIOD_L

byte Field name Description

0 ADC_H A/D converter 12bit value

(Gyro sensor output) 1 ADC_L

2 ENC_A Encoder Phase A signal (0/1)

3 ENC_B Encoder Phase B signal (0/1)

(a) Acceptable message format

(b) Reply message format

Measured performance of

the synthesized ORB Protocol Engine


0

200

400

600

800

1000

1 2 3 4 5

De

lay

[us]

Remote Calls

ORB (PC)ORB (FPGA)Raw (PC)Raw (FPGA)

• Observations

• ORB engine exhibits a stable performance:

200 microsecond (0.2ms)

• Small overhead compared to RAW protocol (4 Bytes)

• CORBA: 50-200Bytes CORBA protocol message

Remotely-controlled Inverted Pendulum


-6000

-4000

-2000

0

2000

4000

6000

-60

-40

-20

0

20

40

60

1

23

45

67

89

11

1

13

3

15

5

17

7

19

9

22

1

24

3

26

5

28

7

30

9

33

1

35

3

37

5

39

7

Mo

tor

Ou

tpu

t

z (W

he

el a

ngl

e)

and

an

gle

(Fr

ame

) [d

egr

ee

]

Control sequence

z

angle

out

Movie (left) and the measured sensor

values (right) and calculated motor

output

Resource usage of the synthesized

ORB Protocol Engine • FPGA :

• Xilinx Spartan6-LX16

• System clock:

• 50MHz

• Note

• UDP/IP hardwired-IP

core is used

• Comparison

• The hardware

resource overhead :

372 slices


(a) Used Total Ratio (%)

Slice

Registers 3,608 18,224 19.8%

Slice

LUTs 5,648 9,112 62.0%

Occupie

d Slices 1,880 2,278 82.5%

(b) Used Total Ratio (%)

Slice

Registers 4,387 18,224 24.1%

Slice

LUTs 7,820 9,112 85.8%

Occupie

d Slices 2,252 2,278 98.9%

(a) Dedicated Raw Protocol Interface

(b) ORB Engine / CORBA Protocol Processing

Conclusion

• Proposed a platform for networked FPGA system

based on ORB (Object Request Broker) Engine

with JavaRock Java-to-HDL synthesizer.

• To let software engineers use FPGAs easily

• Remotely controlled FPGA system of an inverted

pendulum is designed as an example

• The measurement result of the system

• Latency: below 200us (stable)

• The hardware resource overhead : 372 slices


Future work

• To improve the implementation with smaller

hardware footprint and higher response

time.

• To build an eco-system to support the

parallel and distributed system design of

networked FPGA based on the ORB

architecture.


2013 06-ohkawa-heart-presen

Technology