23970-00 2006 1

" " , : , , MSI/LSI IC , RTL , ASM Chart , , . M. M. Mano and C. R. Kime, Logic and Computer Design Fundamentals, 3rd ed., Prentice-Hall, 2004. J. P. Hayes, Introduction to Digital Logic Design, Addison Wesley, 1993. Grading: Exams & HWs, A(

()1.Digital System: What? Why? How?2.Binary Logic & Gates3.Boolean Algebra: Definition, Theorems4.Boolean Expression: , Logic Diagram5.Map Simplification: Karnaugh Map6.Other Logic Gates7. 8. 9.Combinational Functional Blocks: Encoder, Decoder, Multiplexer, Demultiplexer, Code converter, Adder, Subtractor, Adder/Subtractor, Multiplier,

1. Digital System: What? Why? How?Digital system a system that processes (stores, communicates, transforms/manipulates) information expressed in discrete() form. () general-purpose digital computers, Digital signal signal with discrete meaningful states(values). analog signalDigital over Analog: Reliability() high noise immunityAnalog to Digital: Quantization and Encoding Digital signals for analog information (or signal)? quantization() in both value and time Binary signals for multivalued information? encoding() : BCD code, ASCII code, Excess-3 codeCoding? What to do with that code?

2. BINARY LOGIC & GATES1. Binary Logic (2): - Binary Logic Boolean Algebra Switching algebra, Two-valued Boolean Algebra 2

{, }n{, } {HIGH, LOW}n2 {HIGH, LOW} {ON, OFF}n{ON, OFF} : and, or, notSwitch : , , NC/NO switch

{??, ??}n {??, ??}

????, ????

2. BINARY LOGIC & GATES2. Three Basic Logical Operations 2 , () ? 22 1-bit 2 (Binary Logic) (Binary Digital System) (1-bit Binary Arithmetic)

,

0

1

and

0

1

0

0

0

0

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1

1

0

1

,+

0

1

or

+

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0

1

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1

1

1

1

1

1

10

X

X

not

0

1

1

0

2. BINARY LOGIC & GATES3. (Basic) Logic Gates = 2

X

Y

Z

X

Y

Z

L

L

L

0

0

0

L

H

L

0

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H

L

L

1

0

0

H

H

H

1

1

1

X

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Z

X

Y

Z

L

L

L

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0

0

L

H

H

0

1

1

H

L

H

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H

H

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1

1

X

Z

X

Z

L

H

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1

H

L

1

0

2. BINARY LOGIC & GATES4. Timing Diagram ()

2. BINARY LOGIC & GATES5. (Multiple-Input) Gate 2 AND, 2 OR, NOT gate . (more at 2-6, 2-7)AND, OR gate AND, OR .F = ABC = ((AB)C)F = A+B+C+D+E+F = (((((A+B)+C)+D)+E)+F)

3. BOOLEAN ALGEBRA ()1. Boolean Function F(X,Y,Z) = Boolean Expression = X + YZ

* (Truth Table)* , (Logic Diagram)

* algebraic expression logic diagram* * , () .* Informal Spec. Formal Spec.

X

Y

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F

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3. BOOLEAN ALGEBRA ( )2. Huntington : < V={}, O={+, .} > 1. (a) V is closed with respect to the operation p1. (b) V is closed with respect to the operation p2. 2. (a) V has an identity element w.r.t the operation p1. (b) V has an identity element w.r.t the operation p2. 3. (a) V is commutative w.r.t the operation p1. (b) V is commutative w.r.t the operation p2. 4. (a) p1 is distributive over p2. (b) p2 is distributive over p1. 5. For each x in V, there exists an element y in V such that (a) x + y = 1 (b) x . y = 0 6. |V| 2

3. BOOLEAN ALGEBRA ()3. Basic Identities of Boolean Algebra1) X + 0 = X2) X1 = X(identity) ()3) X + 1 = 14) X0 = 0Identity Theorem 5) X + X = X6) XX = XIdempotence Th. 7) X + X = 18) XX = 0(Complement )9) (X) = XInvolution Th. 10) X + Y = Y + X 11) XY = YX Commutative Law12) X+(Y+Z) = (X+Y)+Z 13) X(YZ) = (XY)Z Associative Law14) X(Y + Z) = XY+ XZ 15) X + YZ = (X+Y)(X+Z) Distributive Law16) (X + Y) = XY 17) (XY) = X + Y De Morgans Th.* ? (inverse)?* (Principles of Duality): ANDOR, 01

3. BOOLEAN ALGEBRA ()4. Algebraic Manipulation ( , )- F = XYZ + XYZ + XZ = XY(Z+Z) + XZ = XY + XZ

3. BOOLEAN ALGEBRA ()5. Other Useful Identities(1) (Absorption Theorem) X + XY = X1 + XY = X(1 + Y) = X X(X + Y) = (X + 0)(X + Y) = X + 0Y = X(2) XY + XY = X(Y + Y) = X1 = X (X + Y)(X + Y) = X + YY = X + 0 = X(3) (Simplification Theorem) X + XY = (X + X)(X + Y) = 1(X + Y) = X + Y X(X + Y) = XX + XY = 0 + XY = XY(4) (Consensus Theorem) XY + XZ + YZ = XY + XZ (X + Y)(X + Z)(Y + Z) = (X + Y)(X + Z)* : ,

4. BOOLEAN EXPRESSION ( )Key Points: , , 1. - (Standard Form): (Sum-of-Products, SOP, or Disjunctive Form) F(X,Y,Z) = XY + XZ + YZ (Product-of-Sums, POS, or Conjunctive Form) F(X,Y,Z) = (X + Y)(X + Z)(Y + Z)- (Non-standard, Factored, or Parenthesized Form) F(X,Y,Z) = X + (Y + Z)(Y + Z)- (Canonical Form): (Canonical SOP, or Canonical Disjunctive Form) F(X,Y,Z) = XYZ + XYZ + XYZ [sum-of-minterms form] (Canonical POS, or Canonical Conjunctive Form) F(X,Y,Z) = (X+Y+Z)(X+Y+Z) [product-of-maxterms form] * .

4. BOOLEAN EXPRESSION ( )* (product term) = ANDing of literals* (sum term) = ORing of literals* = 2 (Two-Level Form)* = (Multi-Level Form)

2. Minterms and Maxterms- minterm(, , standard product) = a product term in which all the variables appear exactly once, either complemented or uncomplemented.- maxterm(, , standard sum) = a sum term in which all the variables appear exactly once, either complemented or uncomplemented.* The order of the variables should be assumed for the symbolic representation of minterms/maxterms.

4. BOOLEAN EXPRESSION ( )Table 2-6 Minterms for Three Variables

X

Y

Z

product terms

symbol

m0

m1

m2

m3

m4

m5

m6

m7

0

0

0

XYZ

m0

1

0

0

0

0

0

0

0

0

0

1

XYZ

m1

0

1

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0

0

0

0

0

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1

0

XYZ

m2

0

0

1

0

0

0

0

0

0

1

1

XYZ

m3

0

0

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1

0

0

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1

0

0

XYZ

m4

0

0

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1

0

0

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1

0

1

XYZ

m5

0

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1

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1

1

0

XYZ

m6

0

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1

XYZ

m7

0

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1

4. BOOLEAN EXPRESSION ( )Table 2-7 Maxterms for Three Variables

X

Y

Z

sum terms

symbol

M0

M1

M2

M3

M4

M5

M6

M7

0

0

0

X+Y+Z

M0

0

1

1

1

1

1

1

1

0

0

1

X+Y+Z

M1

1

0

1

1

1

1

1

1

0

1

0

X+Y+Z

M2

1

1

0

1

1

1

1

1

0

1

1

X+Y+Z

M3

1

1

1

0

1

1

1

1

1

0

0

X+Y+Z

M4

1

1

1

1

0

1

1

1

1

0

1

X+Y+Z

M5

1

1

1

1

1

0

1

1

1

1

0

X+Y+Z

M6

1

1

1

1

1

1

0

1

1

1

1

X+Y+Z

M7

1

1

1

1

1

1

1

0

4. BOOLEAN EXPRESSION ( )3. Canonical Expressions- sum-of-minterms of F and F F(X,Y,Z) = [] + [] + [] + = XYZ + XYZ + XYZ + XYZ = m0 + m2 + m5 + m7 = Sm(0, 2, 5, 7), or S(0, 2, 5, 7)

F(X,Y,Z) = [] + [] + [] + = XYZ + XYZ + XYZ + XYZ = m1 + m3 + m4 + m6 = Sm(1, 3, 4, 6), or S(1, 3, 4, 6)

X

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F

F

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4. BOOLEAN EXPRESSION ( )- product-of-maxterms of F and F F(X,Y,Z) = ()()() = (X+Y+Z)(X+Y+Z)(X+Y+Z)(X+Y+Z) = M1M3M4M6 = PM(1, 3, 4, 6), or P(1, 3, 4, 6) Similarly, F(X,Y,Z) = M0M2M5M7 = P(0, 2, 5, 7) Another method: F(X,Y,Z) = [F(X,Y,Z)] = (m0 + m2 + m5 + m7) = (m0)(m2)(m5)(m7) = M0M2M5M7 = P(0, 2, 5, 7)F() = S(0, 2, 5, 7) = P(1, 3, 4, 6) F() = S(1, 3, 4, 6) = P(0, 2, 5, 7)

X

Y

Z

F

F

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4. BOOLEAN EXPRESSION ( )4. Non-Canonical to Canonical

E = Y + XZ = (X+X)Y(Z+Z) + X(Y+Y)Z = (XY+XY)(Z+Z) + XYZ + XYZ = XYZ + XYZ + XYZ + XYZ + XYZ + XYZ = XYZ + XYZ + XYZ + XYZ + XYZ = S(0, 1, 2, 4, 5)

E = Y + XZ = (Y + X)(Y + Z) = (XX+Y+Z)(X+Y+ZZ) = (X+Y+Z)(X+Y+Z)(X+Y+Z)(X+Y+Z) = P(3, 6, 7)

X

Y

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E

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4. BOOLEAN EXPRESSION ( )5. Sum of Products- sum-of-minterms . obtained directly from a truth table . the most complex sum-of-products form . but, a starting point to a simplified s-o-p form- logic diagram of a s-o-p form? . two-level, AND-OR, implementation . (complements of input variables are assumed to be available)- Non-standard form to SOP form? . by means of the distributive law- SOP to simplified SOP? . many ways . Simplification Th., Consensus Th., Identity Th., .- Figure 2-5, Figure 2-6

4. BOOLEAN EXPRESSION ( )- 2 (Figure 2-6)

6. Product of Sums - Two-level, OR-AND Implementation - Figure 2-7

5. MAP SIMPLIFICATIONWhat to Study: Map method for logic simplification () /1. Simplification Criterion: / ? F = () + () + () + + () (i) with a minimum number of terms (ii) with the fewest possible number of literals* There may be many, equally good expressions!

2. (Algebraic Simplification) f(a, b, c) = abc + abc + abc + abc + abc = ab + ab + abc = a + abc = a + bc

5. MAP SIMPLIFICATIONf(a, b, c) = abc + abc + abc + abc + abc = ab + abc + bc = a(b + bc) + bc = a(b + c) + bc = ab + ac + bc = a(bc) + bc = a + bc f(a, b, c) = abc + abc + abc + abc + abc = abc + abc + abc + abc + abc + abc = ab + ab + bc = a + bc = ???* With proper duplication of product terms, only the distributive law would do the job.

5. MAP SIMPLIFICATION3. Algebraic Simplification: Use any boolean axioms and theorems, or (1) two adjacent product terms into one bigger product term (2) a term may be used more than once during combination (3) a term may be partitioned into smaller onesBut, still we have some difficulties:(1) no specific rules to predict each succeeding step(2) difficult to determine whether the simplest expression has been achieved- Simplify the following expression:f(A,B,C,D) = ABCD + ABCD + ABC + ABCD + ABCD = ABD + ABC + ABCD + ABCD = ?????? = ABC + ABC + BD

5. MAP SIMPLIFICATION4. Karnaugh Map, (K-map, Veitch Diagram)(1) 2 ( )(2) (3) (not for computer-aided design)(4) (not apply directly to simplification in non-standard forms)(5) up to 4 variables? ==> depends on YOU!

* possible to find two or more simplified expressions.

Glue logic

5. MAP SIMPLIFICATION5. 2-, 3-, 4-Variable K-Maps * Gray Code

5. MAP SIMPLIFICATIONXYZ0011110001

5. MAP SIMPLIFICATION[EXAMPLE 2-6]

5. MAP SIMPLIFICATIONWhat to Study: ( ) (Dont-Care Conditions)

1. Implicant, Prime Implecant, Essential Prime ImplicantF = () + () + () + ()- Implicant = a product term if the function has the value 1 for all minterms of the product term, , .- Prime Implicant(PI) = implicant, implicant implicant. - Essential Prime Implicant (EPI) = .

5. MAP SIMPLIFICATION2. F = () + () + + () (i) implicant . (ii) PI.3. K-map Implicant, PI, EPI Implicant = 1-cell . PI = . EPI = .4. K-map PI , 1-cell ,(1) EPI .(2) PI .(3) PI [Secondary EPI] , (2) .(4) , (?) , (2) (3) .

5. MAP SIMPLIFICATION[Examples]

5. MAP SIMPLIFICATION5. Product-of-Sums Simplification ( )(1) F s-o-p complement .(2) F K-map 0-cell grouping. [Grouping , ][Example 2-8] F(A, B, C, D) = S(0, 1, 2, 5, 8, 9, 10)

5. MAP SIMPLIFICATION6. Dont-Care Conditions ()= .(i) the input combinations never occur. (ex) BCD code(ii) the input combinations would occur, but we do not care about the outputs in response to these combinations.=> We simply do not care what value is assumed by the function for the unspecified conditions.* imcompletely specified functions ( )- What shall we do with DC conditions?DC .But, somebody will get better designs!!How many complete specifications are possible for a 4-input1-output function with 6 DC conditions? ==>

5. MAP SIMPLIFICATION- , K-map: -, x, X, d, D, DEquation : F = [] + ... + [] + dc([] + ... + []) = [] + ... + [] + ([] + ... + [])dc = S(1, 2, ) + Sdc(7, 8, ) = P(0, 3, ) + Pdc(7, 8, )

- grouping , group group .(I) : grouping .(ii) : grouping .

5. MAP SIMPLIFICATION[Example] F(A,B,C,D) = S(1, 3, 7, 11, 15) + Sdc(0, 2, 5)

6. OTHER LOGIC GATESWhat to study: NAND NOR gate

1. AND, OR, NOT type gate .Gate type : - feasibility & economy of the gates in the implementation tech. - possibility of fan-in extension - ability to implement Boolean functions

2. Simple Gate Types in Bipolar and CMOS Technology: names(), graphic symbols( ), functions()[Figure 2-26] in next slide* negation indicator, bubble

6. OTHER LOGIC GATES

6. OTHER LOGIC GATES

6. OTHER LOGIC GATES3. Functional(Logical) Completeness () A set of gates are functionally, or logically complete if any Boolean function can be implemented or expressed using only the gate types in the set: {AND, OR, NOT} is functionally complete. {NAND} and {NOR} are functionally complete. [PROVE? => Figure 2-27, Figure 2-33 below] *Universal Gates

6. OTHER LOGIC GATES4. How to implement a Boolean function with NAND gates?(1) Obtain the simplified expression and/or circuit in terms of AND, OR, and NOT.(2) Convert AND, OR, NOT gates to NAND gates. [bubble insertion] more on later slides

Alternative NAND and NOT Symbols for Conversion [Fig. 2-28]

6. OTHER LOGIC GATES5. Two-Level NAND Circuits - NAND-NAND Two-Level Implementation - S-O-P expression can be realized by NAND-NAND circuits

Figure 2-29 for the circuits and also for the conversion from AND-OR using bubble insetion.[Example 2-9 & Fig. 2-30] F(x, y, z) = S(1, 2, 3, 4, 5, 7) NAND gates . (1) Simplify in sum-of-products form(2) Draw AND-OR network (Use buffer for terms with single literal)(3) Convert it into NAND-NAND network

6. OTHER LOGIC GATES6. NOR CircuitsCan repeat the disscussion with NAND circuits.

Alternative Symbols for NOR [Fig. 2-34]

NOR-NOR form = P-O-S expression [Fig. 2-35]

Converting AND/OR Circuits into NOR Circuits [Fig. 2-36]

6. OTHER LOGIC GATES

6. OTHER LOGIC GATES1. Exclusive-OR : XOR, EXOR, EOR - X Y = XY + XY [difference ftn.]2. Exclusive-NOR : XNOR, EXNOR, ENOR - complement of exclusive-or - (X Y) = XY + XY[equivanlece ftn]

6. OTHER LOGIC GATES3. XOR X 0 = X X 1 = X X X = 0 X X = 1 X Y = (X Y) X Y = (X Y) A B = B A(A B) C = A (B C) = A B C

6. OTHER LOGIC GATES4. XOR Gate NAND : [Fig. 2-37]5. XOR- A B C = ???- Odd function ( ) : F = 1 when - K-map for XORs: check board : [Fig. 2-38]- Multiple-Input XOR with 2-Input XOR: [Fig. 2-39]- : Parity

Gates as Control ElementsGate as OperatorsGate as Control Elements

(1) (Combinational Logic Circuits) - . - gate (no feedback).(2) (Sequential Logic Circuits) - . - gates + (storage elements: latch, flip-flop)

7. Determine the function that the given circuits implements: - Logic diagrams => Boolean functions => explanation - manual, logic simulationBoole 1. Label all the intermediate signals. 2. Usually from PI(Primary Input) to PO(Primary Output). 1. From Boolean functions, or 2. Directly from the logic diagram. (from PI to PO again)Logic Simulation - fast and accurate: logic waveforms, truth tables - not usually produce Boolean equations - input: net list, schematic input stimulus (vector or waveform)

7. T1= BC,T2 = ABT3 = A + T1 = A + BC,T5 = T2 + D = AB + D T4 = T2D = (AB)D = ABD + AD + BDF2 = T5 = AB + D F1 = T3+T4 = A+BC+ABD+AD+BD = A+BC+BD+BD

7. X Y ZT1T2CCT3S0 0 00 0 11 1 1

7. Computer Simulation* propagation delays , gate delay

8. Design Procedure 1. From spec., determine # and symbols of input and outputs. 2. Derive the truth table. 3. Obtain the simplified Boolean functions for each output. (2 , 2) 4. Draw the logic diagram. 5. Verify the correctness of the design. * For multiple-output circuits?* For multi-level circuits? * With gates in a library given?

8-1 BCD-to-Excess-3 Code Converter[ ] BCD-to-Excess-3 Code Converter

8-1 BCD-to-Excess-3 Code Converter

8-1 BCD-to-Excess-3 Code ConverterW = A+BC+BD = A+B(C+D)X = BC+BD+BCD = B(C+D)+BCD=B(C+D)+B(C+D)=B(C+D)Y = CD+CD = (CD) = ((C+D)(C+D)) = CD + (C+D)Z = D

8-2 BCD-to-Seven-Segment Decoder[ ] BCD-to-Seven-Segment Decoder

8-2 BCD-to-Seven-Segment DecoderMinimizing each output separately: => 26 AND gates.

11*11111*111*11*11*111*1*1111*1*1*

11*11*11*11*

1111*11*11*1*11*1

1*11*11*

8-2 BCD-to-Seven-Segment DecoderMinimizing each output separately, then simply sharing the same gates: => 15 AND gates

11*11111*111*11*11*111*1*1111*1*1*

11*11*11*11*

1111*11*11*1*11*1

1*11*11*

8-2 BCD-to-Seven-Segment DecoderMinimizing each output separately, then simply sharing the same gates, then reduce PI to non-PI for sharing: => 12 AND gates

11*11111*111*11*11*111*1*1111*1*1*

11*11*11*11*

1111*11*11*1*11*1

1*11*11*

8-2 BCD-to-Seven-Segment DecoderMore aggressive minimization: => 9 AND gates:

11111*1111111111111*11111*1

11*111111

11*11*11111*111

1*1111

9. Combinational MSIs & LSIsUltimate Goal of System Design - low cost over the product life of the system - design cost

9. Combinational MSIs & LSIsWhat kinds of MSI and LSI Circuits? (Refer to commercial data books.) - Combinational Circuits: multiplexer, decoder, encoder, demultiplexer, adder, adder-subtractor, look-ahead carry generator, parity generator/checker, 7-segment driver, comparator, multiplier, ALU, ROM, PLD(PROM, PLA, PAL, FPGA, ) - Sequential Circuits: counter, shift register, What to study for MSIs? - function (external operation) - internal organization - extension of data width - other applications

9-1 DECODERSFunction and Internal Structure: inverse of coding - output(s) selected by the input code are active,- input/output polarity (active HIGH/LOW)? - signals on unselected outputs (inactive state, or tri-state)? - enable signals & their polarity?7442 BCD-to-Decimal Decoder7447A BCD-to-Seven-Segment Decoder/Driver (active LOW)7448 BCD-to-Seven-Segemnt Decoder/Driver (active HIGH)74154 4-Line to 16-Line Decoder/Demultiplexer74156 Dual 2-Line to 4-Line Decoder/Demultiplexer

9-1 DECODERSTable 3-4 Truth Table for 3-to-8 Line Decoder

Inputs

Outputs

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

0

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D7

A2

3-to-8

D6

D5

A1

Line

D4

D3

A0

Decoder

D2

D1

D0

9-1 DECODERSFig 3-12:3-to-8Line Decoder

9-1 DECODERSFig 3-13: 2-to-4 Line Decoderwith Enable Input(active low output)

9-1 DECODERSDecoder Expansion: 3-to-8 Line Decoder with Two 2-to-4 Decoders

[Q] An enable input is a must for decoder expansion?

9-1 DECODERSCombinational Circuit ImplementationA decoder provides the 2n minterms of n input variables.Any Boolean function can be expressed as a sum of minterms.=> Any n-input m-output combinational circuit can be implemented with an n-to-2n-line decoder and m OR gates.[Example 3-4] Binary adder:S(X,Y,Z)=S(1,2,4,7)C(X,Y,Z)=S(3,5,6,7)

* Too many minterms?* Active low outputs?* Good for many outputs with small # of minterms

9-2 ENCODERSFunction and Internal Structure: coding - the output lines generate the (binary) code corresponding to the input value.- Input, output polarity?- Enable input?- Auxiliary outputs?74147 10-Line to 4-Line Priority Encoder74148 8-Line to 3-Line Priority Encoder

9-2 ENCODERSOctal-to-Binary Encoder (Table 3-5: Truth Table)- How to implement? => A2=D7+D6+D5+D4, - What happens if two or more inputs are active?- What is the difference when D=00000000 and D=00000001?

9-2 ENCODERSFig 3-16 & 3-174-Input Priority Recoder

Inputs

Outputs

D3

D2

D1

D0

A1

A0

V

0

0

0

0

0

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1

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X

0

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X

X

1

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1

X

X

X

1

1

1

D1

00

01

11

10

00

X

0

0

0

01

1

1

1

1

D2

D3

11

1

1

1

1

10

1

1

1

1

D0

D1

00

01

11

10

00

X

0

1

1

01

0

0

0

0

D2

D3

11

1

1

1

1

10

1

1

1

1

D0

9-3 MULTIPLEXERSExternal Operation, Internal StructureAs Building Blocks, Demultiplexer, ExpansionFunction- Data selector- 2n-to-1 line multiplexer(MUX)- Enable( or Strobe) input?- Common selection and/or enable line?74150 16-Line to 1-Line Multiplexer 74151 8-Line to 1-Line Multiplexer 74153 Dual 4-Line to 1-Line Multiplexer 74157 Quad 2-Line to 1-Line Multiplexer (Non-inverting) 74158 Quad 2-Line to 1-Line Multiplexer (Inverting) 74251 Mux with 30state outputs 74298 Quad 2-input Mux with Storage

9-3 MULTIPLEXERSInternal Structure: with gates Fig 3-18 4-to-1 Line Multiplexer (Function Table)

9-3 MULTIPLEXERSFig 3-20: Quadruple 2-to-1 Line Multiplexer

9-3 MULTIPLEXERSCombinational Circuit Implementation - How to choose the selection inputs?Fig 3-21 Implementing a Boolean Function with a Multiplexer

9-3 MULTIPLEXERSFig 3-12 Implementing a Four-Input Function with a Multiplexer

9-3 MULTIPLEXERSMultiplexer Expansion- 8x1 Mux by two 4x1 Muxes & one 2x1 Mux

- 64x1 by four 16x1 & one 4x1?

- 8x1 by two 4x1 with Enable and tri-state output?

01 4x12 mux Y3 S0 S1

01 2 3S0 S1 S2

45 6 7

9-4 DEMULTIPLEXERSDemultiplexer- inverse of the multiplexing: data distributor- equivalent to n-to-2n line decoder with enableFig 3-23 1-to-4 Line Demultiplexer

9-4 DEMULTIPLEXERSDemultiplexer & Decoder- 1/2 * 74LS139

As a Decoder As a Demultiplexer

E

S1

S0

D3

D2

D1

D0

H

X

X

H

H

H

H

L

L

L

H

H

H

L

L

L

H

H

H

L

H

L

H

L

H

L

H

H

L

H

H

L

H

H

H

S1

S0

D3

D2

D1

D0

X

X

H

H

H

H

L

L

H

H

H

E

L

H

H

H

E

H

H

L

H

E

H

H

H

H

E

H

H

H

9-5 BINARY ADDERS1. Half Adder = addition of two bits

9-5 BINARY ADDERS2. Full Adder = addition of three bits

9-5 BINARY ADDERS3. Binary Ripple Carry AdderFig 3-27 4-Bit Ripple Carry Adder

9-5 BINARY ADDERS4. Carry Lookahead AdderFig 3-28 Development of a Carry lookahead Adder (a)

9-5 BINARY ADDERSFig 3-28 Development of a Carry lookahead Adder (a)

9-6 BINARY ADDER-SUBTRACTORSFig 3-30 Adder-Subtractor Circuit

9-7 BINARY MULTIPLIERSFig 3-32 A 2-Bit by 2-Bit Binary Multiplier

9-7 BINARY MULTIPLIERSFig 3-33 A 4-Bit by 3-Bit Binary Multiplier

9-8 DECIMAL ARITHMETICFig 3-34 Block Diagram of BCD Adder