a 2.2ghz -242db-fom 4.2mw adc-pll using digital sub ... · 25.2: a 2.2ghz -242db-fom 4.2mw adc-pll...

25.2: A 2.2GHz -242dB-FOM 4.2mW ADC-PLL Using Digital Sub-Sampling Architecture© 2015 IEEE International Solid-State Circuits Conference 0 of 39

A 2.2GHz -242dB-FOM 4.2mW ADC-PLL

Using Digital Sub-Sampling Architecture

Teerachot Siriburanon, Satoshi Kondo, Kento

Kimura, Tomohiro Ueno, Satoshi Kawashima,

Tohru Kaneko, Wei Deng, Masaya Miyahara,

Kenichi Okada, and Akira Matsuzawa

Tokyo Institute of Technology, Japan


Outline• Motivation

• Phase Digitization

• ADC-Based Phase Detection

– Digitized sub-sampling architecture

– Resolution enhancement

• Circuit Implementation

– 4-bit flash ADC

– Push-pull class-C DCO

• Measurement Results

• Conclusion


Motivation

• PLL with low jitter and low power

• All-Digital PLL (AD-PLL)

– TDC-based phase detection

– Tradeoff in resolution and power

consumption

• Applications

– Wireless/Wireline transceivers

– Digital clocks




• ADC-Based Phase Detection




– 4-bit flash ADC



• Conclusion


Phase Digitization in AD-PLL

Digital phase detector is usually

based on time-domain approach

...00000111111...

Digital

Loop Filter

REF

DCO

TDCTDC

N


Time-Domain Digitization

- Resolution of inverter-chain TDC limited by one

propagation delay

- Improved resolution by Vernier chain but worsen

linearity and increase power

DQ

delay

DQ

delay

DQ

delay

e[k]

input

ref

• Inverter chain

[1] R. Staszewski, JSSC 2005

1

0

1

1

0

input

Delay e[k]

ref


Time-Domain Digitization (Cont.)

• Time Amplifier

- Improves resolution

- Gain error, mismatch, nonlinearity

of TA causes problems

([2] M. Lee, JSSC 2008)

Delay

Delay

Amplification in time

DQ

delay

DQ

delay

DQ

delayinput

ref

DQ

delay

DQ

delay

DQ

delay

Fine

e[k]Logic

mu

x

Coarse

e[k]

Time Amplifier


Common Issues in TDC

Jitter in delay line causes nonlinearity in TDC

INL

Output

code

delay

Output

code

delay

Gain

error


Proposed ADC-PLL

How about voltage-domain digitization?

00001111

Digital

Loop Filter

REFDPDADC

DCO


Time vs. Voltage Domain

TDC gain needs

calibrationADC full range can be

accurately generated

ADC full

range

VREFP

VREFN

TDC full range varies

over PVT variations


Time vs. Voltage Domain (Cont.)

Require large hardware

cost for nonlinearity

calibration

Linear voltage division can

be achieved by a resistor

ladder

Linear

voltage

division

mismatch

INL



Time amplifier is not

linear

Voltage amplifier can be

very accurate

x G

x G vrms



[14] A. Abidi, JSSC 2006

jitter α 𝐤𝑻/𝑪

Not a factor of current

jitter α𝑰𝑫𝟐

𝐤𝑻𝑪

REF

Vsamp


Simplified Operation

• Phase leading or lagging can be detected by a

simple ADC

• Low power operation can be achieved since

operating at reference clock

n-bit

A/D

Ref

Digital

LPF

DCO


Simplified Operation (Cont.)

• Time resolution can be improved by voltage

gain amplifier

n-bit

A/D

Ref

Digital

LPFxG

DCO


111

110

101

011010

001

000

100

Simplified Operation (Cont.)

Δt

code

• Voltage gain increases the slope of input signal

resulting in high resolution in time


Trade-off in resolution and power

• Extremely fine resolution can be achieved by

increasing gain in voltage

0

2

4

6

8

10

12

0.01 0.1 1 10

Po

wer

(mW

)

Time Resolution (ps)

[7] JSSC 09(GRO)

[6]JSSC 10(Vernier)

[5]ESSCIRC 10(Stochastic)

[3]CICC 13(Charge)

[4]VLSI 11(Pipeline)

N=4, G=20

[2]JSSC 08(TA)

TDC-based

ADC-based

N=4, G=50


Time vs. Voltage Phase Digitization

Time / TDC Voltage / ADC

Full RangeNot accurate

(calibration possible)Stable

Linearity Not accurate

(Require lookup

table)

Accurate

Resolution Can be fine Fine

Power (PDC)High power is

required to lower

internal jitter

Low

• Voltage-domain approach has a potential to break

trade-off in resolution and power




• ADC-based Phase Detection




– 4-bit flash ADC



• Conclusion


Analog Sub-Sampling PLL

• PD/CP noise is not

multiplied by N2

• No divider noise

• Bulky analog LF

• PVT variations

VCO

CP out(t)LFREF

[8] X. Gao, ISSCC 2009

Ph

ase

No

ise PLL

SSPLL20logN

Offset frequency


Proposed ADC-PLL

• ADC-Based PLL

– Digital sub-sampling architecture

• Voltage-domain digital PLL with enhanced

resolution

– Resolution enhancement by voltage

amplification

– No analog loop filter

• Other Building Blocks

– A 4-bit flash ADC with resistive averaging

– Class-C push-pull DCO with adaptive biases


Simplified Block Diagram

• Frequency locked loop is used to assist the

limited acquisition range of ADC PD

/4

1-1-1

MASH4bit

ADC-PD

Digital

Loop

Filter

Class-C Push-

Pull DCO

Frequency

Locked Loop

FREF


Sample and Hold

• Phase difference is sampled into voltage difference

G A/D Digital

Outputs

REF

REF

VSP

VSN

VON

VOP

From DCO After Sampler

From

DCO

VSN

VSP

VOP

VON


G A/D Digital

Outputs

REF

REF

Gain Amplification

ΔVsamp ΔVsamp

• Voltage difference can be further amplified for

finer resolution

From

DCO

VSP VGP

VSN VGN

G

VGP

VGN

VSN

VSP


ADC Phase Detection

• Phase of reference clock is faster than that of DCO

VOP

VON

ref1

ref2

ref4

ref5

ref7

Ideal locking

point

ref3

ref6

FREF

COMP1=1

COMP2=1

COMP3=1

COMP4=0

COMP5=0

COMP6=0

COMP7=0

Comparator

Outputs

Encoder and

Digital Loop

Filter (DLF)

(3-bit case)


ADC Phase Detection (Cont.)

• Phase of reference clock is slower than that of DCO

VOP

VON

ref1

ref2

ref4

ref5

ref7

Ideal locking

point

ref3

ref6

FREF

COMP1=1

COMP2=1

COMP3=1

COMP4=1

COMP5=0

COMP6=0

COMP7=0

Comparator

Outputs

Encoder and

Digital Loop

Filter (DLF)

(3-bit case)


Resolution Enhancement

Ideal locking

point

code

Δt

ΔΦ

Ideal locking

point

code

ΔΦ

Δt’

Δt ≅ Vrange

2N∙VDCO

1

2πfDCO

∙

without pre-amplifier G with pre-amplifier G

Δt’ = 1

G∙ Δt


High Resolution in ADC-PD

• Comparator noise is negligible but sampling noise could limit the PLL phase noise performance

0

1E-13

2E-13

3E-13

4E-13

5E-13

0 10 20 30 40 50 60

Res

olu

tio

n,

Jit

ter

(ps)

Gain

Sampling Noise (kT/C)

Resolution of ADC-PD

0.5

0.4

0.3

0.2

0.1

0

Δt =1

2N∙G∙2πfDCO

Δt α 𝑮 𝒌𝑻/𝑪

C=500fF


Effect of Resolution Enhancement

Phase Error

in Time

Time (s)

G=1

(Δt≈4.52ps)G=20

(Δt≈0.23ps)

0

24∙ΔtG=20

≈ 3.6ps

24∙ΔtG=1

≈ 72.3ps 6∙σT

≈2.3ps

PLL jitter

(peak-to-peak)




• ADC-based Phase Detection




– 4-bit flash ADC



• Conclusion


4-Bit Flash ADC

[9] M. Miyahara, ISSCC 2014

• ADC achieves 10-mV min. resolution with non-calibrated

2.5-mVrms offset

V’OP1

V’ON1

V’OP2

V’ON2

COMP1

Latch

Latch

4-bit Comaparators with Resistive Averaging

4-bit

OutputsCOMP2

LatchDummy

Latch

Latch

V’OP15

V’ON15Latch COMP15

Dummy Dummy

Dummy


Vbias_n

Vbias_p

Vref

Vbias_n

Vbias_p

Vbias_p

VCM

VDD

Vtail

VN VP

Cap. Bank

Vbias_n

Class-C Push-Pull DCO

0.3

0.4

0.5

0.6

0.7

0.8

0 250 500 750 1000 1250 1500

Time (ns)

Vo

lta

ge(V

)

Vbias_n

Start-up Steady-State

Vbias_p

VCM

• Robust Startup

• Enhance oscillation swing

at steady state

[10] A. Mazzanti, JSSC 2013

Voltage [V]


Chip Microphotograph

DCO

Core

ADC-PD

Synthesized

Circuits

0.3 mm0.5

mm

• 65nm CMOS

• Core Area: 0.15 mm2

• Supply Voltage: 1V

• Power: 4.2mW

− DCO ~ 1.5mW

− ADC ~ 1.2mW

− VGA ~ 0.5mW

− Others ~ 1mW


-150

-130

-110

-90

-70

-50

-30

10K 100K 1M 10M

Ph

ase

No

ise

(d

Bc/H

z)

Offset Frequency (Hz)

Phase Noise

Frequency: 2.2GHz

Integrated Jitter: 380fs

PDC: 4.2mW


Measured Spur Level

-74dB

-90

-70

-50

-30

-10

2.09 2.13 2.18 2.22 2.27 2.31

Ou

tpu

t p

ow

er

(dB

m)

Frequency (GHz)


Performance Summary of AD-PLL

*PLL FOM is calculated based on RMS jitter

** Estimated from the figure

This

Work

C. Hsu,

JSSC'08

Rylyakov,

ISSCC’09

C.Yao,

JSSC'13

Chilara,

ISSCC'14

M. He,

ISSCC'14

TopologyADC-

based

TDC-

based

BB-

based

TDC-

based

TDC-

based

TDC-

based

Freq. 2.2GHz 3.6GHz 20GHz 2.7GHz 2.4GHz 5.8GHz

RMS Jitter 380fs 200fs 1ps** 230fs 1.71ps 175fs

In-band

Phase

Noise

-112

dBc/Hz

-107

dBc/Hz

-83**

dBc/Hz

-110

dBc/Hz

-90

dBc/Hz

-105

dBc/Hz

Ref. Spur -74dBc -65dBc N/A -75dBc -70dBc N/A

PLL FoM* -242dB -237dB -220dB** -240dB -236dB -244dB

Power 4.2mW 47mW 64mW 17mW 0.9mW 12.9mW

Area 0.15mm2 0.95mm2 0.11mm2 0.62mm2 0.20mm2 N/A

Tech. 65nm 130nm 65nm 180nm 40nm 40nm


Conclusions

• ADC-based AD-PLL is proposed using

Voltage-domain digitization in sub-

sampling architecture

• Resolution can be enhanced by voltage

amplification

• Voltage domain approach can help

achieving high resolution in phase

detection without calibrations


Acknowledgement

This work was partially supported by

MIC, SCOPE, MEXT, STARC, and VDEC in

collaboration with Cadence Design

Systems, Inc., Synopsys, Inc., and

Mentor Graphics, Inc.


[1] R. B. Staszewski, et al., “All-digital PLL and transmitter for mobile phones,” IEEE

Journal of Solid-State Circuits (JSSC), vol. 40, no. 12, pp. 2469–2482, Dec. 2005.

[2] M. Lee, and A. Abidi, “A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital

Converter in 90 nm CMOS that Amplifies a Time Residue,” IEEE Journal of Solid-State

Circuits (JSSC), vol. 43, no. 4, pp. 769–777, Apr. 2008.

[3] Z. Xu, et al., "A 0.84ps-LSB 2.47mW Time-to-Digital Converter Using Charge Pump

and SAR-ADC", IEEE CICC, San Jose, USA, Sep. 2013.

[4] Y. Seo, et al., "A 0.63ps resolution, 11b pipeline TDC in 0.13µm CMOS," Symp. VLSIC

2011, pp.152-153

[5] M. Zanuso, et al., "Time-to-digital converter with 3-ps resolution and digital

linearization algorithm," Proc. ESSCIRC 2010, pp.262-265.

[6] J. Yu, et al., “A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13um CMOS

Technology,” IEEE Journal of Solid-State Circuits (JSSC), vol. 45, no. 4, pp. 830–842, Apr.

2010.

[7] C. Hsu, et al., "A Low-Noise Wide-BW 3.6-GHz Digital ΔΣ Fractional-N Frequency

Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise

Cancellation," IEEE JSSC, Vol. 43, No. 12, pp. 2776-2786, Dec. 2008.

Reference


[8] X. Gao, et al., "A 2.2-GHz -7.6mW Sub-Sampling PLL with -126dBc/Hz In-Band Phase

Noise and 0.15psrms Jitter in 0.18um CMOS," IEEE International Solid-State Circuits

Conference (ISSCC), San Francisco, CA, USA, pp. 392-393, Feb. 2009.

[9] Masaya Miyahara, et al., "A 2.2GS/s 7b 27.4mW Time-based Folding Flash ADC with

Resistive Averaged Voltage-to-Time Amplifiers," IEEE International Solid-State Circuits

Conference (ISSCC), San Francisco, CA, pp. 388-389, Feb. 2014.

[10] A. Mazzanti, and P. Andreani, “A Push-Pull Class-C CMOS VCO,” IEEE Journal of

Solid-State Circuits (JSSC), vol. 48, no. 3, pp. 724–732, Mar. 2013.

[11] C.-W. Yao, and A. N. Willson, "A 2.8-3.2-GHz Fractional-N Digital PLL With ADC-

Assisted TDC and Inductively Coupled Fine Tuning DCO," IEEE JSSC, vol. 48, no. 3, pp.

698-710, Mar. 2013.

[12] V. K. Chillara, et al., "An 860μW 2.1-to-2.7GHz All-Digital PLL-Based Frequency

Modulator with a DTC-Assisted Snapshot TDC for WPAN (Bluetooth Smart and Zigbee)

Applications," IEEE ISSCC, pp.172-173, Feb. 2014.

[13] M. He, et al., "A 40nm Dual-Band 3-Stream 802.11 a/b/g/n/ac MIMO WLAN SoC with

1.1Gb/s Over-the-Air Throughput," IEEE ISSCC, pp. 350-351, Feb. 2014.

[14] A. A. Abidi, “Phase Noise and Jitter in CMOS Ring Oscillators," IEEE JSSC, vol. 41,

no. 8, pp. 1803-1816, Aug. 2006.

Reference (Cont.)

a 2.2ghz -242db-fom 4.2mw adc-pll using digital sub ... · 25.2: a 2.2ghz -242db-fom 4.2mw adc-pll...

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