a 2.2gs/s 7b 27.4mw time-based folding-flash … › publications › 2014 › isscc › miyahara...

22.6: A 2.2GS/s 7b 27.4mW Time-Based Folding-Flash ADC with Resistively Averaged Voltage-to-Time Amplifiers© 2014 IEEE International Solid-State Circuits Conference 0 of 30

Masaya Miyahara, Ibuki Mano, Masaaki Nakayama, Kenichi Okada, and Akira Matsuzawa

Tokyo Institute of Technology, Japan

Matsuzawa& Okada Lab.

A 2.2GS/s 7b 27.4mW Time -Based Folding -Flash ADC with Resistively

Averaged Voltage -to-Time Amplifiers


Outline

• Motivation• Design concepts

• Time-based folding architecture• Voltage -to-time amplifier

• Measurement results• Conclusion


MotivationFlash ADCs

☺☺☺☺ Highest conversion rate and lowest latency⇒⇒⇒⇒ High speed feedback-loop systems

�� Power and area are proportional to the number of comparators

Folding -Flash ADCs☺☺☺☺ Less number of comparators�� Power consuming of amplifiers in the folding

circuit[1, 2]

New efficient folding architecture is required[1] Y. Nakajima, et al., JSSC 2010 [2] T. Yamase, et al., VLSI symp. 2011


Conventional Folding -Flash ADC

Folding times2M-1

N : Resolution [bit]

Number of Comps2M + 2N-M+1

N=7bit, M=4128⇒⇒⇒⇒32

Coarse Fine

Inp

ut

sig

nal

of

CO

MP

s

No fo

ldin

g

Fla

sh

Fo

ldin

g

Co

ars

eF

ine


Conventional Folding Circuit

• Large current is needed for high speed• Voltage gain is reduced by technology

scalingVFold

VinVth1

Vth2

Vth3

Vth4


New Design Concepts

Time-based -folding architecture• Voltage-based ⇒⇒⇒⇒ Time-based Folding

☺☺☺☺ More suitable for finer process

• Simple logic circuits can realize folding signal of the timing edge☺☺☺☺ No static current

Voltage -to-time amplifier• Dynamic amplifier with resistive averaging

☺☺☺☺ No static current☺☺☺☺ No need of calibration


t

VP

VN

t

DP

DN

V

T

t

VN

VP

t

DP

DN

V

T

t

Case1

Case2

Voltage to Time ConversionVoltage -based Time-based

Case1VP>VN

Case2VP<VN


Block Diagram

Upper dummy

Lower dummy

Input range

En

co

der

Co

ars

e S

R L

atc

hT

ime

-bas

ed

Fo

lder x

4

Fin

e IP

SR

Latc

h

D-F

F x

7

Res

istiv

e A

vera

gin

g


Output of VT Amps

Each VT Amp generates pulse signal which has delay time depending on input signal.

V-T

V-T

V-T

DP3

DN3

DP2

DN2

DP1

DN1

L

VINP3

VINN3

VINP2

VINN2

VINP1

VINN1 L

DP1,N1

DP2,N2

DP3,N3

t

DP1 DN1

DP2 DN2

DN3 DP3


Output of VT Amps

De

lay

Tim

e

How is the folding signal generated in time domain?

V-T

V-T

V-T

DP3

DN3

DP2

DN2

DP1

DN1

L

VINP3

VINN3

VINP2

VINN2

VINP1

VINN1


Delay Time Selector

D1

D2

DAND

Slower signal ⇒⇒⇒⇒ AND GateFaster signal ⇒⇒⇒⇒ OR Gate

Delay time selector


Time-Based -FoldingD

ela

y T

ime

Peak fold ⇒⇒⇒⇒ OR gate

D1_1=DN0 OR DP2 D1_2=DN4 OR DP6


Time-Based -FoldingD

ela

y T

ime

Valley fold ⇒⇒⇒⇒ AND gate

D2_1=D1_1 AND D1_2

D1_1=DN0 OR DP2 D1_2=DN4 OR DP6


TF Circuit Implementation

Folding factor = 8

Symmetrical input logic cells are used for realizin g same transition time.


TF output for interpolation

Time-based folder outputs four signals to interpolate in the fine SR latches.

Dela

y T

ime




VIN

DF1

DF2

DF3

DF4

(DF2:DF3=1:1)

(DF1:DF4=1:1)


De

lay T

ime




Interpolated SR Latch

2bit

SR-Latch

QF

QFB

1bit3bit Interpolator

DF1

DF4

DF2

DF3

DF1

DF4

DF2

DF3

S (DF1:DF4=5:3)

R (DF2:DF3=5:3)

3

1

2

2

3

1

2

2

1

1

1

1

DF1 DF4

S

DF2

R

QF

S

R

QF

DF3

SR-Latch response in the case of

interpolation ratio of 5:3

Gate weighted inverter realizes interpolated signal [6]⇒⇒⇒⇒No need of reference signal in fine SR latches.

[6] D. Miyashita, et al., VLSI symp. 2011


Voltage -to-Time Amplifier

VDD

DN DP

VINP VINN

L

L

M1 M2

M3 M4M5 M6

M9

M7 M8

W5=4W3

W6=4W4

Positive feedback

PFB can increase the gain by about 4 times.⇒⇒⇒⇒No need calibration in coarse and fine Latches.

0

0.2

0.4

0.6

0.8

1

1.2

4.0E-10 5.0E-10 6.0E-10

VT

Am

p ou

tput

s [V

]

Time [s]

PFB1.1ps/mV

w/o PFB0.24ps/mV

DP

DN

DPDN


Time [s]

Ou

tpu

ts [

V]

Resistively Averaged VT Amps

V-T

V-T

V-T

DP3

DN3

DP2

DN2

DP1

DN1

L

VINP3

VINN3

VINP2

VINN2

VINP1

VINN1 DP2 DP3DP1

Ideal case 0 LSBDNL(σσσσ)

Resistive averaging reduces the mismatch voltage.


Time [s]

Ou

tpu

ts [

V]

Resistively Averaged VT Amps

V-T

V-T

V-T

DP3

DN3

DP2

DN2

DP1

DN1

L

VINP3

VINN3

VINP2

VINN2

VINP1

VINN1 DP2 DP3DP1

Mismatch 0.5 LSBIdeal case 0 LSB

DNL(σσσσ)Resistive averaging reduces the mismatch voltage.


Time [s]

Ou

tpu

ts [

V]

Resistively Averaged VT AmpsResistive averaging reduces the mismatch voltage.

DP2 DP3DP1

Averaged 0.16 LSBMismatch 0.5 LSBIdeal case 0 LSB

V-T

V-T

V-T

DP3

DN3

DP2

DN2

DP1

DN1

L

VINP3

VINN3

VINP2

VINN2

VINP1

VINN1

DNL(σσσσ)


Chip photo

0.25mm0.

21m

m

• 40nm LP 8M1P CMOS technology • Chip area of 0.052mm 2


Measured DNL, INL

-2.0

-1.0

0.0

1.0

2.0

0 32 64 96 128

DN

L [L

SB

]

OUTPUT CODE

-2.0

-1.0

0.0

1.0

2.0

0 32 64 96 128

INL

[LS

B]

OUTPUT CODE

+0.6/-0.6 LSB

+1.0/-1.0 LSB


Sampling rate vs. SNDR

20

25

30

35

40

45

50

0 400 800 1200 1600 2000 2400 2800

SN

R, S

FD

R, S

ND

R [d

B]

Sampling rate [MS/s]

SNR SFDR SNDR

Input Frequency = 100MHz SNDR [email protected]/s


Input Frequency vs . SNDR

20

25

30

35

40

45

50

0 200 400 600 800 1000 1200 1400

SN

R, S

FD

R, S

ND

R [d

B]

Input Frequency [MHz]

SNR SFDR SNDR

Sampling rate = 2.2GS/sSNDR [email protected]


Measured Spectrum

-100

-80

-60

-40

-20

0

0 50 100 150

Nor

mal

ized

Pow

er [d

B]

Frequency [MHz]

Sampling rate = 2.2GS/sInput frequency = 800MHz

(Output code is decimated by 8)


Performance Summary

ISSCC 2008 [3] VLSI 2012 [8] VLSI 2013 [9] This workTechnology 90nm 40nm 32nm SOI 40nm LP

Resolution [bit] 5 6 6 7Power Supply [V] 1 1.1 0.85 1.1

Sampling Frequency [GS/s] 1.75 3 5 2.2Power Consumption [mW] 2.2 11 8.5 27.4

SNDR @Nyquist [dB] 27.6 33.1 30.9 37.4FoMw [fJ/conv.-step] 64.5 99.3 59.4 210

FoMs [dB] 143.5 144.4 145.6 143.3

Core area [mm 2] 0.0165 0.021 0.02 0.052Calibration Off chip Foreground Off chip No need

• The highest SNDR in Flash ADCs exceeding 2 GS/s

• No need of calibration

*3.3mW for reference ladder, 19.4mW for analog and 4.7mW for digital

*


Conclusion

• Time-based -folding architecture☺☺☺☺ More suitable for future process☺☺☺☺ No static current

• Voltage -to-time amplifier•Dynamic amplifier with resistive averaging

☺☺☺☺ No static current☺☺☺☺ 1/3 offset voltage, no need of calibration

• A 7b 2.2GS/s 27.4mW Folding Flash ADC is realized


Acknowledgement

This work was partially supported by MIC,Berkeley Design Automation for theuse of the Analog Fast SPICE(AFS)Platform, and VDEC in collaboration withCadence Design Systems, Inc .


References[1] Y. Nakajima, et al., “A Background Self-Calibrated 6b 2.7GS/s ADC Wit h Cascade-

Calibrated Folding-Interpolating Architecture,” IEEE J. Solid-State Circuits, vol. 45, pp. 707-718, Apr. 2010.

[2] T. Yamase, et al., “A 22-mW 7b 1.3-GS/s Pipeline ADC with 1-bit/sta ge Folding Converter Architecture,” Symp. VLSI Circuits, pp. 124-125, June 2011.

[3] B. Verbruggen, et al., “A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm D igital CMOS,” I SSCC Dig. Tech. Papers, pp. 252-253, Feb. 2008.

[4] M. Miyahara, et al., “A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs”, IEEE A-SSCC, pp. 269-272, Nov. 2008.

[5] K. Makigawa, et al., “A 7bit 800Msps 120mW Folding and Interpolation ADC Using a Mixed-Averaging Scheme,” Symp. VLSI Circuits, pp. 124-125, June 2006.

[6] D. Miyashita, et al., “A -104dBc/Hz In-Band Phase Noise 3GHz All Digit al PLL with Phase Interpolation Based Hierarchical Time to Digi tal Convertor,” Symp. VLSI Circuits, pp. 112-113, June 2011.

[7] B. Murmann, “ADC performance survey 1997-2013,” [Online]. Available: http://www.stanford.edu/˜murmann/adcsurvey.html.

[8] Y. -S Shu, “A 6b 3GS/s 11mW Fully Dynamic ADC i n 40nm CMOS with Reduced Number of comparators,” Symp. VLSI Circuits, pp. 26-27, June 2012.

[9] V. H. -C. Chen and L. Pileggi, “An 8.5mW 5GS/s 6b Flash ADC with Dynamic Offset Calibration in 32nm CMOS SOI,” Symp. VLSI Circuits, pp. 264-265, June 2013.

a 2.2gs/s 7b 27.4mw time-based folding-flash … › publications › 2014 › isscc › miyahara...

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