A low power tunable Gm–C filter based on double CMOSinverters in 0.35 lm

Abbas Pirmohammadi • Mohammad Hossein Zarifi

Received: 11 May 2011 / Revised: 5 July 2011 / Accepted: 9 July 2011 / Published online: 21 July 2011

� Springer Science+Business Media, LLC 2011

Abstract In this article, an inverter based transconductor

using double CMOS pair is proposed for implementation of

a second order lowpass Gm–C Filter. The proposed oper-

ational transconductance amplifier (OTA) and biquad filter

are designed using standard 0.35 lm CMOS technology.

Simulation results demonstrate the central frequency tun-

ability from 10 kHz to 2.8 MHz which is suitable for the

wireless specifications of Bluetooth (650 kHz), CDMA

2000 (700 kHz) and Wideband CDMA (2.2 MHz) appli-

cations. The power consumption of the filter is 445 nW and

178 lW at 10 kHz and 2.8 MHz from 3.3 V supply volt-

age, respectively. The active area occupied by the designed

filter on the silicon is 215 9 720 lm2. The proposed

approach guarantees the upper bound on THD to be

-40 dB for 300 mVpp signal swing. Employing the double

CMOS pair in the inverters causes PSRR to reach 68.6 dB

which is higher than similar works.

Keywords Inverter � Double inverter CMOS pair �Gm–C filter and OTA

1 Introduction

Continuous-time filters are quite suited for applications with

moderate speed and low power requirements. Traditionally,

continuous time complementary metal oxide semiconductor

(CMOS) filters with Gm–C architecture have been designed

with MOS transistors operating in strong inversion region

when the interest bandwidth is of the order of several tens of

MHz. A number of architectures have been proposed in the

literature for implementing the transconductor.

A Gm–C bandpass filter of the OTA based on CMOS

inverters with a tuning range of 2.25–3.3 MHz is achieved

in [1], which does not have any internal node and results in

large bandwidth. However, for realizing tunable filters, this

scheme requires the power supply voltage to be varied.

This is not suitable for low voltage applications and results

in poor power supply rejection ratio (PSRR) [1]. To solve

this problem, an OTA Based on FGMOS inverters imple-

mentation is proposed in [2]. The proposed OTA in [1]

requires two voltage sources, one for the filter core and the

other for tuning circuitry.

A 260 MHz continuous-time 5th-order Gm–C biquad low-

pass filter with an automatic tuning circuit has been reported

in [3] Variable MOS capacitances and Digital Controlled

Capacitance Array are two tuning techniques that have been

employed. Otin et al. [4] introduced a programmable 4th

order Gm–C filter with automatically tunable structure.

Quality factor has been improved while other parameters kept

constant. Lo et al. [5] presented a continuous-time analog

filter and achieved a linear structure using flipped-voltage

follower. The active resistor used in the strong inversion

region to achieve the transconductance tuning. Ezzati et al.

implements an adaptive tuning system in Gm–C continuous

time (CT) filter. Reported tuning system is able to tune both

central frequency and quality factor simultaneously [6].

A. Pirmohammadi

Department of Electrical and Computer Engineering,

Ahar Branch, Islamic Azad University, Ahar, Iran

M. H. Zarifi (&)

Nano and Bio Electronics Lab. (NBEL),

Department of Electrical and Computer Engineering,

Science and Research Branch, Islamic Azad University,

Tabriz, Iran

e-mail: m_zarifi@tabrizu.ac.ir

123

Analog Integr Circ Sig Process (2012) 71:473–479

DOI 10.1007/s10470-011-9710-x

In this work, we used double CMOS pair transistors,

operated in sub threshold region, the second isolated volt-

age source for tuning circuit will no longer required.

However, In addition to this, the operation in sub threshold

region can also result in lower power dissipation. Further-

more, the ratio of gain to DC power consumption of the

transconductor operated in subthreshold region is higher

than that operated in strong inversion region, since in sub-

threshold region; drain current has an exponential depen-

dency to the gate-source voltage. By increasing the width of

the transistors operating in subthreshold, the high gain can

still be maintained, while DC power consumption is sub-

stantially reduced. The Gm–C filter has been designed and

simulated in a standard 2P3M 0.35-lm CMOS technology.

2 Proposed structure

2.1 OTA structure

Figure 1 shows the proposed topology derivates from [1].

The operational OTA shown in Fig. 1, is denoted as Gm

block. These Gm blocks are constructed using double

CMOS pair [7] shown in Fig. 2 and the latter is referred to

as gm cell. The class AB OTA in Fig. 1 needs no extra

circuitry to control the DC output value; due to the node A

provides a DC common mode voltage about VDD/2 at node

OUT? and OUT-. The voltage VA and equivalent resis-

tance RA at node A, equal to VA = (VIN??VIN-)/2 and

RA = 1/2gm respectively. The output current at node

OUT?, is the sum of the output currents provided by

inverters Inv3 and Inv8, hence,

IOUTþ ¼ �gm VIN�ð Þ þ gm VINþ þ VIN�ð Þ2

¼ gm VINþ � VIN�ð Þ2

ð1Þ

Designed OTA is able to operate in both voltage and

current mode. Also, by providing the better frequency

performance, lower common mode transconductance gain

and better linearity can be used as alternative design of

Nauta OTA [8–9]. To avoid employing separate supply

voltage, double CMOS inverters are replaced in the CMOS

inverter. This inverter has two inputs one is using for signal

processing (Vin) and the other input uses for tuning of the

inverter (Vg1, Vg4) (Fig. 2).

The double CMOS pair is constructed using the CMOS

pair consisting of two transistors as shown in Fig. 3.

Assume that both transistors operate in weak inversion

region(subthreshold), the current ID for single PMOS/

NMOS transistor can be driven as (2), [10],

ID¼2nkU2T exp

VGB�VT0

nUT

� �exp

�VSB

UT

� ��exp

�VDB

UT

� �� �

ð2Þ

where ‘n’ is sub threshold slope factor, l’ is mobility,

‘Cox’ is the oxide capacitance of the transistor, b = lCox

is process gain factor and transconductance parameter

k = b(W/L). The thermal voltage ‘UT’ is 25.9 mV at room

temperature, VGB, VSB, VDB are gate, source, drain

voltages according to the bulk voltage respectively, VT0

Fig. 1 Double CMOS pair

based Gm block

Fig. 2 Double CMOS pair

474 Analog Integr Circ Sig Process (2012) 71:473–479

123

is the threshold voltage when VSB is Zero. When

VDB [ 5 UT and VSB = 0, an approximate expression of

ID for single transistor is given by (3).

ID ¼ 2nkU2T exp

VGS � VT0

nUT

� �ð3Þ

The current I1 and I2 of the double CMOS pair shown in

Fig. 2 are given by (4) and (5) respectively

I1 ¼ 2keff nU2T exp

VGSeq1 � Vteq1

nUT

� �ð4Þ

I2 ¼ 2keff U2T exp

VGSeq2 � Vteq2

nUT

� �ð5Þ

where, 1ffiffiffiffiffiffiKeff

p ¼ 1ffiffiffiffiKn

p þ 1ffiffiffiffiKp

p ; VGSeq1 ¼ VG1 � Vi; VGSeq2 ¼

Vi þ VG4 and Vteq1 ¼ Vtn1 þ Vtp2

�� ��; Vteq2 ¼ Vtn3 þ Vtp4

�� ��.The double CMOS pair [7], acts as a transconductance cell.

VGSeq1 is the equivalent gate to source voltage between

transistors M1, M2 and VGSeq2 is the equivalent gate to

source voltage between transistors M3, M4 (Fig. 2). all of

the MOS devices are operating in the weak inversion

saturation region and neglecting the channel length

modulation, the output current can be expressed as,

ID1 ¼ I1 � I2 ¼ �2keff nU2T

�exp

VGSeq1 � Vteq1

nUT

� �

� expVGSeq2 � Vteq2

nUT

� ��ð6Þ

Assuming that the n-well process is used, the P-MOS

transistors can have their bulks connected to their own

source terminals and this eliminates the body effect. The

bulks of M1 and M3 should be connected to the most

negative supply (Gnd), resulting in a rise in threshold

voltage. This bulk effect causes the relationship between V

and I to be non-linear. However, when the CMOS pair is

used in Barthelemy’s structure [1], the terms involving the

even powers of input signal get cancelled due to

differential circuit. The terms involving odd powers of

input signal will remain. ID1 and ID2 are the currents

coming out of Inv7 and Inv8 (Fig. 1) respectively.

The differential current coming out of the Gm cell

Io = ID1 - ID2 is given by

IO ¼ �4keff nU2T

�exp

VGSeq1 � Vteq1

nUT

� �

� expVGSeq2 � Vteq2

nUT

� ��ð7Þ

and Gm1 can be derived by taking partial derivative of (7)

vs. VGSeq and is given by

Gm1 ¼ID1

nUTð8Þ

Thus the Gm can be varied by varying the bias voltage VG1,

VG4 and the aspect ratio of the MOS transistors. In order to

ensure that all transistors in gm cell remain in the weak

inversion saturation region, the input voltage Vi and bias

voltage VG must satisfy the inequalities given as

VG1 � Vteq1�Vi�VG4 þ Vteq2 ð9Þ

VG1 should be lesser than or equal to Vdd and VG4 should

be greater than or equal to Gnd.

3 Filter design

The cascade connection of the first—and second—order

filters is a common approach for implementation of high

order filters. For this reason, the performance of the pro-

posed OTA has been evaluated by means of the second-

order filter. The scheme of this filter is shown in Fig. 4. The

transfer function of the lowpass and bandpass filter can be

drive from (10) and (11), respectively:

Hlp sð Þ ¼ Volp sð ÞVi sð Þ

� �¼

gm1gm2

C1C2

s2 þ gm3

C1sþ gm2gm4

C1C2

ð10Þ

Hbp sð Þ ¼ Vobp sð ÞVi sð Þ

� �¼

gm1

C1s

s2 þ gm3

C1sþ gm2gm4

C1C2

ð11Þ

where gmi (i = 1 to 4) and Ci (i = 1 to 2) represent the

transconductance of the ith transconductor and integrating

Fig. 4 Schematic of Gm–C biquad

Fig. 3 CMOS pair

Analog Integr Circ Sig Process (2012) 71:473–479 475

123

capacitor of the ith capacitor in Fig. 4, respectively.

Therefore, the expressions of the gain, f0 and Q are:

Hlp 0ð Þ ¼ gm1

gm4

ð12Þ

Hbp x0ð Þ ¼ gm1

gm3

ð13Þ

f0 ¼1

2p

ffiffiffiffiffiffiffiffiffiffiffiffiffiffigm2gm4

C1C2

rð14Þ

Q ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffigm2gm4

g2m3

C1

C2

sð15Þ

The biquad filter can be designed by using of

Eqs. 12–15 and by varying the Vg1 and Vg4, we can change

the cut off frequency of discussed filter. In tunable con-

tinuous time filters, the center frequency and the quality

factor of the filter can be tuned by varying Gm, which in

turn is controlled by changing either the bias current or the

device dimensions. From (14), the center frequency of the

filter can be varied either by the constant-C or constant-Gm

method. In constant-C technique, the load capacitance is

maintained constant and the value of Gm is changed to alter

the centre frequency of the filter. In constant-Gm technique,

Gm is kept constant and the value of load capacitance is

changed to alter the centre frequency of the filter. In this

article, constant-C approach is used for tunable filter

realizations.

4 Results and discussion

The proposed OTA is implemented in standard 2P3M

0.35 lm CMOS technology with 3.3 V supply voltage.

Simulation results demonstrate total power consumption of

445 nW at 10 kHz and 178 lW at 2.8 MHz. Post-layout

simulation is presented in this section. Figure 5 shows AC

analysis for the proposed OTA. The differential gain of the

OTA is 29.3 dB, its phase margin is 82.8 degree and the

unity gain frequency is 28.97 MHz.

The DC V–I characteristics of the OTA (Iod vs. Vid) for

different bias voltages (Vg1, Vg4) of the double CMOS

pair are presented in Fig. 6. This figure indicates that the

output current is linearly proportional to differential

voltage, up to ±200 mV. The simulated transconductance

for this OTA varies from 49.6 nS to 12.5 lS. The line-

arity of the proposed OTA was evaluated with the total

harmonic distortion (THD), applying 300 mVP-P signal as

an input signal which demonstrates -40 dB as related

THD.

Figure 7, shows the power supply rejection ration

(PSRR) for the OTA for z B 0.5 pF (z is the output

capacitance). PSRR characteristics are obtained with

100 mV ripple on Vdd. Simulation clearly shows that this

OTA exhibits a good PSRR with total rejection of

68.6 dB.

Furthermore, in order to evaluate the selected trans-

conductance function, a biquad filter in the same technol-

ogy at 3.3 V supply voltage (Fig. 4) with a tuning range of

Fig. 7 Power supply rejection (PSRR) vs. frequency for z B 0.5 pF

Fig. 5 AC analysis of the designed OTA

Fig. 6 DC V–I characteristics of the proposed OTA

476 Analog Integr Circ Sig Process (2012) 71:473–479

123

10 kHz–2.8 MHz was designed and simulated, that has

suitable for low power application. Values of capacitors C1

and C2 were set to 2 and 1 pF. From Fig. 8, it can be

observed that the cut off frequency can be tuned from

10 kHz to 2.8 MHz.

The filter performance for typical, slow–slow, fast–fast,

slow–fast, and fast–slow of NMOS and PMOS transistors

parameters for the 0.35 lm-CMOS process has been

demonstrated in Fig. 9.

Temperature variation has strong effect on the transfer-

function of the designed filter and tuning is inevitable for

temperature-variation compensation (Fig. 10).

Cadence has been used to draw the Layout of the

designed filter which is presented in Fig. 11. This filter

consumes 215 9 720 lm2 of silicon active area.

The transistor dimensions (width and length) of Fig. 2

are presented in Table 1.

The performance of the proposed OTA and comparison

with previous work is summarized in Table 2.

The designed filter is compared to the other filters and

results are presented in Table 3.

5 Conclusion

This article presents a new OTA, based on double CMOS

pair which is implemented in standard 0.35 lm CMOS

process. This OTA has a unity gain frequency of

28.97 MHz, open loop DC gain of 29.3 dB and phase

margin of 82.8 degree. Using inverters with double

CMOS pair in subthreshold region, causes the power

consumption of the OTA to be very low, that is about

44.53 lW. THD of the proposed OTA is equal to

-40 dB with 300 mVP-P signal swing. The PSRR of

designed OTA is reached to 68.6 dB which is higher than

similar works. The designed low pass filter have fre-

quency tuning from 10 kHz to 2.8 MHz which Suitable

for the wireless specifications of Bluetooth (650 kHz),

CDMA2000 (700 kHz) and Wideband CDMA (2.2 MHz)

applications. The designed filter has maximum power

consumption of 178 lW.

Table 1 Dimensions of transistors for Double CMOS pair

Transistor Length of

Transistor (lm)

Width of

Transistor (lm)

M1 0.7 14

M2 0.7 45

M3 0.7 1.75

M4 0.7 2

Fig. 8 Gm–C filter f0 tunability for the low-pass responses

Fig. 10 Filter transfer function for different temperatures

Fig. 9 Process corners effect on filter transfer function

Fig. 11 Layout view of the Biquad filter

Analog Integr Circ Sig Process (2012) 71:473–479 477

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References

1. Barthelemy, H., Meill, S., Gaubert, J., Dehaese, N., & Bourdel, S.

(2008). OTA based on CMOS inverter and application in the

design of tunable bandpass filter. Analog Integrated Circuits andSignal Processing, 57, 169–178.

2. Sobhi, J., Koozhkanani, Z. D., & Rahin, A. B. (2010). A low

voltage and low power programmable continuous-time filter

based on FGMOS inverters. In International Conference onCircuit and Signal Processing (ICCSP 2010), Shanghai, China,

25–26 Dec 2010.

3. Fan, J., Li, W., Li, N., & Ren, J. (2008). A 260 MHz 5-order

Gm–C biquad low-pass filter with wide frequency tuning range. In

IEEE Conference 2008, Beijin, pp. 1617–1620.

4. Otin, A., Celma, S., & Aldea, C. (2007). A 40–200 MHz pro-

grammable 4th-order Gm–C filter with auto-tuning system. In

IEEE Conference 2007, Muenchen, Germany, pp. 214–217.

5. Lo, T.-Y., Kao, C.-S., & Hung, C.-C. (2009). A Gm–C continu-

ous-time analog filter for IEEE 802.11 a/b/g/n wireless LANs.

Analog Integrated Circuits and Signal Processing, 58, 197–

204.

6. Ezzati, N., & Abdollahzadeh, S. (2010). High speed and silicon-

saving adaptive tuning system for high frequency Gm-C filters.

Analog Integrated Circuits and Signal Processing, 65, 97–103.

7. Park, C. S., & Schaumann, R. (1986). A high-frequency CMOS

linear transconductance element. IEEE Transactions on Circuitsand Systems, 33, 1132–1137. doi:10.1109/TCS.1986.1085859.

8. Nauta, B. (1992). A CMOS transconductance-C filter technique

for very high frequencies. IEEE Journal of Solid-State Circuits,27(2), 142–153.

9. Nauta, B., & Seevinck, E. (1989). Linear CMOS transconduc-

tance element for VHF filters. Electronics Letter, 25, 448–450.

10. Tsividis, Y. (1995). Mixed analog digital VLSI devices andtechnology (p. 66). New York: McGraw-Hill.

Table 2 Simulated

performance of the proposed

OTA and comparison

Parameters [1] [2] This work

CMOS inverter FGMOS inverter Double CMOS pair

Technology 0.35-lm MOS 0.35-lm CMOS 0.35-lm CMOS

Supply voltage (V) 2.5 1.0 3.3

Open loop DC gain (dB) 31.3 27 29.3

GBW 3.56 GHz 207 MHz 28.97 MHz

Phase margin (�) 77 91 82.8

CMRR@10 kHz – 27.34 dB 35.19 dB

PSRR 37.45 dB – 68.6 dB

Output voltage swing 2.27 (50–950) mV 0.88 V

THD @500mVP-P

-46 dB

@300mVP-P

-50 dB

@300mVP-P

-40 dB

Power consumption (lW) 800 25 44.53

Table 3 Simulated

performance of the Gm–C

biquad and comparison

Parameters [1] [2] This work

CMOS inverter FGMOS inverter Double CMOS pair

Technology 0.35-lm CMOS 0.35-lm CMOS 0.35-lm CMOS

Supply voltage (V) 2.5 1.0 3.3

Power consumption 3.99 mW 80 lW 178 lW

Frequency tuning 10 MHz 100 kHz–1 MHz 10 kHz–2.8 MHz

Tuning range – 10 [200

Auto tuning No No No

Active area – – 0.16 mm2

THD – @Vpp \ 0.4 V

\-38 dB

@Vpp \ 300 mV

-40 dB

Input referred noise – – 113 nV/sqrt(Hz)

Filter order Biquad Biquad Biquad

478 Analog Integr Circ Sig Process (2012) 71:473–479

123

Abbas Pirmohammadi was

born in Tabriz, Iran, in 1981. He

received the BS degree in

Electrical and Electronics engi-

neering from Tabriz Azad Uni-

versity, Tabriz, Iran, in 2005.

He is working as Instrument and

Control expert in the Iranian

offshore oil company from 2005

to now. He is currently working

toward the MS degree at the

Ahar Azad University. His cur-

rent research interests include

Low power and high-frequency

filters.

Mohammad Hossein Zarifiwas born in 1982. He received

the BS, MS and PhD degree in

electrical engineering from

University of Tabriz, Tabriz,

Iran, in 2004, 2006, 2009

respectively. He is now an

assistant professor of Electrical

Engineering at Islamic Azad

University Science and

Research branch and head of

Electronics and Communication

Department. His research inter-

ests include design of high-

speed and low-power analog

circuits, analog-to-digital converters, and low-power analog VLSI and

A/D systems for biomedical applications. Dr. Zarifi is a member of

the IEEE Solid-State Circuits Society, the IEEE Engineering in

Medicine and Biology Society, and the IEEE Circuits and Systems

Society. Dr. Zarifi holds more than 30 international journal and

conference publications.

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