combinational mos logic circuit a. marzuki. topics static characteristic dynamic characteristic...
Post on 21-Dec-2015
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CMOS NOR GATEAnalysis similar to CMOS Inverter , VOL = 0 V, VOH=VDD
!VS4=VDD-VSD3
!ID3+ID4=2ID
AA
BB
!replace ID of BB with AA
Complex Logic Circuits
•OR by parallel-connected drivers.•AND by series-connected drivers.•Inversion by MOS circuit operation.
CMOS Logic Circuit
Pull down graph (NMOS)
Vertex represents node
Pull up graph: vertex is drawn with areaof pull down graph. Edge cross pull downgraph’s edge once.
Discuss Example 7.2Assuming W/L for PMOS is 15 for NMOS is 10
Answer is W/L for n is 12, while p is 12.5
Dynamic Characteristics (Delay)
Capacitance? Pls read chapter 6 and chapter 3. For our case, We just Use Cout i.e. the final total capacitance.
Stick Diagram
• A stick diagram is a graphical view of a layout.
• Does show all components/vias (except possibly tub ties), relative placement.
• Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.
Stick Diagram
• Represents relative positions of transistors
• Stick diagrams help plan layout quickly– Need not be to scale– Draw with color pencils or dry-erase markers
In
Out
VDD
GND
Inverter
A
Out
VDD
GNDB
NAND2
Common Euler Path
The Euler path is defined as an uninterrupted path
that traverses each edge (branch) of the graph exactly once
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