compal la-1811 rev 0.7
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Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
Cover Sheet
1 66, 07, 2003星期四 八月
Compal Electronics, Inc.
Schematics DocumentCompal confidential
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2003-07-30(Under review)
DT TRANSPORT or Prescott uFCPGAwith ATI-RC300M+SB200 core logic
LA-1811
REV:0.7
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Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
Block Diagram
2 66, 07, 2003星期四 八月
Compal Electronics, Inc.
page 7
MDC & BT Conn
EC I/O Buffer
page 25
VGA DDR x2 CHB
page 39
page 41
HDDConnectorpage 31
Thermal SensorADM1032AR
page 44
AC-LINK
page 45
LCD Conn ATI-RC300M
VIA VT1211
DC/DC Interface CKT.
page 25
page 47
CABLE CONN.
page 40
page 14,15,16
page 49
page 4,5,6
Audio Codec
ATI-M9+X/M10C
page 44,45
page 26,27,28,29
CDROM Connector
IDSEL:AD20(PIRQA,B#,GNT#2,REQ#2)
page 37
BGA 457 pin
page 46
CardBus Controller
868 pin u-BGA
Secondary IDE
NS 87591
IDSEL:AD19(PIRQD#,GNT#1,REQ#1)
page 43
Super I/O
page 35
VGA DDR x2 CHA
FDD
IDSEL:AD18(PIRQC#,GNT#3,REQ#3)
ADI 1981B
Primary IDE
Touch Pad
Mini PCIsocket
IEEE 1394TI-TSB43AB22
Compal confidential
AGP BUS
page 30
USB2.0
page 34
page 50,51,52,53,54,55,56,57
page 34
page 45
ATI-SB200
H_A#(3..31)
PCI BUS
RTC CKT.
page 23
RJ45 CONN
LAN
Int.KBD
Power Circuit DC/DC
uFCBGA-479/uFCPGA-478 CPU
H_D#(0..63)
page 22
page 26
page 40
ATA-100
page 47
RJ11 CONN
IDSEL:AD16(PIRQA#,GNT#0,REQ#0)
2.5V DDR- 200/266
BIOS
USB conn x3
A-Linkpage 38
Power OK CKT.
ATA-100
page 7
PSB
Intel Northwood/Prescott Processor
page 43
page 48
Fan Control
page 44
Mini-PCI solt
LPC BUS
AMP & Audio Jack
RTL 8101BL
page 32
File Name :LA1811
W/EXT VGA CHIP
page 45
800MHz
DDR-SO-DIMM X2
Slot 0,1
page 17,18,19,20,21
3.3V 33 MHz
page 44
W/EXT VGA CHIP
Power On/Off CKT.
BANK 0, 1, 2, 3
Memory BUS(DDR)
FIR
W/O EXT VGA CHIP
page 8,9,10,11,12,13
CRT & TV-OUT Conn.
TI PCI1520/1620
VGA M9 Embeded
PARALLEL
W/O EXT VGA CHIP
*RJ45 CONN*LINE IN JACK*DC JACK*COM PORT*USB CONN x1*SPDIF*5V INPUT*VOLUME ADJUSTMENT KEY+TV-OUT PORT
page 30
Card slot
BT/USB KEYUSB1.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
CLOCK GENERATORICS951402AGT
page 24
page 33
page 44
page 36
USB2.0 Ctrl.NEC uPD720101
IDSEL:AD23(PIRQA/C/D#,GNT#4,REQ#4)
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Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
Notes List
3 66, 07, 2003星期四 八月
Compal Electronics, Inc.
External PCI Devices
Voltage Rails
IDSEL # PIRQ
DDR SO-DIMM 0
REQ/GNT #DEVICE
NB Internal VGA
1 0 1 0 0 0 0 XA0
AGP BUSSOUTHBRIDGEUSBAC97ATA 100ETHERNET1394L ANCARD BUSWireless LAN(MINI PCI)
N/AAGP_DEVSELAD31 (INT.)AD30 (INT.)AD31 (INT.)AD31 (INT.)AD24(INT.)AD16AD19AD20AD18
2
N/A
3
01
N/AN/AN/AN/AN/AN/A
N/A
AA
DB
CA
A
A .BC
D
I2C / SMBUS ADDRESSING
DEVICE HEX ADDRESS
DDR SO-DIMM 1CLOCK GENERATOR (EXT.)
A2D2
1 0 1 0 0 0 1 X1 1 0 1 0 0 1 X
Power Plane
B+
+1.25VS
Description
VIN
+VCC_CORE Core voltage for CPUAC or battery power rail for power circuit.
1.25V switched power rail for DDR VttThe voltage for Processor VID select
Adapter power supply (19V)
+VCCVIDON
N/AN/A
S3
OFFON
S5
OFF
N/AOFF
N/AN/A
ON
N/A
OFFOFF OFF
S0-S1 Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build
NAGP@ : means just build when no external AGP VGA chip build in (UMA).
OFFOFF
ON2.5V switched power rail
+3VS OFF
ON*+2.5VS
3.3V switched power rail
ONON2.5V system power rail for DDR
ON*ON
OFF
+2.5VALW+2.5V
ON
1.5V I/O power rail for ATI-RS300M/RC300M NB AGP.
OFF2.5V always on power rail
+3VALWON
ON
OFFON
OFF+1.5VS
3.3V always on power rail
+1.8VS
ON
1.8V switched power rail for ATI-RS300M/RC300M NB.
OFF
OFFOFF
ON
ON
+1.2VS_VGA 1.2V I/O power rail for ATI-VGA M9+X/M10P. ON OFFOFF
12V always on power rail+5VS
ONONONOFF
ON
ON
ON+12VALW
5V switched power rail OFF
RTC powerON*
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
ON
RTCVCC ON
ON*+5VALW 5V always on power rail
+3V 3.3V system power rail for SB,LAN,CardReader and HUB.ON
ONOFF
+5V 5V system power rail .
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ON ON OFF
M10@ : means build VGA M10M9@ : means build VGA M9+XM9-M10@ : means build VGA M9 or M10 1520@ : means build Cardbus PCI15201620@ : means build Cardbus PCI1620
EXT USB AD23(EXT.) 4 A,C,D
ATI@ : means build ATI SB USB2.0 related to turn on the function .NEC@ : means build NEC USB2.0 related to turn on the function .
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CK_BCLK#
H_A#3H_A#4H_A#5H_A#6H_A#7H_A#8H_A#9H_A#10H_A#11H_A#12H_A#13H_A#14H_A#15H_A#16H_A#17H_A#18H_A#19H_A#20H_A#21H_A#22H_A#23H_A#24H_A#25H_A#26H_A#27H_A#28
H_A#31
H_A#29H_A#30
H_D#0H_D#1H_D#2H_D#3H_D#4H_D#5H_D#6H_D#7H_D#8H_D#9H_D#10H_D#11H_D#12H_D#13H_D#14H_D#15H_D#16H_D#17H_D#18H_D#19H_D#20H_D#21H_D#22H_D#23H_D#24H_D#25H_D#26H_D#27H_D#28H_D#29H_D#30H_D#31H_D#32H_D#33H_D#34H_D#35H_D#36H_D#37H_D#38H_D#39H_D#40H_D#41H_D#42H_D#43H_D#44H_D#45H_D#46H_D#47H_D#48H_D#49H_D#50H_D#51H_D#52H_D#53H_D#54H_D#55H_D#56H_D#57H_D#58H_D#59H_D#60H_D#61H_D#62H_D#63
H_IERR#
H_REQ#0H_REQ#1H_REQ#2H_REQ#3H_REQ#4
CK_BCLK
H_D#[0..63] <8>H_A#[3..31]<8>
H_REQ#[0..4]<8>
H_ADS#<8>
H_BR0#<8>
H_LOCK#<8>
CK_BCLK<24>CK_BCLK#<24>
H_HIT#<8>H_HITM#<8>
H_DEFER#<8>
H_BOOTSELECT <56>
H_BNR#<8>H_BPRI#<8>
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+5VS+5VS
Title
Size Document Number R ev
Date: Sheet o f
LA-1811 0.7
Prescott Processor in uFCPGA478
4 66, 07星期四 八月 , 2003
Compal Electronics, Inc.
Pull-up56ohmto +VCC_CORE
Pull-up 56ohmto +VCC_CORE
Pull-up 62ohmto +VCC_CORE
Prescott
B6 FERR# FERR#/PBE# Pull-up 62ohmto +VCC_CORE
Pull-up 62ohmto +VCC_CORE
Reference Intel documentDesktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0
Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5
Pin number NorthwoodPin name
PrescottPin name
Commend Commend
AA20 ITPCLKOUT0 Pull-up56ohmto +VCC_CORE
TESTHI6 Pull-up 62ohmto +VCC_CORE
Pop
Pop
Pop
Pop
Pop
PopDepop
Pop
Pop
Depop
DepopPop
Pop
Northwood
Pop
Depop
Depop
AB22 ITPCLKOUT1 Pull-up 56ohmto +VCC_CORE
TESTHI7 Pull-up 62ohmto +VCC_CORE
AD2 NC VIDPWRGD Pull-up 2.43K ohmto +VCCVID
float
AD3 NC float VID5 Pull-up1Kohm to+3VRUN & connectto PWRIC
AF3 NC float VCCVIDLB Connect to +VCCVID
Northwood MT
Northwood MTPin name
AD20
VCCA VCCIOPLLConnect to CPUFilter
FERR#
ITPCLKOUT0
ITPCLKOUT1
Connect to CPUFilterAE23
Connect to CPUFilter
Connect to CPUFilter
NC
NC
NC
VCCA
VSS
VCCIOPLL VCCA
AD1 VSS BOOTSELECT
VCCIOPLL
VSS
Connect to GND CPU determine
AE26 VSS Connect to GND OPTIMIZED/COMPAT#
Commend
float
Pop
Pop
Pop
TESTHI12 TESTHI12AD25 DPSLP
Connect to CPUFilter
Connect to CPUFilter
Connect to GND
Connect to GND
Pop
Pop
float
float
float
Depop
Depop
Depop
Pull-up 62ohmto +VCC_CORE Pop
Pull-up 200ohmto +VCC_CORE
Connect to PLDthrough 0ohm Pop Pop
A6 TESTHI11 GHIPull-up 200ohmto +VCC_CORE
Pull-up 62ohmto +VCC_CORE
Connect to PLD CPUPREF through0ohm PopPop Pop
TESTHI11
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R230@62_0402_5%1 2
R900
100K_0402_5%
12
R1099
47K_0402_5%
12
R1100
47K_0402_5%
12
R899 22K_0402_5%1 2
Prescott
JP8A
AMP_3-1565030-1_Prescott
A#3K2A#4K4A#5L6A#6K1A#7L3A#8M6A#9L2A#10M3A#11M4A#12N1A#13M1A#14N2A#15N4A#16N5A#17T1A#18R2A#19P3A#20P4A#21R3A#22T2A#23U1A#24P6A#25U3A#26T4A#27V2A#28R6A#29W1A#30T5A#31U4A#32V3A#33W2A#34Y1A#35AB1
REQ#0J1REQ#1K5REQ#2J4REQ#3J3REQ#4H3ADS#G1
AP#0AC1AP#1V5BINIT#AA3IERR#AC3
BNR#G2 BPRI#D2 BR0#H6
LOCK#G4
DEFER#E2 HITM#E3 HIT#F3
D#0 B21D#1 B22D#2 A23D#3 A25D#4 C21D#5 D22D#6 B24D#7 C23D#8 C24D#9 B25
D#10 G22D#11 H21D#12 C26D#13 D23D#14 J21D#15 D25D#16 H22D#17 E24D#18 G23D#19 F23D#20 F24D#21 E25D#22 F26D#23 D26D#24 L21D#25 G26D#26 H24D#27 M21D#28 L22D#29 J24D#30 K23D#31 H25D#32 M23D#33 N22D#34 P21D#35 M24D#36 N23D#37 M26D#38 N26D#39 N25D#40 R21D#41 P24D#42 R25D#43 R24D#44 T26D#45 T25D#46 T22D#47 T23D#48 U26D#49 U24D#50 U23D#51 V25D#52 U21D#53 V22D#54 V24D#55 W26D#56 Y26D#57 W25D#58 Y23D#59 Y24D#60 Y21D#61 AA25D#62 AA22D#63 AA24
VC
C_0
A10
VC
C_1
A12
VC
C_2
A14
VC
C_3
A16
VC
C_4
A18
VC
C_5
A20
VC
C_6
A8
VC
C_7
AA
10V
CC
_8A
A12
VC
C_9
AA
14V
CC
_10
AA
16V
CC
_11
AA
18V
CC
_12
AA
8V
CC
_13
AB
11V
CC
_14
AB
13V
CC
_15
AB
15V
CC
_16
AB
17V
CC
_17
AB
19V
CC
_18
AB
7V
CC
_19
AB
9V
CC
_20
AC
10V
CC
_21
AC
12V
CC
_22
AC
14V
CC
_23
AC
16V
CC
_24
AC
18V
CC
_25
AC
8V
CC
_26
AD
11V
CC
_27
AD
13V
CC
_28
AD
15V
CC
_29
AD
17V
CC
_30
AD
19V
CC
_31
AD
7V
CC
_32
AD
9V
CC
_33
AE
10V
CC
_34
AE
12V
CC
_35
AE
14V
CC
_36
AE
16V
CC
_37
AE
18V
CC
_38
AE
20V
CC
_39
AE
6V
CC
_40
AE
8V
CC
_41
AF1
1V
CC
_42
AF1
3V
CC
_43
AF1
5V
CC
_44
AF1
7V
CC
_45
AF1
9V
CC
_46
AF2
VC
C_4
7A
F21
VC
C_4
8A
F5V
CC
_49
AF7
VC
C_5
0A
F9V
CC
_51
B11
VC
C_5
2B
13V
CC
_53
B15
VC
C_5
4B
17V
CC
_55
B19
VC
C_5
6B
7V
CC
_57
B9
VC
C_5
8C
10V
CC
_59
C12
VC
C_6
1C
14V
CC
_62
C16
VC
C_6
3C
18V
CC
_64
C20
VC
C_6
5C
8V
CC
_66
D11
VC
C_6
7D
13V
CC
_68
D15
VC
C_6
9D
17V
CC
_70
D19
VC
C_7
1D
7V
CC
_72
D9
VC
C_7
4E
12V
CC
_75
E14
VC
C_7
6E
16V
CC
_77
E18
VC
C_7
8E
20V
CC
_79
E8
VC
C_8
0F1
1
VS
S_0
H1
VS
S_1
H4
VS
S_2
H23
VS
S_3
H26
VS
S_4
A11
VS
S_5
A13
VS
S_6
A15
VS
S_7
A17
VS
S_8
A19
VS
S_9
A21
VS
S_1
0A
24V
SS
_11
A26
VS
S_1
2A
3V
SS
_13
A9
VS
S_1
4A
A1
VS
S_1
5A
A11
VS
S_1
6A
A13
VS
S_1
7A
A15
VS
S_1
8A
A17
VS
S_1
9A
A19
VS
S_2
0A
A23
VS
S_2
1A
A26
VS
S_2
2A
A4
VS
S_2
3A
A7
VS
S_2
4A
A9
VS
S_2
5A
B10
VS
S_2
6A
B12
VS
S_2
7A
B14
VS
S_2
8A
B16
VS
S_2
9A
B18
VS
S_3
0A
B20
VS
S_3
1A
B21
VS
S_3
2A
B24
VS
S_3
3A
B3
VS
S_3
4A
B6
VS
S_3
5A
B8
VS
S_3
6A
C11
VS
S_3
7A
C13
VS
S_3
8A
C15
VS
S_3
9A
C17
VS
S_4
0A
C19
VS
S_4
1A
C2
VS
S_4
2A
C22
VS
S_4
3A
C25
VS
S_4
4A
C5
VS
S_4
5A
C7
VS
S_4
6A
C9
BO
OTS
ELE
CT
AD
1
VS
S_4
7A
D10
VS
S_4
8A
D12
VS
S_4
9A
D14
VS
S_5
0A
D16
VS
S_5
1A
D18
VS
S_5
2A
D21
VS
S_5
3A
D23
VS
S_5
4A
D4
VS
S_5
5A
D8
BCLK0AF22BCLK1AF23
VC
C_8
1F1
3V
CC
_82
F15
VC
C_8
3F1
7V
CC
_84
F19
VC
C_8
5F9
VC
C_7
3E
10
R231 51_0402_5%1 2
Q1062SC2411K_SC59
C1
E3
B2
Q107
MMBT3904_SOT23
2
31
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ITP_TMS
ITP_TDI
ITP_TCK
ITP_TDO
H_VID_PWRGD
H_TESTHI2_7
H_FERR#
H_THERMTRIP#
H_RESET#
H_PROCHOT#
H_PWRGOOD
CK_ITPCK_ITP#
VID3VID4VID5
ITP_TRST#
H_TESTHI9
H_PWRGOOD
H_RS#0
ITP_BPM#3
ITP_TDIITP_TCK
H_RS#2
H_RESET#
ITP_BPM#0
H_RS#1
H_PROCHOT#
ITP_BPM#2
VID0
H_THERMTRIP#
ITP_DBRESET#
H_TESTHI0_1
COMP0
ITP_TDO
H_VCCA
ITP_BPM#1
COMP1
H_FERR#
H_TESTHI11
ITP_TRST#
ITP_BPM#5ITP_BPM#4
H_TESTHI10
H_THERMDC
H_TESTHI8
ITP_TMS
H_THERMDA
H_DPSLP#
VID1VID2
VID4
VID1VID2
VID5
VID3
VID0
H_VID_PWRGD
ITP_DBRESET#
H_VSSA
CPU_STP#
CPU_STP#
H_RS#[0..2]<8>
H_TRDY#<8>
H_A20M#<26>H_FERR#<26>
H_IGNNE#<26>H_SMI#<26>
H_PWRGOOD<26>H_STPCLK#<26>
H_INTR<26>H_NMI<26>
H_INIT#<26>H_RESET#<8,26>
H_DBSY#<8>H_DRDY#<8>
H_THERMDA<7>H_THERMDC<7>
H_THERMTRIP#<7>
VCCSENSE<56>VSSSENSE<56>
H_DSTBN#0 <8>H_DSTBN#1 <8>H_DSTBN#2 <8>H_DSTBN#3 <8>
H_DSTBP#0 <8>H_DSTBP#1 <8>H_DSTBP#2 <8>H_DSTBP#3 <8>
H_ADSTB#0 <8>H_ADSTB#1 <8>
H_DINV#0 <8>H_DINV#1 <8>H_DINV#2 <8>
H_PROCHOT# <26,51>
H_DINV#3 <8>
H_CPUSLP# <26>
VID4<56>
VID2<56>VID1<56>
VID5<56>
VID0<56>
VID3<56>
VID_PWRGD<55,56>
CK_ITP<24>CK_ITP#<24>
CPU_GHI# <27>
CPUCLK_STP#<11,26,56>
BSEL0<13,24>BSEL1<13,24>
+CPU_GTLREF
+CPU_GTLREF
+VCCVID
+VCC_CORE
+3VS
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+3VS
+3VALW
+VCCVID
+VCCVID
+3VS
+VCC_CORE
Title
Size Document Number R ev
Date: Sheet o f
LA-1811 0.7
Prescott Processor in uFCPGA478
5 66, 07星期四 八月 , 2003
Compal Electronics, Inc.
Place near SB200 (U6)
Place near CPU
Close to the CPU
3. Place decoupling cap 220PF near CPU.
GTL Reference Voltage
2. Place R_A and R_B near CPU.
Layout note :
R_A
R_B
1. +CPU_GTLREF Trace wide12mils(min),Space 15mils
1.Place cap within 600 mils ofthe VCCA and VSSA pins.
Note: Please change to 10uH, DC currentof 100mA parts and close to cap
PLL Layout note :
2.H_VCCIOPLL,HVCCA,HVSSA trace wide12 mils(min)
Close to the ITP
Between the CPU and ITP
H_TESTHI12
I f CPU is P4 , Change theresistor R53 9,R540 value to51 .1_0603_1%,or pre scott6 1 . 9 _ 0 6 0 3 _ 1 %
If CPU is P4 , Change the resistorR546 va lue to 75_0603_1%
If CPU is P4 , Change the resistorR550 va lue to 39_0402_5%
If CPU is P4 , Change the resistorR556 va lue to 27.4_0402_5%
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R522 56_0402_5%1 2
R545
4.7K_0402_5%
R521 56_0402_5%1 2
R1125
12K_0402_5%
1 2
R559680_0603_5%
1 2
+C854
33U_D2_8M_R35
1
2
R55047_0402_5%
12
G
D
SQ45
2N7002 1N_SOT23
2
13
C546
0.1U_0402_10V6K1
2
RP137 56_0804_8P4R_5%
1 82 73 64 5
L37 LQG21F4R7N00_0805
1 2
Prescott
JP8B
AMP_3-1565030-1_Prescott
RS#0F1RS#1G5RS#2F4RSP#AB2TRDY#J6
A20M#C6FERR#B6IGNNE#B2SMI#B5PWRGOODAB23STPCLK#Y4
TESTHI12 AD25
LINT0D1LINT1E5INIT#W5RESET#AB25
DRDY#H2 DBSY#H5
THERMDCC4 THERMDAB3
TDIC1 TCKD4
TDOD5TMSF7TRST#E6
COMP1P1 COMP0L24
DP#0 J26DP#1 K25DP#2 K26DP#3 L25
VS
S_5
7A
E11
VS
S_5
8A
E13
VS
S_5
9A
E15
VS
S_6
0A
E17
VS
S_6
1A
E19
VS
S_6
2A
E22
VS
S_6
3A
E24
OPTIMIZED/COMPAT# AE26
VS
S_6
5A
E7
VS
S_6
6A
E9
VS
S_6
7A
F1V
SS
_68
AF1
0V
SS
_69
AF1
2V
SS
_70
AF1
4V
SS
_71
AF1
6V
SS
_72
AF1
8V
SS
_73
AF2
0
SK
TOC
C#
AF2
6
VS
S_7
5A
F6V
SS
_76
AF8
VS
S_7
7B
10V
SS
_78
B12
VS
S_7
9B
14V
SS
_80
B16
VS
S_8
1B
18V
SS
_82
B20
VS
S_8
3B
23V
SS
_84
B26
VS
S_8
5B
4V
SS
_86
B8
VS
S_8
7C
11V
SS
_88
C13
VS
S_8
9C
15V
SS
_90
C17
VS
S_9
1C
19V
SS
_92
C2
VS
S_9
3C
22V
SS
_94
C25
VS
S_9
5C
5V
SS
_96
C7
VS
S_9
7C
9V
SS
_98
D10
VS
S_9
9D
12V
SS
_100
D14
VS
S_1
01D
16V
SS
_102
D18
VS
S_1
03D
20V
SS
_104
D21
VS
S_1
05D
24V
SS
_106
D3
VS
S_1
07D
6V
SS
_108
D8
VS
S_1
09E
1V
SS
_110
E11
VS
S_1
11E
13V
SS
_112
E15
VS
S_1
13E
17V
SS
_114
E19
VS
S_1
15E
23V
SS
_116
E26
VS
S_1
17E
4V
SS
_118
E7
VS
S_1
19E
9V
SS
_120
F10
VS
S_1
21F1
2V
SS
_122
F14
VS
S_1
23F1
6V
SS
_124
F18
VS
S_1
25F2
VS
S_1
26F2
2V
SS
_127
F25
VS
S_1
28F5
VID
0A
E5
VID
1A
E4
VID
2A
E3
VID
3A
E2
VID
4A
E1
GTLREF0 AA21GTLREF1 AA6GTLREF2 F20GTLREF3 F6
NC1 A22NC2 A7
TESTHI0 AD24TESTHI1 AA2TESTHI2 AC21TESTHI3 AC20TESTHI4 AC24TESTHI5 AC23TESTHI6 AA20TESTHI7 AB22TESTHI8 U6TESTHI9 W4
TESTHI10 Y3TESTHI11 A6
VS
S_1
29F8
VS
S_1
30G
21V
SS
_131
G24
VS
S_1
32G
3V
SS
_133
G6
VS
S_1
34J2
VS
S_1
35J2
2V
SS
_136
J25
VS
S_1
37J5
VS
S_1
38K
21V
SS
_139
K24
VS
S_1
40K
3V
SS
_141
K6
VS
S_1
42L1
VS
S_1
43L2
3V
SS
_144
L26
VS
S_1
45L4
VS
S_1
46M
2V
SS
_147
M22
VS
S_1
48M
25V
SS
_149
M5
VS
S_1
50N
21V
SS
_151
N24
VS
S_1
52N
3V
SS
_153
N6
VS
S_1
54P
2V
SS
_155
P22
VS
S_1
56P
25V
SS
_157
P5
VS
S_1
58R
1V
SS
_159
R23
VS
S_1
60R
26V
SS
_161
R4
VS
S_1
62T2
1V
SS
_163
T24
VS
S_1
64T3
VS
S_1
65T6
VS
S_1
66U
2V
SS
_167
U22
VS
S_1
68U
25V
SS
_169
U5
VS
S_1
70V
1V
SS
_171
V23
VS
S_1
72V
26V
SS
_173
V4
VS
S_1
74W
21V
SS
_175
W24
VS
S_1
76W
3V
SS
_177
W6
VS
S_1
78Y
2V
SS
_179
Y22
VS
S_1
80Y
25V
SS
_181
Y5
BSEL0AD6BSEL1AD5
BPM#0AC6BPM#1AB5BPM#2AC4BPM#3Y6BPM#4AA5BPM#5AB4
DSTBN#0 E22DSTBN#1 K22DSTBN#2 R22DSTBN#3 W22
DSTBP#0 F21DSTBP#1 J23DSTBP#2 P23DSTBP#3 W23
ITP_CLK0AC26ITP_CLK1AD26
ADSTB#0 L5ADSTB#1 R5
DBI#0 E21DBI#1 G25DBI#2 P26DBI#3 V21
DBR# AE25
VCCIOPLLAD20
VCCSENSEA5
VCCAAE23
VC
CV
IDA
F4
THERMTRIP#A2
PROCHOT# C3MCERR# V6
SLP# AB26VSSAAD22
VSSSENSEA4
VID
PW
RG
DA
D2
VID
5A
D3
NC5 AE21NC4 AF24NC3 AF25
VCCVIDLBAF3
R541 2.43K_0603_1%1 2
R54754.9_0603_1%1 2
R530 56_0402_5%1 2
L36 LQG21F4R7N00_08051 2
R529 56_0402_5%1 2
R542 1K_0402_5%1 2
R514
@0_0402_5%
1 2
C547
220P_0402_25V8K
1
2
RP136 56_0804_8P4R_5%1 82 73 64 5
R520 0_0402_5% 1 2
R527 56_0402_5%1 2
R518 300_0402_5%1 2
R552 150_0402_5%1 2
RP94 1K_1206_8P4R_5%18273645
R519 56_0402_5%1 2
R543 1K_0402_5%1 2
+C544
33U_D2_8M_R35
1
2
R53951.1_0402_1%
12
R54654.9_0603_1%1 2
R10170_0402_5%1 2
R558
100_0402_1%
12
R515 56_0402_5%1 2
R556 47_0402_5%12
R517 130_0402_5%1 2
C932
0.1U_0402_10V6K
1
2
Q95MMBT3904_SOT23
2
31
R513 56_0402_5%1 2
R55349.9_0402_1%
12
R9934.7K_0402_5%
12
Q96MMBT3904_SOT23
2
31
R990 56_0402_5%1 2
R54051.1_0402_1%
12
U32A
SN74LVC14APWLE_TSSOP14
O 2I1
P14
G7
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
Title
Size Document Number R ev
Date: Sheet o f
LA-1811 0.7
CPU Decoupling
6 66, 07星期四 八月 , 2003
Compal Electronics, Inc.
Place 11 North of Socket(Stuff 6)
Place 12 Inside Socket(Stuff all)
Place 9 South of Socket(Unstuff all)
Place Inside Socket around the edge
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
+C178
470U_D2_2.5VM
1
2
C15922U_1206_16V4Z
1
2
C14322U_1206_16V4Z
1
2
+C180
470U_D2_2.5VM
1
2
C16222U_1206_16V4Z
1
2
C172
0.22U_0603_10V7K
1
2
C13222U_1206_16V4Z
1
2
C170
0.22U_0603_10V7K
1
2
C13922U_1206_16V4Z
1
2
C168
0.22U_0603_10V7K
1
2
+C183
@470U_D2_2.5VM
1
2
C13422U_1206_16V4Z
1
2
C15422U_1206_16V4Z
1
2
C15322U_1206_16V4Z
1
2
C15122U_1206_16V4Z
1
2
C14522U_1206_16V4Z
1
2
C13522U_1206_16V4Z
1
2
C14622U_1206_16V4Z
1
2
C173
0.22U_0603_10V7K
1
2
+C163
470U_D2_2.5VM
1
2
C15622U_1206_16V4Z
1
2
+C179
470U_D2_2.5VM
1
2
C14122U_1206_16V4Z
1
2
C14722U_1206_16V4Z
1
2
+C167
470U_D2_2.5VM
1
2
C15222U_1206_16V4Z
1
2
C15522U_1206_16V4Z
1
2
C15822U_1206_16V4Z
1
2
C13822U_1206_16V4Z
1
2
+C165
470U_D2_2.5VM
1
2
C13122U_1206_16V4Z
1
2
C171
0.22U_0603_10V7K
1
2
+C176
@330U_D2E_2.5VM
1
2
C14222U_1206_16V4Z
1
2
C13622U_1206_16V4Z
1
2
C16122U_1206_16V4Z
1
2
+C182
470U_D2_2.5VM
1
2
C15722U_1206_16V4Z
1
2
C15022U_1206_16V4Z
1
2
+C166
@330U_D2E_2.5VM
1
2
C14022U_1206_16V4Z
1
2
C14922U_1206_16V4Z
1
2
C16022U_1206_16V4Z
1
2
+C164
470U_D2_2.5VM
1
2
C13322U_1206_16V4Z
1
2
C14822U_1206_16V4Z
1
2
+C174
470U_D2_2.5VM
1
2
+C177
470U_D2_2.5VM
1
2
C14422U_1206_16V4Z
1
2
C13722U_1206_16V4Z
1
2
+C175
470U_D2_2.5VM
1
2
+C181
470U_D2_2.5VM
1
2
C169
0.22U_0603_10V7K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_THERMDA
H_THERMDC
H_THERMDA
H_THERMDC
EN_DFAN2 EN_FAN2
FAN1 FAN2
H_THERMTRIP#
EC_SMC_2 <46>
EC_SMD_2 <46>
H_THERMDA <5>
H_THERMDC <5>
EN_FAN1<46> EN_FAN2<46>
FANSPEED2<46>FANSPEED1<46>
H_THERMTRIP#<5>
MAINPWON <50,51,53>
+3VALW
+VCC_CORE
+5VS
+3VS
+5VS
+3VS
+12VALW
Title
Size Document Number R ev
Date: Sheet o f
LA-1811 0.7
CPU Thermal Sensor&FAN CTRL
7 66, 07星期四 八月 , 2003
Compal Electronics, Inc.
Thermal Sensor ADM1032AR
Address:1001_100X
W= 15mil
FAN CONN.1 FAN CONN. 2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C265
10U_0805_10V4Z
1
2
R91610K_0402_5%
12
R917 8.2K_0402_5%1 2
R920 10K_0402_5%1 2
C840
0.1U_0402_10V6K1
2
JP11
ACES_85205-0300
123
R918 8.2K_0402_5%1 2
C253
2200P_0402_25V7K
1
2
C
BE
Q90
FMMT619_SOT231
2
3
JP10
ACES_85205-0300
123
U10A
LM358A_SO8
+IN3
-IN2 OUT 1
P8
G4
R283
@10K_0402_5%
12
C856
@1000P_0402_16V7K
1
2
C855
@1000P_0402_16V7K
1
2
C
BE
Q91
FMMT619_SOT231
2
3
D25
1N4148_SOD80
12
C251
0.1U_0402_10V6K1
2
C907
@1000P_0402_16V7K
1
2
Q172SC2411K_SC59
C 1
E3
B2
R913 100_0402_5%1 2D68
1SS355_SOD323
12
D67
1SS355_SOD323
12
C83810U_0805_16V4Z
12
C266
10U_0805_10V4Z
1
2
R286 300_0402_5%12 C256 @1U_0603_10V6K12
R919 10K_0402_5%1 2
C839
10U_0805_16V4Z
1
2
R91510K_0402_5%
12
D26
1N4148_SOD80
12
R914 100_0402_5%1 2
U8
ADM1032AR_SOP8
VDD1
ALERT# 6
THERM#4 GND 5
D+2
D-3
SCLK 8
SDATA 7
C841
0.1U_0402_10V6K1
2
C908@1000P_0402_16V7K
1
2
U10B
LM358A_SO8
+IN5
-IN6 OUT 7
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_D#[ 0..63]
H_REQ#[0..4]
H_A#[3..31]
H_D#62
H_DSTBP#3
H_D#37
H_D#59
H_DINV#2
H_D#39
H_D#54
H_D#11
H_DSTBN#2
H_D#12
H_D#46
H_D#63
H_D#8
H_DSTBP#2
H_D#48
H_D#50
H_DSTBN#0
H_D#19
H_D#47
H_D#0
H_D#6
H_D#13
H_D#5
H_D#9
H_D#18
H_D#4
H_D#28
H_D#57
H_D#40
H_D#36
H_DSTBP#1
H_D#43
H_D#33
H_D#24H_D#25
H_D#34
H_D#29
H_D#55
H_DSTBN#3
H_DINV#0
H_D#16
H_D#51
H_D#2
H_D#45
H_D#31
H_D#23
H_D#52
H_D#3
H_D#20
H_D#17
H_D#7
H_DINV#3
H_D#22
H_D#15
H_D#30
H_DSTBP#0
H_D#32
H_D#58
H_D#10
H_D#1
H_D#35
H_D#21
H_D#41
H_D#44
H_D#42
H_D#53
H_D#60
H_D#27
H_D#38
H_DSTBN#1
H_D#56
H_D#49
H_D#26
H_D#61
H_DINV#1
H_D#14
H_A#28
H_ADSTB#1
H_A#7
H_A#30
H_A#3
H_A#20
H_A#29
H_A#6
H_A#22
H_A#18
H_A#24
H_REQ#3
H_A#23
H_BNR#
H_A#9H_A#8
H_A#25
H_A#11
H_DEFER#
H_A#10
H_ADSTB#0
H_A#4
H_DRDY#
H_LOCK#
H_A#17
H_TRDY#
H_A#27
H_A#16
H_A#13
H_HIT#
H_ADS#
H_RS#1
H_RESET#
H_DBSY#
H_A#5
COMP_P
H_A#15H_A#14
H_A#26
H_A#31
H_HITM#
H_RS#2
H_BPRI#
H_REQ#1
NB_GTLREF
H_A#19
H_REQ#2
H_A#21
H_REQ#4
H_REQ#0
H_RS#0
H_A#12
H_BR0#
COMP_N
CPVSS
CPVDD
H_D#[0..63] <4>
H_A#[3..31] <4>
H_REQ#[0..4] <4>
H_DSTBP#0 <5>
H_DSTBN#3 <5>
H_DSTBN#0 <5>
H_DSTBP#3 <5>
H_DSTBP#2 <5>H_DSTBN#2 <5>
H_DSTBP#1 <5>H_DSTBN#1 <5>
H_TRDY#<5>
H_RS#1<5>
H_DEFER#<4>
H_HITM#<4>H_HIT#<4>
NB_PWRGD<48>
H_ADSTB#1<5>
H_DRDY#<5>
H_ADSTB#0<5>
H_RS#2<5>
H_LOCK#<4>
H_DBSY#<5>
H_BPRI#<4>H_BNR#<4>
H_RS#0<5>
H_RESET#<5,26>
NB_RST#<17,26,39>
H_ADS#<4>
H_BR0#<4>
H_DINV#3 <5>
H_DINV#0 <5>
H_DINV#2 <5>
H_DINV#1 <5>
SUS_STAT#<27>
+VCC_CORE
+VCC_CORE
+1.8VS
+VCC_CORE
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
ATI RC300M-AGTL+
8 66, 07, 2003星期四 八月
Compal Electronics, Inc.
C363 CLOSE TO Ball W28
PLACE CLOSE TO U27 BallW28, USE 20/20WIDTH/SPACE
Note: PLACE CLOSE TO RC300M,USE 10/10 WIDTH/SPACE
L
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
--> 412_0402_1%
R383
49.9_0402_1%
12
C372
0.1U_0402_10V6K
1
2
R381 24.9_0402_1%1 2
C366
0.1U_0402_10V6K
1
2
R384
100_0402_1%
12
C368
0.1U_0402_10V6K
1
2
C369
0.1U_0402_10V6K
1
2
L34
HB-1M2012-121JT03_08051 2
C362
1U_0603_10V6K
1
2
C36422U_1206_16V4Z_V1
1
2
R382 49.9_0402_1%1 2
C371
0.1U_0402_10V6K
1
2
C365
0.1U_0402_10V6K
1
2
R385
4.7K_0402_5%
12
C361
1U_0603_10V6K1 2
C363
220P_0402_25V8K
1
2
R380 412_0402_1%1 2
C370
0.1U_0402_10V6K
1
2
C9740.1U_0402_10V6K
12
C367
0.1U_0402_10V6K
1
2
PART 1 OF 6
PEN
TIU
MIV
AD
DR
. GR
OU
P 1
AD
DR
. GR
OU
P 0
CO
NTR
OL
MIS
C.
DA
TA G
RO
UP
0D
ATA
GR
OU
P 1
DA
TA G
RO
UP
2D
ATA
GR
OU
P 3
AGTL
+ I/F
U27A
216RC300M_BGA_718
CPU_ADS#L27CPU_BNR#K25CPU_BPRI#H26
CPU_D0# L30CPU_D1# K29CPU_D2# J29CPU_D3# H28CPU_D4# K28CPU_D5# K30CPU_D6# H29CPU_D7# J28CPU_D8# F28CPU_D9# H30
CPU_D10# E30CPU_D11# D29CPU_D12# G28CPU_D13# E29CPU_D14# D30CPU_D15# F29
CPU_D16# B26CPU_D17# C30CPU_D18# A27CPU_D19# B29CPU_D20# C28CPU_D21# C29CPU_D22# B28CPU_D23# D28CPU_D24# D26CPU_D25# B27CPU_D26# C26CPU_D27# E25CPU_D28# E26CPU_D29# A26CPU_D30# B25CPU_D31# C25
CPU_D32# F24CPU_D33# D24CPU_D34# E23CPU_D35# E24CPU_D36# F23CPU_D37# C24CPU_D38# B24CPU_D39# A24CPU_D40# F21CPU_D41# A23CPU_D42# B23CPU_D43# C22CPU_D44# B22CPU_D45# C21CPU_D46# E21CPU_D47# D22
CPU_D48# B21CPU_D49# F20CPU_D50# A21CPU_D51# C20CPU_D52# E20CPU_D53# D20
CPU_A3#M28CPU_A4#P25
CPU_D54# A20CPU_D55# D19CPU_D56# C18CPU_D57# B20CPU_D58# E18CPU_D59# B19CPU_D60# D18CPU_D61# B18CPU_D62# C17CPU_D63# A18
CPU_ADSTB0#R27
CPU_ADSTB1#T29
CPU_BR0#F25 CPU_DBSY#G27
CPU_DEFER#J27CPU_DRDY#L26
CPU_LOCK#K26
CPU_TRDY#F26
CPU_REQ0#M29CPU_REQ1#N25CPU_REQ2#R26CPU_REQ3#L28CPU_REQ4#L29
CPU_HIT#J26CPU_HITM#H25
CPU_RS0#J25 CPU_RS1#G26 CPU_RS2#G25
CPU_DSTBN3# E19
CPU_DSTBN2# E22
CPU_DSTBN1# D27
CPU_DSTBN0# G30
CPU_DSTBP3# F18
CPU_DSTBP2# F22
CPU_DSTBP1# E27
CPU_DSTBP0# G29
CPU_DBI3# F19
CPU_DBI2# D23
CPU_DBI1# A28
CPU_DBI0# E28
CPU_CPURSET#A17
CPU_COMP_PW29
CPU_COMP_NV28
CPVSSJ23
CPU_VREFW28
THERMALDIODE_NY29THERMALDIODE_PY28
TESTMODEB17
CPVDDH23
SYSRESET#AG5POWERGOODC7
CPU_A5#M25CPU_A6#N29CPU_A7#N30CPU_A8#M26CPU_A9#N28CPU_A10#P29CPU_A11#P26CPU_A12#R29CPU_A13#P30CPU_A14#P28CPU_A15#N26CPU_A16#N27
CPU_A17#U30CPU_A18#T30CPU_A19#R28CPU_A20#R25CPU_A21#U25CPU_A22#T28CPU_A23#V29CPU_A24#T26CPU_A25#U29CPU_A26#U26CPU_A27#V26CPU_A28#T25CPU_A29#V25CPU_A30#U27CPU_A31#U28
SUS_STAT#AH5 CPU_RSET#A9
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MPVSS
DDRA_DQ44
DDRA_DQ48DDRA_DQ49
DDRA_DQ54
DDRA_DQ59
DDRA_DM0
DDRA_DM3
DDRA_ADD15
DDRA_CLK3
MEN_COMP
DDRA_DQ3
DDRA_DQ33
DDRA_DQ52
DDRA_ADD4
DDRA_ADD8
DDRA_DM5
DDRA_CLK1
DDRA_DQ18
DDRA_DQ21
DDRA_DQ23
DDRA_ADD10
DDRA_DM6
DDRA_CLK4
DDRA_DQ6
DDRA_DQ13
DDRA_DQ38
DDRA_DQ42DDRA_DQ43
DDRA_DQ47
DDRA_DQS1
DDRA_DQ57
DDRA_ADD12
DDRA_CLK0
DDRA_CLK1#
DDRA_DQ7
DDRA_DQ15
DDRA_DQ17
DDRA_DQ24DDRA_DQ25
DDRA_DQ35
DDRA_DQ40DDRA_DQ41
DDRA_DQ60
DDRA_DQ63
DDRA_ADD6
DDRA_ADD9
DDRA_RAS#DDRA_CAS#
DDRA_DQS4
MPVDD
DDRA_CLK3#
DDRA_CLK4#
DDRA_DQ9
DDRA_DQ62
DDRA_ADD5
DDRA_DM4
DDRA_DQ4
DDRA_DQ32
DDRA_DQ34
DDRA_DQ53
DDRA_DQ56
DDRA_CKE_R0DDRA_CKE_R1
DDRA_DQ11
DDRA_DQ14
DDRA_DQ16
DDRA_DQ37
DDRA_DQ55
DDRA_DQS5
DDRA_CLK0#
DDRA_DQ20
DDRA_DQ26DDRA_DQ27
DDRA_DQ45
DDRA_ADD2
DDRA_ADD7
DDRA_DQ2
DDRA_DQ5
DDRA_DQ51
DDRA_DQ61
DDRA_ADD3
DDRA_ADD13
DDRA_DQS0
DDRA_DQ0DDRA_DQ1
DDRA_DQ8
DDRA_DQ19
DDRA_DQ12
DDRA_DQ28
DDRA_DQ39
DDRA_DQ46
DDRA_ADD14
DDRA_DM2
DDRA_WE#
DDRA_DQS2
DDRA_DQ30
DDRA_DQ50
DDRA_DQ58
DDRA_ADD1
DDRA_ADD11
DDRA_DM7
DDRA_DQS6
DDRA_DQ10
DDRA_DQ22
DDRA_DQ29
DDRA_DQ36
DDRA_DM1
DDRA_DQS3
DDRA_DQ31
DDRA_ADD0
DDRA_DQS7
DDRA_CKE_R2DDRA_CKE_R3
DDRA_CS#0DDRA_CS#1
DDRA_CS#3DDRA_CS#2
DDR_VREF
DDRA_DQ23
DDRA_SDQ22
DDRA_SDQ23DDRA_DQ19
DDRA_DQ22DDRA_SDQ18
DDRA_SDQ19
DDRA_DQ18
DDRA_ADD[0..15]
DDRA_SDQS[0..7]
DDRA_SDQ[0..63]
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ4
DDRA_SDQ5DDRA_DQ5DDRA_DQ1
DDRA_DQ4DDRA_DQ0
DDRA_DQ30
DDRA_DQ29DDRA_DQ25
DDRA_DQS3 DDRA_SDQS3
DDRA_DQ28
DDRA_DQ31
DDRA_SDQ30
DDRA_DQ27
DDRA_SDQ28
DDRA_SDQ31
DDRA_DQ24
DDRA_SDQ29
DDRA_DQ26
DDRA_SDQ24
DDRA_SDQ27
DDRA_SDQ26
DDRA_DM3 DDRA_SDM3
DDRA_SDQ25
DDRA_DM0
DDRA_DQS0 DDRA_SDQS0
DDRA_SDM0
DDRA_DQ9
DDRA_DQ10
DDRA_DQ15DDRA_DQ11
DDRA_DQ8DDRA_DQ12
DDRA_DQ14
DDRA_DQ13
DDRA_DM1
DDRA_DQS1
DDRA_SDM1
DDRA_SDQS1
DDRA_SDQ9
DDRA_SDQ8
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ15
DDRA_SDQ14
DDRA_SDM[0..7]
DDRA_SDM5
DDRA_SDQS6DDRA_DQS6
DDRA_DM7
DDRA_DQ51
DDRA_DQ54
DDRA_SDQS7
DDRA_DQ50
DDRA_SDM7
DDRA_DQS5
DDRA_SDM4
DDRA_DQS7
DDRA_SDQS4
DDRA_SDQ50
DDRA_SDQS5
DDRA_SDQ54
DDRA_DM4
DDRA_SDQ51DDRA_DQ55
DDRA_DM5
DDRA_SDQ55
DDRA_DQS4
DDRA_SDM6DDRA_DM6
DDRA_DQ49 DDRA_SDQ49DDRA_SDQ53DDRA_DQ53
DDRA_SDQ48DDRA_DQ48DDRA_DQ52 DDRA_SDQ52
DDRA_SDQ63DDRA_DQ63DDRA_DQ59 DDRA_SDQ59
DDRA_SDQ62DDRA_DQ62DDRA_DQ58 DDRA_SDQ58
DDRA_SDQ61DDRA_DQ61DDRA_DQ57 DDRA_SDQ57
DDRA_SDQ56DDRA_DQ56DDRA_DQ60 DDRA_SDQ60
DDRA_SDQ43DDRA_SDQ47DDRA_DQ47
DDRA_DQ43
DDRA_SDQ46DDRA_SDQ42
DDRA_DQ46DDRA_DQ42
DDRA_DQ45DDRA_DQ41
DDRA_SDQ45DDRA_SDQ41
DDRA_SDQ40DDRA_SDQ44DDRA_DQ44
DDRA_DQ40
DDRA_DQ39DDRA_DQ35 DDRA_SDQ35
DDRA_SDQ39
DDRA_SDQ38DDRA_SDQ34
DDRA_DQ38DDRA_DQ34
DDRA_DQ33DDRA_DQ37
DDRA_SDQ33DDRA_SDQ37
DDRA_SDQ32DDRA_SDQ36
DDRA_DQ32DDRA_DQ36
DDRA_SDQ21DDRA_SDQ17
DDRA_DQ21DDRA_DQ17
DDRA_SDQ16DDRA_SDQ20
DDRA_DQ16DDRA_DQ20
DDRA_DM2 DDRA_SDM2
DDRA_SDQS2
DDRA_DQ2
DDRA_DQ3
DDRA_DQ6
DDRA_DQ7DDRA_SDQ3DDRA_SDQ7
DDRA_SDQ2DDRA_SDQ6
DDRA_DQS2
DDRA_CLK0<14>
DDRA_CLK3<15>
DDRA_CLK1#<14>
DDRA_CLK4<15>
DDRA_CLK3#<15>
DDRA_CLK1<14>
DDRA_CLK4#<15>
DDRA_CLK0#<14>
DDRA_SDQ[0..63] <14,15,16>
DDRA_SDQS[0..7] <14,15,16>
DDRA_SDM[0..7] <14,15,16>
DDRA_ADD[0..15] <14,15,16>
DDRA_CKE_R0<14,16>DDRA_CKE_R1<14,16>DDRA_CKE_R2<15,16>DDRA_CKE_R3<15,16>
DDRA_CS#0<14,16>DDRA_CS#1<14,16>DDRA_CS#2<15,16>DDRA_CS#3<15,16>
DDRA_RAS#<14,15,16>DDRA_CAS#<14,15,16>
DDRA_WE#<14,15,16>
+2.5V
+1.8VS
+2.5V+2.5V
DDR_VREF
+2.5V
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
ATI RC300M-DDR I/F
9 66, 07, 2003星期四 八月
Compal Electronics, Inc.
DDR_VREF trace width of20mils and space20mils(min)
L
Group 6 sweep Group 7
Place these resistorclosely DIMM0,all trace lengthMax=0.75"
Layout note
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
RP64
0_0404_4P2R_5%
1 42 3
C381
0.1U_0402_10V6K
1
2
RP46
0_0404_4P2R_5%
1 42 3
R405 49.9_0402_1%1 2
RP31
0_0404_4P2R_5%
1 42 3
RP52
0_0404_4P2R_5%
1 42 3
RP61
0_0404_4P2R_5%
1 42 3
C376
0.1U_0402_10V6K1
2
C384
0.1U_0402_10V6K
1
2
C385
0.1U_0402_10V6K
1
2
C374 0.47U_0603_16V7K1 2
RP63
0_0404_4P2R_5%
1 42 3
C860
@0.1U_0402_10V6K
1
2
RP30
0_0404_4P2R_5%
1 42 3
RP47
0_0404_4P2R_5%
1 42 3
RP36
0_0404_4P2R_5%
1 42 3
RP33
0_0404_4P2R_5%
1 42 3
C380
0.1U_0402_10V6K
1
2
RP55
0_0404_4P2R_5%
1 42 3
C388
0.1U_0402_10V6K
1
2
R412 0_0402_5%12
RP34
0_0404_4P2R_5%
1 42 3
R403 0_0402_5%12
C386
0.1U_0402_10V6K
1
2
RP48
0_0404_4P2R_5%
1 42 3
RP51
0_0404_4P2R_5%
1 42 3
C382
0.1U_0402_10V6K
1
2
C859
@0.1U_0402_10V6K
1
2
R413 0_0402_5%12
RP45
0_0404_4P2R_5%
1 42 3
R415 0_0402_5%12
R395 0_0402_5%12
RP37
0_0404_4P2R_5%
1 42 3
R387 0_0402_5%12
+C378
100U_D2_10VM
1
2
R404 0_0402_5%12
R406 0_0402_5%12
R409
1K_0603_1%
12
R408
1K_0603_1%
12
RP44
0_0404_4P2R_5%
1 42 3
R416 0_0402_5%12
R394 0_0402_5%12
R398 0_0402_5%12
C858
@0.1U_0402_10V6K
1
2
C383
0.1U_0402_10V6K
1
2
RP62
0_0404_4P2R_5%
1 42 3
RP58
0_0404_4P2R_5%
1 42 3
RP54
0_0404_4P2R_5%
1 42 3
RP59
0_0404_4P2R_5%
1 42 3
RP40
0_0404_4P2R_5%
1 42 3
R389 0_0402_5%12
RP43
0_0404_4P2R_5%
1 42 3
R386 0_0402_5%12
MEM
I/F
PART 2 OF 6
U27B
216RC300M_BGA_718
MEM_DQ0 AG6MEM_DQ1 AJ7MEM_DQ2 AJ9MEM_DQ3 AJ10MEM_DQ4 AJ6MEM_DQ5 AH6MEM_DQ6 AH8MEM_DQ7 AH9MEM_DQ8 AE7MEM_DQ9 AE8
MEM_DQ10 AE12MEM_DQ11 AF12MEM_DQ12 AF7MEM_DQ13 AF8MEM_DQ14 AE11MEM_DQ15 AF11MEM_DQ16 AJ12MEM_DQ17 AH12MEM_DQ18 AH14MEM_DQ19 AH15MEM_DQ20 AH11MEM_DQ21 AJ13MEM_DQ22 AJ15MEM_DQ23 AJ16MEM_DQ24 AF18MEM_DQ25 AG20MEM_DQ26 AG21MEM_DQ27 AF22MEM_DQ28 AF19MEM_DQ29 AF20MEM_DQ30 AE22MEM_DQ31 AF23MEM_DQ32 AJ21MEM_DQ33 AJ22MEM_DQ34 AJ24MEM_DQ35 AK25MEM_DQ36 AH21MEM_DQ37 AH22MEM_DQ38 AH24MEM_DQ39 AJ25MEM_DQ40 AK26MEM_DQ41 AK27MEM_DQ42 AJ28MEM_DQ43 AH29MEM_DQ44 AH25MEM_DQ45 AJ26MEM_DQ46 AJ29MEM_DQ47 AH30MEM_DQ48 AF29MEM_DQ49 AE29MEM_DQ50 AB28MEM_DQ51 AA28MEM_DQ52 AE28MEM_DQ53 AD28MEM_DQ54 AC29MEM_DQ55 AB29MEM_DQ56 AC26MEM_DQ57 AB25MEM_DQ58 Y26MEM_DQ59 W26MEM_DQ60 AE26MEM_DQ61 AD26MEM_DQ62 AA26MEM_DQ63 Y27
MEM_DDRVREF AK20
MEM_A0AH19MEM_A1AJ17MEM_A2AK17MEM_A3AH16MEM_A4AK16MEM_A5AF17MEM_A6AE18MEM_A7AF16MEM_A8AE17MEM_A9AE16MEM_A10AJ20MEM_A11AG15MEM_A12AF15MEM_A13AE23MEM_A14AH20
MEM_DM0AH7MEM_DM1AF10MEM_DM2AJ14MEM_DM3AF21MEM_DM4AH23MEM_DM5AK28MEM_DM6AD29MEM_DM7AB26
MEM_RAS#AF24MEM_CAS#AF25
MEM_WE#AE24
MEM_CKE0AF13
MEM_DQS0AJ8MEM_DQS1AF9MEM_DQS2AH13MEM_DQS3AE21MEM_DQS4AJ23MEM_DQS5AJ27MEM_DQS6AC28MEM_DQS7AA25
MEM_CK0#AH10 MEM_CK0AK10
MEM_CS#0AH26MEM_CS#1AH27MEM_CS#2AF26MEM_CS#3AG27
MPVDDAC18
MPVSSAD18
MEM_A15AE25
MEM_CKE1AE13
MEM_CK1AH18MEM_CK1#AJ19
MEM_CK2AG30MEM_CK2#AG29
MEM_CK3AK11MEM_CK3#AJ11
MEM_CK4AH17MEM_CK4#AJ18
MEM_CK5AF28MEM_CK5#AG28
MEM_CKE2AG14MEM_CKE3AF14
MEM_CAP1 AF6
MEM_CAP2 AA29
MEM_COMP AK19
RP41
0_0404_4P2R_5%
1 42 3
RP49
0_0404_4P2R_5%
1 42 3
RP57
0_0404_4P2R_5%
1 42 3
L35HB-1M2012-121JT03_0805
1 2
C391
0.1U_0402_10V6K
1
2
RP28
0_0404_4P2R_5%
1 42 3
RP50
0_0404_4P2R_5%
1 42 3
R388 0_0402_5%12
C387
0.1U_0402_10V6K
1
2
RP56
0_0404_4P2R_5%
1 42 3
C375
1U_0603_10V6K
1 2
C379
0.1U_0402_10V6K
1
2
C857
0.1U_0402_10V6K
1
2
C373 0.47U_0603_16V7K1 2
R407 0_0402_5%12
RP27
0_0404_4P2R_5%
1 42 3
R397 0_0402_5%12
RP60
0_0404_4P2R_5%
1 42 3
C390
0.1U_0402_10V6K
1
2
C389
0.1U_0402_10V6K
1
2
C861
@0.1U_0402_10V6K
1
2
RP53
0_0404_4P2R_5%
1 42 3
C377
0.1U_0402_10V6K1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
A_AD[0..31]
A_CBE#[0..3]
AGP_AD2
AGP_SBA2
AGP_WBF#
AGP_AD27
AGP_AD18
AGP_AD4
AGP_SBSTB#
AGP_AD13
AGP_PAR
AGP_SBA6
AGP_SBA1
AGP_AD25
AGP_AD20
AGP_AD7AGP_AD6
AGP_ST2
AGP_AD28
AGP_CBE#3
AGP_AD31
AGP_AD14
AGP_AD3
AGP_DBI_LOAGP_RBF#
AGP_SBA4
AGP_AD12
AGP_AD1
AGP_DEVSEL#
AGP_ADSTB1
AGP_SBSTB
AGP_AD26
AGP_AD10
AGP_ST0
AGP_ADSTB1#
AGP_AD29
AGP_AD22
AGP_DBI_HI/PIPE#
AGP_STOP#
AGP_ADSTB0
AGP_AD19
AGP_AD9
AGP_ST1
AGP_SBA7
AGP_CBE#0
AGP_AD23
AGP_AD8
AGP_AD16
AGP_AD11
AGP_SBA5
AGP_SBA3
AGP_FRAME#
AGP_CBE#2
AGP_ADSTB0#
AGP_AD5
AGP_AD0
AGP_IRDY#
AGP_CBE#1
AGP_AD21
AGP_AD17
AGP_SBA0
AGP_TRDY#
AGP_AD30
AGP_AD24
AGP_AD15
A_AD11
A_AD17
A_AD20
A_END#
A_AD27
A_AD6
A_DEVSEL#
A_AD26
A_AD24A_AD25
A_AD18
A_AD9
A_AD0
A_AD3
A_AD7
A_AD5
A_ACAT#
A_AD12
A_AD15
A_SBGNT#
A_AD1
A_AD13
A_AD16
A_AD30
A_AD22
A_AD29
AGP_GNT#
A_CBE#3
A_OFF#
A_AD31
A_AD8
A_SBREQ#
A_CBE#0A_CBE#1A_CBE#2
A_AD23
A_AD14
A_PAR
A_AD19
A_AD4
A_AD28
A_AD2
A_STROBE#
A_AD10
AGP_REQ#
A_AD21
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
LVDS_SSOUTAGP_SBA6
AGP_SBA7 LVDS_SSIN
AGPREF_8X
AGP_COMP
LVDS_SSOUT
LVDS_SSIN
AGP8X_DET#
DDC_DAT
DDC_CLK
AGP8X_DET#
AGPREF_8X
AGP_ST[0..2]
AGP_AD[0..31]
AGP_SBA[0..7]
AGP_CBE#[0..3]
AGP_SBA1
AGP_SBA0
A_AD[0..31]<13,26>
A_CBE#[0..3]<13,26>
AGP_RBF# <17>AGP_WBF# <17>
AGP_TRDY# <17>AGP_IRDY# <17>
AGP_FRAME# <17>
AGP_ADSTB1# <17>
AGP_ADSTB0# <17>
AGP_STOP# <17>
AGP_SBSTB# <17>AGP_SBSTB <17>
AGP_PAR <17>
AGP_ADSTB1 <17>
AGP_ADSTB0 <17>
AGP_DBI_HI/PIPE# <17>AGP_DBI_LO <17>
AGP_DEVSEL# <17>
AGP_GNT#<17>AGP_REQ#<17>
VREF_8X_IN<17>
A_DEVSEL#<26>
A_SBGNT#<26>
A_OFF#<26>
A_END#<26>
A_SBREQ#<26>
A_ACAT#<26>
A_PAR<13,26>A_STROBE#<26>
ENABLT# <17,25>
ENAVDD <17,25,46>
AGP_BUSY# <17,27>
AGP_STP# <17,27>
SSOUT <17>
DDC_DAT <17,25>
DDC_CLK <17,25>
PCI_PIRQA#<17,26,31,35,36>
AGP8X_DET#<17>
SSIN <17>
AGP_AD[0..31] <17>
AGP_SBA[0..7] <17>
AGP_ST[0..2] <17>
AGP_CBE#[0..3] <17>
+1.5VS +3VS
+3VS
+3VS
+3VS
+1.5VS
+1.5VS
+1.5VS+1.5VS
+1.5VS
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
ATI RC300M-AGP, ALINK BUS
10 66, 07, 2003星期四 八月
Compal Electronics, Inc.
AGPAND LVDS MUXED SIGNALS
?
PLACE CLOSE TOCONNECTOR
8X(M9+M10@)Ra 169_0402_1%
324_0402_1%
100_0402_1%
S1
S0
LVDS SPREAD SPECTRUM
Note: PLACE CLOSE TO U27 (NB RC300M)L
4X(NAGP@)
RbRc
52.1_0402_1%
Ra
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ATI request
1K_0402_1%
1K_0402_1%
Rb
Rc
Note: PLACE CLOSE TO U27 (NB RC300M)L
PIR BOM 92.06.23
C553
0.1U_0402_10V6K
1
2
C550
0.1U_0402_10V6K
1 2
R945
NAGP@47K_0402
12
C557
0.1U_0402_10V6K
1
2
C573
0.1U_0402_10V6K
1
2
C943
0.1U_0402_10V6K
1
2
R560 NAPG@0_0402_5%1 2
R573@0_0402_5%
12
C556
0.1U_0402_10V6K
1
2
C935
@0.01U_0402_16V7Z
1
2
U33
@SM561BS_SO8
Xin/CLK1
Xout 8S07
S16
VDD
2
SSCLK 4
SSCC 5
VSS
3
C570
0.1U_0402_10V6K
1
2
C567
0.1U_0402_10V6K
1
2
C864
@0.01U_0402_16V7Z
1
2
C572
0.1U_0402_10V6K
1
2
C560
0.1U_0402_10V6K
1
2
C951
@0.01U_0402_16V7Z
1
2
R567
@0_0402_5%
12
C938
0.1U_0402_10V6K
1
2
C950
@0.01U_0402_16V7Z
1
2
C942
0.1U_0402_10V6K
1
2
C948
@0.01U_0402_16V7Z
1
2
C574
0.1U_0402_10V6K
1
2
R576
324_0402_1%
12
R1086
@0_0402_5%
12
C554
0.1U_0402_10V6K
1
2
R1144 @0_0402_5%
1 2
R563 NAPG@0_0402_5%1 2
C934
@0.01U_0402_16V7Z
1
2
C578
0.1U_0402_10V6K
1
2
C947
@0.01U_0402_16V7Z
1
2
C555
0.1U_0402_10V6K
1
2
R577
100_0402_1%
12
C939
0.1U_0402_10V6K
1
2
C945
0.1U_0402_10V6K
1
2
C568
0.1U_0402_10V6K
1
2
R564 @0_0402_5%1 2
R565 @0_0402_5%1 2
+C551
47U_B_6.3VM
1
2
C952
@10P_0402_25V8K
1
2
R1088@0_0402_5%
12
R572
@0_0402_5%
12
R574
@0_0402_5%
12
C936
@0.01U_0402_16V7Z
1
2
C562
0.1U_0402_10V6K
1
2
C940
0.1U_0402_10V6K
1
2
R569
@0_0402_5%
12
C946
0.1U_0402_10V6K
1
2
C577
0.1U_0402_10V6K
1
2
C569
0.1U_0402_10V6K
1
2
R5708.2K_0402_5%1 2
C549
@0.1U_0402_10V6K
C563
0.1U_0402_10V6K
1
2
C561
0.1U_0402_10V6K
1
2
C564
0.1U_0402_10V6K
1
2
C566
0.1U_0402_10V6K
1
2
C576
0.1U_0402_10V6K
1
2
C571
0.1U_0402_10V6K
1
2
C559
0.1U_0402_10V6K
1
2
C632
10U_0805_10V4Z
1
2
C941
0.1U_0402_10V6K
1
2
C575
0.1U_0402_10V6K
1
2
R561 NAPG@0_0402_5%1 2
L38@BLM21P300S_0805
1 2
C548
@10U_0805_6.3V6M
R562 NAPG@0_0402_5%1 2
C933
@0.01U_0402_16V7Z
1
2
C949
@0.01U_0402_16V7Z
1
2
R568
@0_0402_5%
12
R994 NAPG@0_0402_5%1 2
C558
0.1U_0402_10V6K
1
2
+C552
47U_B_6.3VM
1
2
C944
0.1U_0402_10V6K
1
2
R575
169_0402_1%
1 2
R1005 0_0402_5%1 2
C565
0.1U_0402_10V6K
1
2
R1087
@0_0402_5%1 2
C937
0.1U_0402_10V6K
1
2
PART 3 OF 6
PCI B
us 0
/ A-
Link
I/F
PCI B
US
1 / A
GP
Bus
(GPI
O ,
TMD
S , Z
VPor
t)
U27C
216RC300M_BGA_718
ALINK_AD0AK5ALINK_AD1AJ5ALINK_AD2AJ4ALINK_AD3AH4ALINK_AD4AJ3ALINK_AD5AJ2ALINK_AD6AH2ALINK_AD7AH1ALINK_AD8AG2ALINK_AD9AG1ALINK_AD10AG3ALINK_AD11AF3ALINK_AD12AF1ALINK_AD13AF2ALINK_AD14AF4ALINK_AD15AE3ALINK_AD16AE4ALINK_AD17AE5ALINK_AD18AE6ALINK_AD19AC2ALINK_AD20AC4ALINK_AD21AB3ALINK_AD22AB2ALINK_AD23AB5ALINK_AD24AB6ALINK_AD25AA2ALINK_AD26AA4ALINK_AD27AA5ALINK_AD28AA6ALINK_AD29Y3ALINK_AD30Y5ALINK_AD31Y6
ALINK_CBE#0AG4ALINK_CBE#1AE2ALINK_CBE#2AC3ALINK_CBE#3AA3
PCI_PAR/ALINK_NCAD5PCI_FRAME#/ALINK_STROBE#AC6PCI_IRDY#/ALINK_ACAT#AC5PCI_TRDY#/ALINK_END#AD2INTA#W4ALINK_DEVSEL#AD3PCI_STOP#/ALINK_OFF#AD6
ALINK_SBREQ#W5ALINK_SBGNT#W6
PCI_REQ#0/ALINK_NCV5PCI_GNT#0/ALINK_NCV6
AGP_AD0/TMD2_HSYNC Y2AGP_AD1/TMD2_VSYNC W3
AGP_AD2/TMD2_D1 W2AGP_AD3/TMD2_D0 V3AGP_AD4/TMD2_D3 V2AGP_AD5/TMD2_D2 V1AGP_AD6/TMD2_D5 U1AGP_AD7/TMD2_D4 U3AGP_AD8/TMD2_D6 T2AGP_AD9/TMD2_D9 R2
AGP_AD10/TMD2_D8 P3AGP_AD11/TMD2_D11 P2AGP_AD12/TMD2_D10 N3
AGP_AD13 N2AGP_AD14 M3AGP_AD15 M2
AGP_AD16/TMD1_VSYNC L1AGP_AD17/TMD1_HSYNC L2
AGP_AD18/TMD1_DE K3AGP_AD19/TMD1_D0 K2AGP_AD20/TMD1_D1 J3AGP_AD21/TMD1_D2 J2AGP_AD22/TMD1_D3 J1AGP_AD23/TMD1_D4 H3AGP_AD24/TMD1_D7 F3AGP_AD25/TMD1_D6 G2AGP_AD26/TMD1_D9 F2AGP_AD27/TMD1_D8 F1
AGP_AD28/TMD1_D11 E2AGP_AD29/TMD1_D10 E1
AGP_AD30/TMDS_HPD D2AGP_AD31 D1
AGP2_SBSTB/AGP3_SBSTBF/NC/LVDS_BLON E5AGP2_SBSTB#/AGP3_SBSTBS/NC/ENA_BL E6
AGP2_ADSTB0/AGP3_ADSTBF0/TMD2_CLK# T3AGP2_ADSTB0#/AGP3_ADSTBS0/TMD2_CLK U2AGP2_ADSTB1/AGP3_ADSTBF1/TMD1_CLK# G3AGP2_ADSTB1#/AGP3_ADSTBS1/TMD1_CLK H2
AGP2_CBE#0/AGP3_CBE0/TMD2_D7 R3AGP2_CBE#1/AGP3_CBE1/TMD2_DE M1
AGP2_CBE#2/AGP3_CBE2 L3AGP2_CBE#3/AGP3_CBE3/TMD1_D5 H1
AGP2_DEVSEL#/AGP3_DEVSEL/GPIO9/I2C_DATA R5AGP2_FRAME#/AGP3_FRAME/TMDS_DVI_DATA P6
AGP2_IRDY#/AGP3_IRDY/GPIO8/I2C_CLK P5AGP2_TRDY#/AGP3_TRDY/TMDS_DVI_CLK R6
AGP2_WBF#/AGP3_WBF N5
AGP2_SBA0/AGP3_SBA#0/GPIO0/VDDC_CNTL0 C3AGP2_SBA1/AGP3_SBA#1/GPIO1/VDDC_CNTL1 C2
AGP2_SBA3/AGP3_SBA#3/GPIO3/LVDS_DIGON E4
AGP2_SBA5/AGP3_SBA#5/GPIO5/AGP_BUSY# F5AGP2_SBA6/AGP3_SBA#6/GPIO6/LVDS_SSOUT G6
AGP2_SBA7/AGP3_SBA#7/GPIO7/LVDS_SSIN G5
AGP_ST0 L6AGP_ST1 M6AGP_ST2 L5
AGP8X_DET#M5
AGP_VREF/TMDS_VREFJ6
AGP2_REQ#/AGP3_REQK6 AGP2_GNT#/AGP3_GNTK5
AGP2_SBA2/AGP3_SBA#2/GPIO2/LVDS_BLON# D4
AGP2_SBA4/AGP3_SBA#4/GPIO4/STP_AGP# F6
AGP2_STOP#/AGP3_STOP/GPIO10/DDC_DATA T6AGP_PAR T5
AGP2_RBF#/AGP3_RBF N6
AGP2_PIPE#/AGP3_DBI_HI C1AGP2_NC/AGP3_DBI_LO D3
AGP_COMPJ5
R995 NAPG@0_0402_5%1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RC300M_X2
RC300M_X1
CLK_AGP_66M
CLK_MEM_66M
CLK_AGP_66M
LVSSR
+1.8VS_LPVDD
+1.8VS_LVDDR
CRMA_R
COMPS_R
LUMA_R
HSYNC_R
GREEN_RRED_R
BLUE_R
VSYNC_R
NB_RSET
27M_TV 27M_TV_R
CLK_NB_BCLK#CLK_NB_BCLK
RC300M_X2
3VDDCCLDDCDATA_RDDCCLK_R
CRMA_R
3VDDCDA
DDCDATA_R
DDCCLK_R
CLK_MEM_66M
GREEN_RCRT_G
VSYNC_R
CRT_B BLUE_R
CRT_HSYNC
CRT_R
HSYNC_R
RED_R
CRT_VSYNC
LPVSS
RC300M_X1
TV_CRMALUMA_R TV_LUMA
TV_COMPSCOMPS_R
PLLVSS_18
PLLVDD_18
CPUCLK_STP#
CLK_AGP_66M<24>
TXACLK-_NB <25>
TXA0+_NB <25>
TXB0+_NB <25>
TXB2+_NB <25>TXBCLK-_NB <25>
TXB2-_NB <25>
TXA1-_NB <25>
TXBCLK+_NB <25>
TXA0-_NB <25>
TXB1+_NB <25>TXB1-_NB <25>
TXA2-_NB <25>
TXACLK+_NB <25>
TXA2+_NB <25>
CLK_NB_BCLK#<24>CLK_NB_BCLK<24>
3VDDCCL <17,25>
TV_LUMA <17,41,48>TV_COMPS <17,41,48>
TV_CRMA <17,41,48>
3VDDCDA <17,25>
CLK_MEM_66M<24>
CRT_HSYNC<17,25>CRT_VSYNC<17,25>
CRT_B<17,25>
CRT_R<17,25>CRT_G<17,25>
REFCLK1_NB<24>
TXB0-_NB <25>
TXA1+_NB <25>
PCI_RST# <26,30,31,34,35,36,43,46>
CPUCLK_STP# <5,26,56>
+1.8VS
+1.8VS
+3VS
+3VS
+1.8VS
+1.8VS
+1.8VS
+3VS
+2.5VS
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
ATI RC300M-VIDEO I/F
11 66, 07, 2003星期四 八月
Compal Electronics, Inc.
Note: PLACE CLOSE TO U27 (NB CHIP)
L Note: PLACE CLOSE TO U6 (VGA CHIP)
L
wait 1% new part
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
L Note: PLACE CLOSE TO U27 (NB CHIP)
R595 NAPG@0_0402_5%1 2
C600
10U_0805_16V4Z
1
2
R590 1K_0402_5%
R599 NAPG@0_0402_5%1 2
C601
@15P_0402_50V8J
L58
FBM-11-160808-121-T_06031 2
L63
KC FBM-L11-201209-221LMAT_08051 2
C594
0.1U_0402_10V6K
1
2
R587
68_0402_5%
12
R596 NAPG@0_0402_5%1 2
RP104
NAGP@0_4P2R_0402_5%
1423
L61KC FBM-L11-201209-221LMAT_0805
1 2
L59
KC FBM-L11-201209-221LMAT_0805
12
L62KC FBM-L11-201209-221LMAT_0805
1 2
C5870.1U_0402_10V6K
1
2
R592 NAGP@22_0402_5%
R597 NAPG@0_0402_5%1 2
C605
@18P_0402_50V8K
C588
0.1U_0402_10V6K
1
2
Y4@14.31818MHZ_20P_6X1430004201
12
R593
@1M_0402_1%
12
L60KC FBM-L11-201209-221LMAT_0805
1 2
R589 @0_0402_5%
C598
0.1U_0402_10V6K
1
2
R591
@10_0402_5%
12
C592
0.1U_0402_10V6K
1
2
G
D S
Q97@2N7002 1N_SOT23
2
1 3
L64
KC FBM-L11-201209-221LMAT_08051 2
PART 4 OF 6
CRT
CLK. GEN.
SVID
LVD
S
U27D
216RC300M_BGA_718
TXOUT_U0N D12TXOUT_U0P E12TXOUT_U1N F11TXOUT_U1P F12TXOUT_U2N D13TXOUT_U2P D14
TXCLK_UN E13TXCLK_UP F13
TXOUT_L0N E10TXOUT_L0P D10TXOUT_L1N B9TXOUT_L1P C9TXOUT_L2N D11TXOUT_L2P E11
TXCLK_LN B10TXCLK_LP C10
LVDDR_18 B12
LPVSS A11
LVDDR_18 C12
LPVDD_18 A12
LVSSR B11LVSSR C11
C_R E15
Y_G C15
COMP_B D15
DACSCL D6
DACSDA C6
CPUSTOP# D5
REDF14GREENF15BLUEE14DACHSYNCC8DACVSYNCD9
RSETC14
VDDR3H9
AVDDQA15
AVSSNB13
AVDD_25A14
AVDDDI_18B14
AVSSDIC13
AVSSQB15
PLLVDD_18H11
PLLVSSG11
VDDR3G9
XTALINA4XTALOUTB4
EXT_MEM_CLKA3
SYSCLK A8
SYSCLK# B8
AGPCLKINB3
HCLKIN#B5
ALINK_CLKD8
AGPCLKOUTB2
USBCLKD7REF27B7
SYS_FBCLKOUTB6
OSCC5
SYS_FBCLKOUT#A6
HCLKINA5
C596
10U_0805_16V4Z
1
2
R594 NAPG@0_0402_5%1 2
R584 715 _0402_1%1 2
R598 NAPG@0_0402_5%1 2
C590
0.1U_0402_10V6K
1
2
C591
10U_0805_16V4Z
1
2
C589
0.1U_0402_10V6K
1
2
C586
0.1U_0402_10V6K
1
2
C603
@15P_0402_50V8J
X2
NAGP@27MHZ_20P_6N
OUT 3
GND 2
VCC4
ST1
R588
@10_0402_5%
12
C602
NAGP@0.1U_0402_16V7K
1
2
C599
0.1U_0402_10V6K1
2
RP103
NAGP@0_4P2R_0402_5%
1 42 3
C593
0.1U_0402_10V6K
1
2
R585 0_0402_5%1 2
C604
@18P_0402_50V8K
C595
0.1U_0402_10V6K1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.5VS +2.5V
+VCC_CORE
+3VS
+3VS
+1.5VS
+1.8VS
+1.5VS
+1.8VS
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
ATI RC300M-POWER
12 66, 07, 2003星期四 八月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C583
0.1U_0402_10V6K
1
2
C582
0.1U_0402_10V6K
1
2
C579
10U_0805_10V4Z
1
2
C580
0.1U_0402_10V6K
1
2
C581
0.1U_0402_10V6K
1
2
R418M9-M10@0_0603_5%
1 2
PART 6 OF 6
GND
U27F
216RC300M_BGA_718
VSSA29VSSAB23VSSAB24VSSAB27VSSAB4VSSAB8VSSAC1VSSAC11VSSAC14VSSAC16VSSAC20VSSAC30VSSAD11VSSAD14VSSAD16VSSAD20VSSAD4VSSAE27VSSAF30VSSAF5VSSAG10VSSAG13VSSAG16VSSAG19VSSAG22VSSAG25VSSAG7VSSAH28VSSAH3VSSAJ1VSSAK13VSSAK2VSSAK22VSSAK29VSSAK4VSSAK7VSSB1VSSB16VSSB30VSSC19VSSC23VSSC27VSSC4VSSD21VSSD25VSSE3VSSE8VSSE9VSSF27VSSF4VSSF8VSSG14VSSG15VSSG18VSSG20VSSH14VSSH15VSSH18VSSH20VSSH27VSSH4VSSH8VSSJ7 VSS J8VSS K27VSS K4VSS L23VSS L24VSS L25VSS L7VSS L8VSS M15VSS M16VSS M27VSS M4VSS N15VSS N16VSS N23VSS N24VSS N8VSS P15VSS P16VSS P27VSS P4VSS R1VSS R12VSS R13VSS R14VSS R15VSS R16VSS R17VSS R18VSS R19
VSS R23VSS R7VSS R8VSS T12VSS T13VSS T14VSS T15VSS T16VSS T17VSS T18VSS T19VSS T27VSS T4VSS U15VSS U16VSS U7VSS U8VSS V15VSS V16VSS V27VSS V4VSS V7VSS V8VSS W15VSS W16VSS W27VSS Y1VSS Y23VSS Y24VSS Y30VSS Y4VSS Y7VSS Y8
R419 NAGP@0_0603_5%1 2
PART 5 OF 6
POW
ER
CO
RE
PW
R
AG
P P
WR
MEM
I/F
PWR
CPU
I/F
PWR
ALIN
K PW
R
U27E
216RC300M_BGA_718
VDD_COREF10VDD_COREF9VDD_COREG12VDD_COREH12VDD_COREH13VDD_COREM12VDD_COREM13VDD_COREM14VDD_COREM17VDD_COREM18VDD_COREM19VDD_COREN12VDD_COREN13VDD_COREN14VDD_COREN17VDD_COREN18VDD_COREN19VDD_COREP12VDD_COREP13VDD_COREP14VDD_COREP17VDD_COREP18VDD_COREP19VDD_COREU12VDD_COREU13VDD_COREU14VDD_COREU17VDD_COREU18VDD_COREU19VDD_COREV12VDD_COREV13VDD_COREV14VDD_COREV17VDD_COREV18VDD_COREV19VDD_COREW12VDD_COREW13VDD_COREW14VDD_COREW17VDD_COREW18VDD_COREW19
VDD_18 H22VDD_18 H10VDD_18 AC9VDD_18 AC22
VDDP_AGP/VDDP33 G8VDDP_AGP/VDDP33 F7VDDP_AGP/VDDP33 E7
VDDP_AGP T8VDDP_AGP R4VDDP_AGP P8VDDP_AGP P7VDDP_AGP P1VDDP_AGP N4VDDP_AGP M8VDDP_AGP M7VDDP_AGP L4VDDP_AGP K8VDDP_AGP J4VDDP_AGP H7VDDP_AGP H6VDDP_AGP H5VDDP_AGP G4VDDP_AGP A2
VDDR_MEM AA23VDDR_MEM AA27VDDR_MEM AB30VDDR_MEM AC10VDDR_MEM AC12VDDR_MEM AC13VDDR_MEM AC15VDDR_MEM AC17VDDR_MEM AC19VDDR_MEM AC21VDDR_MEM AC23VDDR_MEM AC24VDDR_MEM AC25VDDR_MEM AC27VDDR_MEM AD10VDDR_MEM AD12VDDR_MEM AD13VDDR_MEM AD15VDDR_MEM AD17VDDR_MEM AD19VDDR_MEM AD21VDDR_MEM AD23VDDR_MEM AD24VDDR_MEM AD25VDDR_MEM AD27VDDR_MEM AE10VDDR_MEM AE14VDDR_MEM AE15VDDR_MEM AE19VDDR_MEM AE20VDDR_MEM AE30VDDR_MEM AE9VDDR_MEM AF27VDDR_MEM AG11VDDR_MEM AG12
VDDL_ALINKW8 VDDL_ALINKAK3 VDDL_ALINKAD8 VDDL_ALINKAD7 VDDL_ALINKAD1 VDDL_ALINKAC8 VDDL_ALINKAC7 VDDL_ALINKAA8 VDDL_ALINKAA7 VDDL_ALINKAA1
VDDR2_CPUW30 VDDR2_CPUU24 VDDR2_CPUU23 VDDR2_CPUT24 VDDR2_CPUT23 VDDR2_CPUP24 VDDR2_CPUP23 VDDR2_CPUM23 VDDR2_CPUK24 VDDR2_CPUK23 VDDR2_CPUH24 VDDR2_CPUH21 VDDR2_CPUH19 VDDR2_CPUH17 VDDR2_CPUH16 VDDR2_CPUG24 VDDR2_CPUG23 VDDR2_CPUG21 VDDR2_CPUG17 VDDR2_CPUF17 VDDR2_CPUF16 VDDR2_CPUE17 VDDR2_CPUE16 VDDR2_CPUD17 VDDR2_CPUD16 VDDR2_CPUC16
VDDR_MEM AG17VDDR_MEM AG18VDDR_MEM AG23VDDR_MEM AG24VDDR_MEM AG26VDDR_MEM AG8VDDR_MEM AG9VDDR_MEM AJ30VDDR_MEM AK14VDDR_MEM AK23VDDR_MEM AK8VDDR_MEM V23VDDR_MEM W23VDDR_MEM W24VDDR_MEM W25VDDR_MEM Y25
VDDP_AGP U4VDDP_AGP U5VDDP_AGP U6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
A_AD[0..31]
A_CBE#[0..3]
A_AD22
A_AD24
A_AD30
A_AD17
A_AD18
A_PAR
A_AD31
A_CBE#0
A_CBE#3
A_AD26
A_AD28
A_AD21
A_AD29
A_AD20
A_AD27
A_AD25
A_AD23
A_AD[0..31]<10,26>
A_CBE#[0..3]<10,26>
A_PAR<10,26>
BSEL1 <5,24>
BSEL0 <5,24>
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
ATI RC300M-SYSTEM STRAP
13 66, 07, 2003星期四 八月
Compal Electronics, Inc.
0: IOQ=11: IOQ=12
DEFAULT:1
A_AD23 : CLOCK BYPASS DISABLE
A_AD24 : MOBILE CPU SELECT
A_CBE#3: NOT USED
0: DISABLE1: ENABLE
0: TEST MODE 1: NORMAL MODE
00: 100 MHZ01: 133 MHZ10: 200MHZ11:166 MHZ
A_AD28: SPREAD SPECTRUM ENABLE
0: DISABLE1: ENABLE
0: REDUCEDE SET
DEFAULT : 0
DEFAULT: 01
1: FULL SET
A_AD26 : ENABLE IOQ
DEFAULT: 1
A_AD29: STRAP CONFIGURATION
A_AD27: FrcShortReset#
A_AD[31..30] : FSB CLK SPEED
DEFAULT:0
DEFAULT: 1
0: TEST MODE1: NORMAL
DEFAULT: 10
A_AD22 : OSC PAD OUTPUT PCICLK
DEFAULT: 1
A_CBE#0 :NO USED
DEFAULT: 1
DEFAULT : 1
A_AD20 : INTERNAL CLK GEN ENABLE
0: DEBUG MODE1: NORMAL
0: BANIAS CPU1: OTHER CPU
00: 1.05V01: 1.35V11: 1.75V10: 1.45V
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
PAR: EXTENDED DEBUG MODE
0:PCICLK OUT 1: OSC CLK OUT
DEFAULT : 1
A_AD21 : AUTO_CAL ENABLE
DEFAULT : 10: DISABLE1: ENABLE
A_AD18 : ENABLE PHASE CALIBRATION
0: DISABLE 1:ENABLE
DEFAULT: 0
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
DEFAULT: 0
00: 1.05V01: 1.35V11: 1.75V10: 1.45V
AD25=1 DESTOP CPUAD25=0 MOBILE CPUAD17--DON'T CARE
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R431 4.7K_0402_5%
R428 4.7K_0402_5%
R422 4.7K_0402_5%
R429 @4.7K_0402_5%
R469 @4.7K_0402_5%
R438 10K_0402_5%1 2
R430 @10K_0402_5%1 2
R461 10K_0402_5%1 2
R425 4.7K_0402_5%
R443 10K_0402_5%1 2
R434 10K_0402_5%1 2
R427 10K_0402_5%1 2
R463 @4.7K_0402_5%
R435 @4.7K_0402_5%
R452 10K_0402_5%1 2
R448 10K_0402_5%1 2
D86RB751V_SOD323
2 1
R468 @4.7K_0402_5%
R423 4.7K_0402_5%
R454 @4.7K_0402_5%
D85RB751V_SOD323
2 1
R460 4.7K_0402_5%
R465 4.7K_0402_5%
R464 @4.7K_0402_5%
R466 @4.7K_0402_5%
R420 10K_0402_5%1 2
R444 @4.7K_0402_5%
R467 @4.7K_0402_5%
R421 @4.7K_0402_5%
R424 10K_0402_5%1 2
R440 @4.7K_0402_5%
R457 @4.7K_0402_5%
R462 @4.7K_0402_5%
R426 @4.7K_0402_5%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDRA_SDQS[0..7]
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_ADD[0..15]
DDRA_SDQ32
DDRA_SDQS3
DDRA_SDQ42
DDRA_SDQS4
DDRA_SDQS2
DDRA_SDQ19
DDRA_SDQ34
DDRA_SDQS5
DDRA_SDQ43
DDRA_WE#
DDRA_SDQ26
DDRA_SDQ16
DDRA_SDQ35
DDRA_SDQ41
DDRA_SDQ27
DDRA_SDQ18
DDRA_SDQ40
DDRA_SDQ25
DDRA_SDQ33
DDRA_SDQ24
DDRA_SDQ17
DDRA_SDQ44
DDRA_RAS#
DDRA_SDQ38
DDRA_CAS#
DDRA_SDQ39
DDRA_SDQ46
DDRA_SDM4
DDRA_SDQ36
DDRA_SDQ23
DDRA_SDM5
DDRA_SDQ37
DDRA_SDQ45
DDRA_SDQ47
DDRA_SDQ31
DDRA_SDM3
DDRA_SDQ20
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ21
DDRA_SDM2DDRA_SDQ22
DDRA_SDQ28
DDRA_VREF
DDRA_SDQ56DDRA_SDQ57
DDRA_SDQS7DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60DDRA_SDQ61
DDRA_SDM7DDRA_SDQ62
DDRA_SDQ63DDRA_SDQ48
DDRA_SDQ49DDRA_SDQS6
DDRA_SDQ50DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53DDRA_SDM6
DDRA_SDQ54DDRA_SDQ55
DDRA_SDQ6DDRA_SDQ7
DDRA_SDQ4
DDRA_SDM1
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDM0DDRA_SDQ5
DDRA_SDQ12
DDRA_SDQS0
DDRA_SDQ2
DDRA_SDQ1
DDRA_SDQ8
DDRA_SDQ3
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11DDRA_SDQ0
DDRA_SDQS1
DDRA_CKE_R1 DDRA_CKE_R0
DDRA_CS#0 DDRA_CS#1
DDRA_ADD5
DDRA_ADD12DDRA_ADD9
DDRA_ADD7
DDRA_ADD3DDRA_ADD1
DDRA_ADD10DDRA_ADD13
DDRA_ADD6DDRA_ADD4DDRA_ADD2DDRA_ADD0
DDRA_ADD14
DDRA_ADD11DDRA_ADD8
DDRA_ADD15
SMB_CK_DAT2<15,24,27>SMB_CK_CLK2<15,24,27>
DDRA_SDQ[0..63]<9,15,16>
DDRA_ADD[0..15]<9,15,16>
DDRA_SDM[0..7]<9,15,16>
DDRA_SDQS[0..7]<9,15,16>
DDRA_CKE_R1<9,16>
DDRA_CLK0<9>DDRA_CLK0#<9>
DDRA_WE#<9,15,16>
DDRA_CLK1# <9>DDRA_CLK1 <9>
DDRA_CAS# <9,15,16>DDRA_RAS# <9,15,16>
DDRA_CKE_R0 <9,16>
DDRA_CS#0<9,16> DDRA_CS#1 <9,16>
+2.5V+2.5V
+3VS
+2.5V
+2.5V
+2.5V+2.5V
Title
Size Document Number R ev
Date: Sheet o f
LA-1811 0.7
DDR-SODIMM SLOT1
14 66, 07星期四 八月 , 2003
Compal Electronics, Inc.
System Memory Decoupling caps
DDRA_VREF trace width of20mils and space 20mils(min)
DIMM0
Group 6 sweep Group 7Group 6 sweep Group 7
Group 0 sweep Group 1
Group 0 sweep Group 1
L
REVERSE
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C419
0.1U_0402_10V6K
1
2
C431
0.1U_0402_10V6K
1
2
C414
0.1U_0402_10V6K
1
2
C435
0.1U_0402_10V6K
1
2
C428
0.1U_0402_10V6K
1
2
C425
10U_0805_6.3V6M
1
2
C424
0.1U_0402_10V6K
1
2
C430
0.1U_0402_10V6K
1
2
C432
0.1U_0402_10V6K
1
2
C4110.1U_0402_10V6K
1
2R472
1K_0603_1%
12
C4120.1U_0402_10V6K
1
2
C416
0.1U_0402_10V6K
1
2
C433
0.1U_0402_10V6K
1
2
C436
0.1U_0402_10V6K
1
2
C422
0.1U_0402_10V6K
1
2
C426
0.1U_0402_10V6K
1
2
C434
0.1U_0402_10V6K
1
2
C438
10U_0805_6.3V6M
1
2
C417
0.1U_0402_10V6K
1
2
C437
0.1U_0402_10V6K
1
2
C429
0.1U_0402_10V6K
1
2
C415
0.1U_0402_10V6K
1
2
R473
1K_0603_1%
12
C418
0.1U_0402_10V6K
1
2
C427
0.1U_0402_10V6K
1
2
C413
0.1U_0402_10V6K
1
2
JP24
AMP_1565918-1
VREF1VSS3DQ05DQ17VDD9DQS011DQ213VSS15DQ317DQ819VDD21DQ923DQS125VSS27DQ1029DQ1131VDD33CK035CK0#37VSS39
DQ1641DQ1743VDD45DQS247DQ1849VSS51DQ1953DQ2455VDD57DQ2559DQS361VSS63DQ2665DQ2767VDD69CB071CB173VSS75DQS877CB279VDD81CB383DU85VSS87CK289CK2#91VDD93CKE195DU/A1397A1299A9101VSS103A7105A5107A3109A1111VDD113A10/AP115BA0117WE#119S0#121DU123VSS125DQ32127DQ33129VDD131DQS4133DQ34135VSS137DQ35139DQ40141VDD143
VREF 2VSS 4DQ4 6DQ5 8VDD 10DM0 12DQ6 14VSS 16DQ7 18
DQ12 20VDD 22
DQ13 24DM1 26VSS 28
DQ14 30DQ15 32VDD 34VDD 36VSS 38VSS 40
DQ20 42DQ21 44VDD 46DM2 48
DQ22 50VSS 52
DQ23 54DQ28 56VDD 58
DQ29 60DM3 62VSS 64
DQ30 66DQ31 68VDD 70CB4 72CB5 74VSS 76DM8 78CB6 80VDD 82CB7 84
DU/RESET# 86VSS 88VSS 90VDD 92VDD 94
CKE0 96DU/BA2 98
A11 100A8 102
VSS 104A6 106A4 108A2 110A0 112
VDD 114BA1 116
RAS# 118CAS# 120
S1# 122DU 124
VSS 126DQ36 128DQ37 130VDD 132DM4 134
DQ38 136VSS 138
DQ39 140DQ44 142VDD 144
DQ41145DQS5147VSS149DQ42151DQ43153VDD155VDD157VSS159VSS161DQ48163DQ49165VDD167DQS6169DQ50171VSS173DQ51175DQ56177VDD179DQ57181DQS7183VSS185DQ58187DQ59189VDD191SDA193SCL195VDD_SPD197VDD_ID199
DQ45 146DM5 148VSS 150
DQ46 152DQ47 154VDD 156
CK1# 158CK1 160VSS 162
DQ52 164DQ53 166VDD 168DM6 170
DQ54 172VSS 174
DQ55 176DQ60 178VDD 180
DQ61 182DM7 184VSS 186
DQ62 188DQ63 190VDD 192SA0 194SA1 196SA2 198DU 200
C421
0.1U_0402_10V6K
1
2
C420
0.1U_0402_10V6K
1
2
C423
0.1U_0402_10V6K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDRA_SDQS[0..7]
DDRA_SDM[0..7]
DDRA_ADD[0..15]
DDRA_SDQ[0..63]
DDRB_VREF
DDRA_SDQ30
DDRA_SDQ23
DDRA_SDQ32
DDRA_SDQ24
DDRA_SDQ43
DDRA_SDQ31
DDRA_SDQ29
DDRA_SDQ35
DDRA_SDQ42
DDRA_SDQ39
DDRA_SDQ28
DDRA_SDM2
DDRA_SDQS4
DDRA_SDQ47
DDRA_SDM5
DDRA_SDQS2
DDRA_SDM4
DDRA_SDQ21
DDRA_SDQ26
DDRA_SDQ19
DDRA_SDQ36
DDRA_SDQ20
DDRA_SDQ46
DDRA_SDQ33
DDRA_SDQ27
DDRA_SDQ44
DDRA_SDM3
DDRA_SDQ17
DDRA_SDQS5
DDRA_SDQ37
DDRA_SDQ41
DDRA_SDQ34
DDRA_SDQ16
DDRA_SDQ45
DDRA_SDQ38
DDRA_SDQ22
DDRA_SDQ40
DDRA_SDQS3DDRA_SDQ25
DDRA_SDQ18
DDRA_SDQS7
DDRA_SDQ50
DDRA_SDQ59
DDRA_SDQ51
DDRA_SDQS6
DDRA_SDQ48
DDRA_SDQ58
DDRA_SDQ57
DDRA_SDQ49
DDRA_SDQ56DDRA_SDQ61
DDRA_SDM6
DDRA_SDM7
DDRA_SDQ52
DDRA_SDQ62
DDRA_SDQ60
DDRA_SDQ63
DDRA_SDQ54
DDRA_SDQ53
DDRA_SDQ55
DDRA_SDQ8DDRA_SDQ9
DDRA_SDQS1DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12DDRA_SDQ13
DDRA_SDM1DDRA_SDQ14
DDRA_SDQ15DDRA_SDQ0
DDRA_SDQ1DDRA_SDQS0
DDRA_SDQ2DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5DDRA_SDM0
DDRA_SDQ6DDRA_SDQ7
DDRA_SWE#DDRA_SCS#2
DDRA_CKE2
DDRA_SCS#3
DDRA_SRAS#DDRA_SCAS#
DDRA_CKE3
DDRA_SMA13DDRA_SMA10
DDRA_SMA12
DDRA_SMA3
DDRA_SMA7
DDRA_SMA1
DDRA_SMA9
DDRA_SMA5
DDRA_SMA15
DDRA_SMA6
DDRA_SMA8
DDRA_SMA2DDRA_SMA0
DDRA_SMA11
DDRA_SMA4
DDRA_SMA14
DDRA_CKE3DDRA_CKE_R3
DDRA_WE# DDRA_SWE#
DDRA_CS#2 DDRA_SCS#2
DDRA_CKE2DDRA_CKE_R2
DDRA_RAS# DDRA_SRAS#
DDRA_CAS# DDRA_SCAS#
DDRA_CS#3 DDRA_SCS#3
DDRA_SMA9DDRA_SMA12
DDRA_ADD9DDRA_ADD12
DDRA_SMA7DDRA_SMA5
DDRA_ADD7DDRA_ADD5
DDRA_SMA3DDRA_SMA1
DDRA_ADD3DDRA_ADD1
DDRA_SMA10DDRA_SMA13
DDRA_ADD10DDRA_ADD13 DDRA_SMA14DDRA_ADD14
DDRA_ADD15DDRA_SMA15
DDRA_SMA11DDRA_SMA8
DDRA_SMA6DDRA_SMA4
DDRA_SMA2DDRA_SMA0
DDRA_ADD11DDRA_ADD8
DDRA_ADD6DDRA_ADD4
DDRA_ADD2DDRA_ADD0
DDRA_SDQ[0..63]<9,14,16>
DDRA_SDQS[0..7]<9,14,16>
DDRA_ADD[0..15]<9,14,16>
DDRA_SDM[0..7]<9,14,16>
SMB_CK_CLK2<14,24,27>SMB_CK_DAT2<14,24,27>
DDRA_CLK3<9>DDRA_CLK3#<9>
DDRA_CLK4# <9>DDRA_CLK4 <9>
DDRA_WE#<9,14,16>
DDRA_CS#2<9,16>
DDRA_CKE_R2<9,16>
DDRA_RAS#<9,14,16>
DDRA_CAS#<9,14,16>
DDRA_CS#3<9,16>
DDRA_CKE_R3<9,16>
+2.5V
+3VS
+2.5V
+2.5V
+2.5V
+2.5V+2.5V
+3VS
Title
Size Document Number R ev
Date: Sheet o f
LA-1811 0.7
DDR-SODIMM SLOT2
15 66, 07星期四 八月 , 2003
Compal Electronics, Inc.
System Memory Decoupling caps
DIMM1
Group 6 sweep Group 7
Group 0 sweep Group 1
Group 0 sweep Group 1
DDRB_VREF trace width of20mils and space20mils(min)
L
STANDARD
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R401 10_0402_5%12
R1122 10_0402_5%12
C406
0.1U_0402_10V6K
1
2
R471
1K_0603_1%
12
R390 10_0402_5%12
C408
0.1U_0402_10V6K
1
2
RP39
10_0404_4P2R_5%
1 42 3
JP23
AMP_1565917-1
VREF1VSS3DQ05DQ17VDD9DQS011DQ213VSS15DQ317DQ819VDD21DQ923DQS125VSS27DQ1029DQ1131VDD33CK035CK0#37VSS39
DQ1641DQ1743VDD45DQS247DQ1849VSS51DQ1953DQ2455VDD57DQ2559DQS361VSS63DQ2665DQ2767VDD69CB071CB173VSS75DQS877CB279VDD81CB383DU85VSS87CK289CK2#91VDD93CKE195DU/A1397A1299A9101VSS103A7105A5107A3109A1111VDD113A10/AP115BA0117WE#119S0#121DU123VSS125DQ32127DQ33129VDD131DQS4133DQ34135VSS137DQ35139DQ40141VDD143
VREF 2VSS 4DQ4 6DQ5 8VDD 10DM0 12DQ6 14VSS 16DQ7 18
DQ12 20VDD 22
DQ13 24DM1 26VSS 28
DQ14 30DQ15 32VDD 34VDD 36VSS 38VSS 40
DQ20 42DQ21 44VDD 46DM2 48
DQ22 50VSS 52
DQ23 54DQ28 56VDD 58
DQ29 60DM3 62VSS 64
DQ30 66DQ31 68VDD 70CB4 72CB5 74VSS 76DM8 78CB6 80VDD 82CB7 84
DU/RESET# 86VSS 88VSS 90VDD 92VDD 94
CKE0 96DU/BA2 98
A11 100A8 102
VSS 104A6 106A4 108A2 110A0 112
VDD 114BA1 116
RAS# 118CAS# 120
S1# 122DU 124
VSS 126DQ36 128DQ37 130VDD 132DM4 134
DQ38 136VSS 138
DQ39 140DQ44 142VDD 144
DQ41145DQS5147VSS149DQ42151DQ43153VDD155VDD157VSS159VSS161DQ48163DQ49165VDD167DQS6169DQ50171VSS173DQ51175DQ56177VDD179DQ57181DQS7183VSS185DQ58187DQ59189VDD191SDA193SCL195VDD_SPD197VDD_ID199
DQ45 146DM5 148VSS 150
DQ46 152DQ47 154VDD 156
CK1# 158CK1 160VSS 162
DQ52 164DQ53 166VDD 168DM6 170
DQ54 172VSS 174
DQ55 176DQ60 178VDD 180
DQ61 182DM7 184VSS 186
DQ62 188DQ63 190VDD 192SA0 194SA1 196SA2 198DU 200
R393 10_0402_5%12
C410
0.1U_0402_10V6K
1
2
C399
0.1U_0402_10V6K
1
2
C3920.1U_0402_10V6K
1
2
RP26
10_0404_4P2R_5%
1 42 3
C404
0.1U_0402_10V6K
1
2
C396
0.1U_0402_10V6K
1
2
C3930.1U_0402_10V6K
1
2
C401
10U_0805_6.3V6M
1
2
R392 10_0402_5%12
RP32
10_0404_4P2R_5%
1 42 3
C402
10U_0805_6.3V6M
1
2
R1121 10_0402_5%12
C403
0.1U_0402_10V6K
1
2
C407
0.1U_0402_10V6K
1
2
R396 10_0402_5%12
C394
22U_1206_10V4Z
1
2
RP38
10_0404_4P2R_5%
1 42 3
R470
1K_0603_1%
12
C409
0.1U_0402_10V6K
1
2
RP29
10_0404_4P2R_5%
1 42 3
R402 10_0402_5%12
C398
0.1U_0402_10V6K
1
2
RP42
10_0404_4P2R_5%
1 42 3
C397
0.1U_0402_10V6K
1
2
C405
0.1U_0402_10V6K
1
2
C400
0.1U_0402_10V6K
1
2
RP35
10_0404_4P2R_5%
1 42 3
C395
0.1U_0402_10V6K
1
2
R391 10_0402_5%12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDRA_SDM[0..7]
DDRA_SDQ[0..63]
DDRA_ADD[0..15]
DDRA_SDQS[0..7]
DDRA_SDQ8
DDRA_SDQ13
DDRA_SDQ21
DDRA_SDQ16
DDRA_SDQ24DDRA_SDQ28
DDRA_SDQ11DDRA_SDQ15
DDRA_SDQ14
DDRA_SDQS1
DDRA_SDQ19DDRA_SDQ23
DDRA_SDQ22
DDRA_SDQS2
DDRA_SDQ50
DDRA_SDQ54DDRA_SDQ55DDRA_SDQ51
DDRA_SDQ49
DDRA_SDQ53
DDRA_SDQS6
DDRA_SDM6
DDRA_SDQ59
DDRA_SDQ63DDRA_SDQ52
DDRA_SDQ48
DDRA_SDQ62
DDRA_SDQ58DDRA_SDQS7
DDRA_SDM7
DDRA_SDQ56
DDRA_SDQ60
DDRA_SDQ57
DDRA_SDQ61
DDRA_SDQS5
DDRA_SDM5DDRA_SDQ41
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ42DDRA_SDQ47
DDRA_SDQ43
DDRA_SDQ35DDRA_SDQ39
DDRA_SDQ40DDRA_SDQ44
DDRA_SDQ38
DDRA_SDQ34DDRA_SDQS4
DDRA_SDM4
DDRA_SDQ36
DDRA_SDQ32DDRA_SDQ33
DDRA_SDQ37
DDRA_SDQ25
DDRA_SDQ29
DDRA_SDQS3
DDRA_SDM3
DDRA_SDQ18DDRA_SDM2
DDRA_SDQ20DDRA_SDQ17
DDRA_SDQ6
DDRA_SDQ2DDRA_SDQ7
DDRA_SDQ3
DDRA_SDQ5
DDRA_SDQ1DDRA_SDQS0
DDRA_SDM0
DDRA_SDQ4DDRA_SDQ0
DDRA_SDQ10DDRA_SDM1
DDRA_SDQ12DDRA_SDQ9
DDRA_CS#0
DDRA_SDQ30
DDRA_SDQ26DDRA_SDQ31
DDRA_SDQ27
DDRA_CKE_R0DDRA_CKE_R1
DDRA_CS#3
DDRA_ADD9
DDRA_ADD8
DDRA_ADD2
DDRA_ADD10DDRA_ADD13DDRA_ADD15
DDRA_ADD1
DDRA_ADD0DDRA_ADD14DDRA_RAS#
DDRA_ADD12
DDRA_CS#1DDRA_CS#2
DDRA_WE#DDRA_ADD11
DDRA_ADD3DDRA_ADD7DDRA_ADD5
DDRA_CKE_R3DDRA_CKE_R2
DDRA_ADD4DDRA_ADD6
DDRA_CAS#
DDRA_SDQ[0..63]<9,14,15>
DDRA_SDQS[0..7]<9,14,15>
DDRA_ADD[0..15]<9,14,15>
DDRA_SDM[0..7]<9,14,15>
DDRA_CS#0 <9,14>
DDRA_CKE_R0 <9,14>DDRA_CKE_R1 <9,14>
DDRA_CS#3 <9,15>
DDRA_RAS# <9,14,15>
DDRA_CS#1 <9,14>DDRA_CS#2 <9,15>
DDRA_WE# <9,14,15>
DDRA_CKE_R3 <9,15>DDRA_CKE_R2 <9,15>
DDRA_CAS# <9,14,15>
+2.5V
+2.5V
+1.25VS +1.25VS
+2.5V
+1.25VS
+1.25VS
+1.25VS
+1.25VS
+1.25VS
+1.25VS
Title
Size Document Number R ev
Date: Sheet o f
LA-1811 0.7
DDR Termination Resistors
16 66, 07星期四 八月 , 2003
Compal Electronics, Inc.
DDR Termination resistors & Decoupling caps
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C466
0.1U_0402_10V6K
1
2
C486
0.1U_0402_10V6K
1
2
C470
0.1U_0402_10V6K
1
2
C469
0.1U_0402_10V6K
1
2
RP73
56 _0804_8P4R_5%
18273645
R474
33_0402_5%
12
C472
0.1U_0402_10V6K
1
2
C495
0.1U_0402_10V6K
1
2
C458
0.1U_0402_10V6K
1
2
RP91
56 _0804_8P4R_5%
18273645
RP89
33_0404_4P2R_5%
1423
RP70
56 _0804_8P4R_5%
18273645
C494
0.1U_0402_10V6K
1
2
RP82
56 _0804_8P4R_5%
18273645
RP68
56 _0804_8P4R_5%
1 82 73 64 5
RP65
56 _0804_8P4R_5%
1 82 73 64 5
C460
0.1U_0402_10V6K
1
2
C476
0.1U_0402_10V6K
1
2
C484
0.1U_0402_10V6K
1
2
C463
0.1U_0402_10V6K
1
2
RP78
33_0804_8P4R_5%
18273645
C490
4.7U_0805_16V6K
1
2
RP85
56 _0804_8P4R_5%
18273645
C473
0.1U_0402_10V6K
1
2
C474
0.1U_0402_10V6K
1
2
C496
0.1U_0402_10V6K
1
2
C471
0.1U_0402_10V6K
1
2
C465
0.1U_0402_10V6K
1
2
RP84
33_0804_8P4R_5%
18273645
C467
0.1U_0402_10V6K
1
2
C464
0.1U_0402_10V6K
1
2
RP88
56 _0804_8P4R_5%
18273645
RP79
56 _0804_8P4R_5%
18273645
RP92
33_0404_4P2R_5%
1423
C455
0.1U_0402_10V6K
1
2
C493
0.1U_0402_10V6K
1
2
C461
0.1U_0402_10V6K
1
2
C483
0.1U_0402_10V6K
1
2
RP81
33_0804_8P4R_5%
18273645
C452
0.1U_0402_10V6K
1
2
C462
0.1U_0402_10V6K
1
2
RP67
56 _0804_8P4R_5%
18273645
RP75
33_0804_8P4R_5%
18273645
+ C491
@100U_D2_10M_R45
1
2
C468
0.1U_0402_10V6K
1
2
C489
4.7U_0805_16V6K
1
2
RP72
33_0404_4P2R_5%
1423
+ C492
100U_D2_10M_R45
1
2
C457
0.1U_0402_10V6K
1
2
RP90
56 _0804_8P4R_5%
1 82 73 64 5
RP80
56 _0804_8P4R_5%
1 82 73 64 5
RP86
56 _0804_8P4R_5%
1 82 73 64 5
C478
0.1U_0402_10V6K
1
2
C459
0.1U_0402_10V6K
1
2
C497
4.7U_0805_16V6K
1
2
C479
0.1U_0402_10V6K
1
2
C475
0.1U_0402_10V6K
1
2
RP71
56 _0804_8P4R_5%
1 82 73 64 5
C482
0.1U_0402_10V6K
1
2
RP83
56 _0804_8P4R_5%
1 82 73 64 5
RP87
33_0404_4P2R_5%
1423
C481
0.1U_0402_10V6K
1
2
C456
0.1U_0402_10V6K
1
2
C451
0.1U_0402_10V6K
1
2
RP76
56 _0804_8P4R_5%
18273645
C480
0.1U_0402_10V6K
1
2
C453
0.1U_0402_10V6K
1
2
RP74
56 _0804_8P4R_5%
1 82 73 64 5
C488
0.1U_0402_10V6K
1
2
C485
0.1U_0402_10V6K
1
2
C454
0.1U_0402_10V6K
1
2
C487
0.1U_0402_10V6K
1
2
RP69
33_0404_4P2R_5%
1423
C477
0.1U_0402_10V6K
1
2
RP93
56 _0804_8P4R_5%
18273645
RP77
56 _0804_8P4R_5%
1 82 73 64 5
RP66
56 _0804_8P4R_5%
18273645
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
STRAP_S
STRAP_A
STRAP_L
STRAP_F
FREQOUT
STRAP_E
AGP_AD[0..31]
STRAP_M
STRAP_O
STRAP_N
STRAP_D
STRAP_B
AGP_ST[0..2]
AGP_SBA[0..7]
AGP_CBE#[0..3]
STRAP_R
STRAP_J
XTALIN_SSFREQOUT
STRAP_G
XTALIN
STRAP_T
XTALIN_SS
ENABLT#
CRT_R
TV_LUMA
AGP_REQ#
AGP_AD12
AGP_RSET
TXA0-
STRAP_E
AGP_SBA7
AGP_SBA2
NB_RST#
AGP_AD22
AGP_AD2
CRT_HSYNC
TXBCLK+
VREFG
STRAP_J
SSOUT
TV_CRMA
AGP_ADSTB0
AGP_AD27
AGP_AD16
DVOMODE
STRAP_M
AGP_SBSTB#
AGP_ST0
AGP_RBF#
AGP_DEVSEL#
AGP_AD23
AGP_AD17
AGP_AD8
TXB0+
AGP_AD5
TXA2+
TXA1+
STRAP_B
TV_COMPS
AGP_SBA4
AGP_BUSY#
AGP_AD10
TXBCLK-
AGP_SBA1
AGP_PAR
AGP_CBE#3
AGP_AD15
AGP_AD1
STRAP_K
CRT_G
STRAP_A
STRAP_K
AGP_ADSTB0#
AGP_IRDY#
AGP_AD20
AGP_AD11
STRAP_O
XTALIN
AGP_DBI_HI/PIPE#
AGP_ST2
AGP_SBA3
AGP_STP#
AGP_AD29
AGP_AD19
AGP_AD4
CRT_B
AGP_DBI_LO
AGP_ST1
AGP_AD14
3VDDCCL
TXB1-
MCLK_SPREAD
STRAP_F
AGP_CBE#1AGP_CBE#0
AGP_AD18
AGP_AD9
TXB2+TXB2-
TXA1-
STRAP_D
SUSSTAT#
AGP_AD26AGP_AD25
TXACLK-
STRAP_G
SSIN
AGP_SBA0
AGP_ADSTB1
CLK_AGP_EXT_66M
AGP_CBE#2
AGP_AD31
AGP_AD0
SUSSTAT#
TXA0+
STRAP_T
STRAP_N
AGP_SBA5
AGP_FRAME#
AGP_AD24
AGP_AD3
STRAP_H
3VDDCDA
TXB1+
TXACLK+
STRAP_L
AGP_ADSTB1#
AGP_GNT#
AGP_AD30
AGP_AD28
AGP_AD21
AGP_AD7
CRT_VSYNC
ENAVDD
TXB0-
STRAP_H
AGP_STOP#
TXA2-
AGP_SBSTB
AGP_SBA6
AGP_TRDY#
AGP_AD13
AGP_AD6
DRAM128M
DRAM128M
STRAP_SSTRAP_R
AGP_AD[0..31]<10>
AGP_SBA[0..7]<10>
AGP_CBE#[0..3]<10>
AGP_ST[0..2]<10>
CLK_AGP_EXT_66M<24>
AGP_BUSY#<10,27>AGP_STP#<10,27>
VREF_8X_IN<10>
AGP8X_DET#<10>
ENABLT# <10,25>
TV_LUMA<11,41,48>
AGP_RBF#<10>
PCI_PIRQA#<10,26,31,35,36>
AGP_WBF#<10>
CRT_B <11,25>CRT_HSYNC <11,25>
AGP_ADSTB0<10>
AGP_REQ#<10>
3VDDCCL <11,25>
AGP_TRDY#<10>
AGP_STOP#<10>
AGP_IRDY#<10>
AGP_ADSTB1<10>
3VDDCDA <11,25>
AGP_SBSTB#<10>
TV_COMPS<11,41,48>
AGP_ADSTB1#<10>AGP_ADSTB0#<10>
CRT_R <11,25>
CRT_VSYNC <11,25>
AGP_DBI_HI/PIPE#<10>
AGP_PAR<10>
AGP_SBSTB<10>
AGP_DBI_LO<10>
AGP_GNT#<10>
NB_RST#<8,26,39>
CRT_G <11,25>
TV_CRMA<11,41,48>
AGP_DEVSEL#<10>
AGP_FRAME#<10>
SSOUT<10>
SSIN<10>
M10_BKOFF# <25>
TXACLK- <25>
TXB0+ <25>
TXBCLK- <25>
TXA0- <25>TXA0+ <25>
TXB1- <25>
TXA2- <25>
TXB1+ <25>
TXA1- <25>
TXA2+ <25>
TXB2+ <25>TXB2- <25>
TXBCLK+ <25>
TXB0- <25>
TXA1+ <25>
TXACLK+ <25>
ENAVDD <10,25,46>
DDC_DAT <10,25>DDC_CLK <10,25>
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+1.5VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
ATI M10-P & M9+X (AGP BUS)
17 66, 02, 2003星期二 九月
Compal Electronics, Inc.
GPIO0
GPIO6
GPIO5
GPIO4
VGA_Disable
3.3V OSC out for W180
GPIO7
1.5V OSC out for M9+X1.2V OSC out for M10-P
ID_Disable
Rb
Divider Circuit for 1.2V/(1.5)dc XTALIN from 3.3Vdc OSC out
GPIO8
Ra
Leave These Pin No Connecting, WhenUsing M10-P Internal Spread Spectrum
GPIO3
GPIO13
GPIO2
GPIO12
GPIO11
GPIO9
GPIO1
AGP, DAC & LVDS INTERFACE
AGP8X_DET#Low:AGP3.0
(15mil)
(25mil)
(15mil)
(15mil)
(25 mil)
SS%
(Closed to M26)
If M10+P POP 47_0603_1%If M9+P POP 137_0603_1%
Note: PLACE CLOSE TO U6 (VGA M9+X/M10-P)L
Ra 261_0603_1%
150_0402_5%150_0402_5%
180_0603_5%
M10-PM9+X
Rb
Fin>Fout>Fin-3.75%
Spread % Setting for Freq. RangeFin>Fout>Fin-1.25%0
1
Selection Table For W180
SS%
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
For VGA DDR spread sprum
CLK
DATA
For 8Mx32 VGA DRAM only
R235 @1K_0402_5%1 2
R267 100K_0402_5%
R247 @10K_0402_5%12C184 @10P_0402_50V8K
1 2
R270 10K_0402_5%12
R268 22_0402_5%1 2
R238 @10K_0402_5%12
R234
M10@1K_0603_1%
12
U7
W180-01GT_SO8
X1/CLK1
X2 2FS17
FS28
VDD
6
CLKOUT 5
SS% 4
GN
D3
C189
0.1U_0402_10V6K1
2
R257 @10K_0402_5%12
R250 @10K_0402_5%12
R258 0_0402_5%1 2
R272 499_0402_1%1 2
R233 @10K_0402_5%12
R236 @10K_0402_5%12
R242 @10K_0402_5%12
R244 @10K_0402_5%12
R232 @10K_0402_5%12
R239
M10@1K_0603_1%
12
R243 M10@10K_0402_5%12
R274 10K_0402_5%1 2
R271 @10K_0402_5%12
L13
FCM2012C-800_0805
1 2
R264 137_0603_1%1 2
R829M9@0_0402_5%
R830 M10@0_0402_5%
R936@4.7K_0402_5%
R246 @10K_0402_5%12
C1912.2U_0603_6.3V4Z1
2R266 715_0603_1%
C1860.1U_0402_10V6K
1
2
R248 @10K_0402_5%12
R276 1K_0603_5%1 2
C188
0.1U_0402_10V6K
1
2
R269 10K_0402_5%12
R265M9-M10@1K_5%1 2
R249 @10_0402_5%1 2
C185
0.1U_0402_10V6K
1
2
R259 @10K_0402_5%12
R1149@10K_0402_5%
12
R245 @10K_0402_5%12
R254 @10K_0402_5%12
R241 M10@10K_0402_5%12
R26110K_0402_5%
12
R252 @10K_0402_5%12
R260 @10K_0402_5%12
C187
@15P_0402_50V8J
X1
27MHZ_15P
OUT 3
GND 2
VDD4
OE1
R275 1K_0603_5%1 2
R262 180_0603_5%1 2
PCI/A
GP
AG
P8X
CLK
ZV P
OR
T / E
XT T
MD
S / G
PIO
/ R
OM
LVD
STM
DS
DA
C1SS
CD
AC
2
M10-P/(M9+X) (1/6)
THRM
U6A
SA002160E00(0301021300)
AD0H29AD1H28AD2J29AD3J28AD4K29AD5K28AD6L29AD7L28AD8N28AD9P29AD10P28AD11R29AD12R28AD13T29AD14T28AD15U29AD16N25AD17R26AD18P25AD19R27AD20R25AD21T25AD22T26AD23U25AD24V27AD25W26AD26W25AD27Y26AD28Y25AD29AA26AD30AA25AD31AA27
C/BE#0N29C/BE#1U28C/BE#2P26C/BE#3U26
PCICLKAG30RST#AG28REQ#AF28GNT#AD26PARM25STOP#N26DEVSEL#V29TRDY#V28IRDY#W29FRAME#W28INTA#AE26
WBF#AC26
STP_AGP#AH30AGP_BUSY#AH29RBF#AE29AD_STBF_0M28AD_STBF_1V25AD_STBS_0M29AD_STBS_1V26
SBA0AD28SBA1AD29SBA2AC28SBA3AC29SBA4AA28SBA5AA29SBA6Y28SBA7Y29
ST0AF29ST1AD27ST2AE28
SB_STBFAB29SB_STBSAB28
AGPREFM26AGPTESTM27
DBI_HIAB25DBI_LOAB26
AGP8X_DET#AC25
DMINUSAE11DPLUSAF11
R2SETAK21
C_RAJ23Y_GAJ22COMP_BAK22H2SYNCAJ24V2SYNCAK24
DDC3CLKAG23DDC3DATAAG24
SSINAK25
SSOUTAJ25
XTALINAH28
XTALOUTAJ29
TESTENAH27
SUS_STAT#AG26
GPIO0 AJ5GPIO1 AH5GPIO2 AJ4GPIO3 AK4GPIO4 AH4GPIO5 AF4GPIO6 AJ3GPIO7 AK3GPIO8 AH3GPIO9 AJ2
GPIO10 AH2GPIO11 AH1GPIO12 AG3GPIO13 AG1GPIO14 AG2GPIO15 AF3GPIO16 AF2
VREFG/(NC) AG4
ROMCS# AF5
ZV_LCDDATA0 AH6ZV_LCDDATA1 AJ6ZV_LCDDATA2 AK6ZV_LCDDATA3 AH7ZV_LCDDATA4 AK7ZV_LCDDATA5 AJ7ZV_LCDDATA6 AH8ZV_LCDDATA7 AJ8ZV_LCDDATA8 AH9ZV_LCDDATA9 AJ9
ZV_LCDDATA10 AK9ZV_LCDDATA11 AH10ZV_LCDDATA12 AE6ZV_LCDDATA13 AG6ZV_LCDDATA14 AF6ZV_LCDDATA15 AE7ZV_LCDDATA16 AF7ZV_LCDDATA17 AE8ZV_LCDDATA18 AG8ZV_LCDDATA19 AF8ZV_LCDDATA20 AE9ZV_LCDDATA21 AF9ZV_LCDDATA22 AG10ZV_LCDDATA23 AF10
ZV_LCDCNTL0 AJ10ZV_LCDCNTL1 AK10ZV_LCDCNTL2 AJ11ZV_LCDCNTL3 AH11
DVOMODE AE10
TXOUT_L0N AK16TXOUT_L0P AH16TXOUT_L1N AH17TXOUT_L1P AJ16TXOUT_L2N AH18TXOUT_L2P AJ17TXOUT_L3N AK19TXOUT_L3P AH19
TXCLK_LN AK18TXCLK_LP AJ18
TXOUT_U0N AG16TXOUT_U0P AF16TXOUT_U1N AG17TXOUT_U1P AF17TXOUT_U2N AF18TXOUT_U2P AE18TXOUT_U3N AH20TXOUT_U3P AG20
TXCLK_UN AF19TXCLK_UP AG19
DIGON AE12BLON/(BLON#) AG12
TX0M AJ13TX0P AH14TX1M AJ14TX1P AH15TX2M AJ15TX2P AK15
TXCM AH13TXCP AK13
DDC2CLK AE13DDC2DATA AE14
HPD1 AF12
R AK27G AJ27B AJ26
HSYNC AG25VSYNC AH25
RSET AH26
DDC1DATA AF25DDC1CLK AF24
AUXWIN AF26
TEST_MCLK/(NC) B6
TEST_YCLK/(NC) E8
PLLTEST/(NC) AE25
RSTB_MSK/(NC) AG29
R2370_0402_5%1 2
R263150_0402_5%
12
R955@10K_0402_5%
12
R240 @10K_0402_5%12
R253
10K_0402_5%
12
R256 @10K_0402_5%12
R273
10K_0402_5%
12
C190
0.1U_0402_10V6K
1
2
R255 @10K_0402_5%12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NDQSA3
NMDA13
NMDA26
NMDA32
NMDA7
NDQSA0
NMAA6
NMDA12
NDQMA1
NMDA59
NMDA16
NMDA43
MVREFS
NMDA30
NMDA27
NDQMA4
NMDA3
NMDA1
NMAA11
NMDA25
NMAA12
NDQSA7
NMDA11
NMDA46
NMDA50
NMDA2
NDQMA0
NMAA4
NMDA52
NMDA55
NDQSA5
NDQMA3
NMDA24
NMAA0
NMDA45
NMDA48
NDQSA2
NMDA49
NDQMA7
NMDA33
NMDA19
NMCASA#
NMDA18
NMDA28
NMDA38
NMAA2
NMDA41
NMDA47
NMDA35
NMAA10
NMCLKA0#
NMDA14
NMDA31
NMDA15
NMDA20
NMDA56
NDQSA4
NMAA[0..13]
NMDA54
MVREFD
NMDA58
NMDA51
NMDA37
NMDA42
NMDA6
NMDA34
NMAA9NMDA10
NMDA60
NMDA62
NDQMA6
NMCKEA
NMDA4
NMWEA#
NMDA36
NMDA61
NDQMA[0..7]
NMDA44NMCSA0#
NDQMA5
NMDA39
NMDA63
NMDA0
NMDA17
NDQSA6
MVREFD
NMAA8
NMDA29
NDQMA2
NMAA7
NMDA[0..63]
NMAA3
NDQSA1
NMCLKA1
NMAA1
NMAA13
NMDA57
NMDA21
NMDA5
NMDA9
MVREFS
NMAA5
NMDA23NMDA22
NMDA53
NMDA40
NMDA8
NDQSA[0..7]
NMCLKA1#
NMRASA#
NMCLKA0
NMCSA1#
NMCLKA0# <22>
NMCASA# <22>
NMDA[0..63]<22>
NMCSA0# <22>
NDQMA[0..7]<22>
NMCLKA1 <22>
NMAA[0..13]<22>
NMWEA# <22>
NDQSA[0..7]<22>
NMCLKA1# <22>
NMCKEA <22>
NMRASA# <22>
NMCLKA0 <22>
NMCSA1# <22>
+2.5VS
+2.5VS
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
ATI M10-P/M9+X DDR-A
18 66, 07, 2003星期四 八月
Compal Electronics, Inc.
Poped for M10-PDepoped forM9+X
MEMORYINTERFACE A
(25 mil)
(25 mil)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R475
1K_0402_1%
12
R486
M10@1K_0402_1%
12
R478
1K_0402_1%
12
R487
M10@1K_0402_1%
12
C498
0.1U_0402_10V6K
1
2
MEM
OR
Y IN
TER
FAC
EA
M10-P/(M9+X) (2/6)
U6B
SA002160E00(0301021300)
DQA0L25DQA1L26DQA2K25DQA3K26DQA4J26DQA5H25DQA6H26DQA7G26DQA8G30DQA9D29DQA10D28DQA11E28DQA12E29DQA13G29DQA14G28DQA15F28DQA16G25DQA17F26DQA18E26DQA19F25DQA20E24DQA21F23DQA22E23DQA23D22DQA24B29DQA25C29DQA26C25DQA27C27DQA28B28DQA29B25DQA30C26DQA31B26DQA32F17DQA33E17DQA34D16DQA35F16DQA36E15DQA37F14DQA38E14DQA39F13DQA40C17DQA41B18DQA42B17DQA43B15DQA44C13DQA45B14DQA46C14DQA47C16DQA48A13DQA49A12DQA50C12DQA51B12DQA52C10DQA53C9DQA54B9DQA55B10DQA56E13DQA57E12DQA58E10DQA59F12DQA60F11DQA61E9DQA62F9DQA63F8
AA0 E22AA1 B22AA2 B23AA3 B24AA4 C23AA5 C22AA6 F22AA7 F21AA8 C21AA9 A24
AA10 C24AA11 A25
AA12/(AA13) E21AA13/(AA12) B20
AA14/(NC) C19
DQMA#0 J25DQMA#1 F29DQMA#2 E25DQMA#3 A27DQMA#4 F15DQMA#5 C15DQMA#6 C11DQMA#7 E11
QSA0 J27QSA1 F30QSA2 F24QSA3 B27QSA4 E16QSA5 B16QSA6 B11QSA7 F10
RASA# A19
CASA# E18
WEA# E19
CSA0# E20
CSA1# F20
CKEA B19
CLKA0 B21CLKA0# C20
CLKA1 C18CLKA1# A18
DIMA0 D30DIMA1 B13
MVREFD B7
MVREFS/(NC) B8C503
M10@0.1U_0402_16V4Z
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NMDB26
NMDB40
NMAB5
NMDB62
NMDB[0..63]
NMDB44
NMDB48
NMDB18
NMDB54
NDQSB3
NMDB49
NMDB63
NMAB0
NMAB11
NDQSB4
NDQSB7
NMDB39
NMDB22
NMDB36
NMAB7
NMDB12
NMDB21
NMDB31
NMCLKB0#
NMDB42
NMAB2
NMAB4
NMDB34
NMDB43
NMCLKB0
NMDB19
NDQMB6
NMDB20
NMDB11
NMDB29
NDQMB1
NMCASB#
NDQMB4
NMDB53NMDB52
NMDB14
NMAB12
NDQMB0
NMAB[0..13]
NMDB10
NMDB38
NMDB46
NMDB35
NMDB45
NMDB51NMCLKB1#
NMDB61
NMDB13
NMAB1
NMDB50
NDQMB[0..7]
NMDB60
NMDB25
NMDB2
NMDB4
NMWEB#
NMDB16
NMDB23
NMDB7
NMAB3
NMAB10
NMDB59
NMDB41
NMDB24
NMDB3
NMDB58
NDQMB7
NMDB30
NMDB57
NMAB6
NMDB8
NDQSB1
NDQSB6
NDQMB5
NMAB13
NMDB28NMDB27
NMAB9
NDQSB[0..7]
NMAB8
NMCSB0#
NMDB47
NDQMB2
NMDB6
NMDB55
NMDB9
NMDB33
NMDB56
NMDB15
NDQSB0
NMDB5
NMDB17
NMDB32
NMDB37
NMRASB#
NDQMB3
NMDB1NMDB0
NDQSB5
NDQSB2
NMCKEB
NMCLKB1
NMCSB1#
NMCASB# <23>
NMWEB# <23>
NMCLKB0 <23>
NMDB[0..63]<23>
NMCKEB <23>
NDQMB[0..7]<23>
NMCSB0# <23>
NMAB[0..13]<23>
NMCLKB0# <23>
NDQSB[0..7]<23>
NMRASB# <23>
NMCLKB1# <23>NMCLKB1 <23>
NMCSB1# <23>
+1.8VS
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
ATI M10-P/M9+X DDR-B
19 66, 07, 2003星期四 八月
Compal Electronics, Inc.
(15mil)
MEMORYINTERFACE B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
MEM
OR
Y IN
TER
FAC
E B
M10-P/(M9+X) (3/6)
U6C
SA002160E00(0301021300)
DQB0D7DQB1F7DQB2E7DQB3G6DQB4G5DQB5F5DQB6E5DQB7C4DQB8B5DQB9C5DQB10A4DQB11B4DQB12C2DQB13D3DQB14D1DQB15D2DQB16G4DQB17H6DQB18H5DQB19J6DQB20K5DQB21K4DQB22L6DQB23L5DQB24G2DQB25F3DQB26H2DQB27E2DQB28F2DQB29J3DQB30F1DQB31H3DQB32U6DQB33U5DQB34U3DQB35V6DQB36W5DQB37W4DQB38Y6DQB39Y5DQB40U2DQB41V2DQB42V1DQB43V3DQB44W3DQB45Y2DQB46Y3DQB47AA2DQB48AA6DQB49AA5DQB50AB6DQB51AB5DQB52AD6DQB53AD5DQB54AE5DQB55AE4DQB56AB2DQB57AB3DQB58AC2DQB59AC3DQB60AD3DQB61AE1DQB62AE2DQB63AE3
AB0 N5AB1 M1AB2 M3AB3 L3AB4 L2AB5 M2AB6 M5AB7 P6AB8 N3AB9 K2
AB10 K3AB11 J2
AB12/(AB13) P5AB13/(AB12) P3
AB14/(NC) P2
DQMB#0 E6DQMB#1 B2DQMB#2 J5DQMB#3 G3DQMB#4 W6DQMB#5 W2DQMB#6 AC6DQMB#7 AD2
QSB0 F6QSB1 B3QSB2 K6QSB3 G1QSB4 V5QSB5 W1QSB6 AC5QSB7 AD1
RASB# R2
CASB# T5
WEB# T6
CSB0# R5
CSB1# R6
CKEB R3
CLKB0 N1CLKB0# N2
CLKB1 T2CLKB1# T3
MEMVMODE0 C6MEMVMODE1 C7
DIMB0 E3DIMB1 AA3
MEMTEST C8
R509 4.7K_0402_5%1 2R510 4.7K_0402_5%1 2
R511 47_0603_1%1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+LVDDR+VDDC1.5
+1.8VS
+VDD_DAC1.8
+VDD_DAC2.5
+VDD_PNLIO1.8
+VDD_PNLIO1.8
+VDD_PNLIO2.5
+3VS
+2.5VDDRH
+VDD_PLL1.8
+VDD_PNLIO2.5
+2.5VS
+VDD_PNLPLL1.8
+VDD_DAC1.8
+3VS
+2.5VS
+VDD_MEMPLL1.8
+1.8VS
+VDD_PNLIO1.8
+2.5VS
+1.8VS
+1.8VS
+2.5VS
+2.5VS
+VDD_MEMPLL1.8
+VDD_DAC1.8
+VDD_PNLPLL1.8
+VDD_PNLPLL1.8
+2.5VDDRH
+VDD_PNLIO1.8
+1.8VS
+VDD_DAC1.8+VDD_DAC2.5
+VDD_PLL1.8
+1.8VS
+1.5VS
+1.5VS
+1.5VS
+VDDC1.5 +LVDDR
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
ATI M10-P/M9+X POWER-A
20 66, 07, 2003星期四 八月
Compal Electronics, Inc.
(20 mil)
As close as possible to related pin
Poped for M9+X
(20 mil)Poped for M10-P
Poped for M10-P
(20 mil)
POWERINTERFACE
(20 mil)
(20 mil)
Poped for M9+X
(20 mil)
(20 mil)
(20 mil)
Poped forM10-P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Note: PLACE CLOSE TO U6 (VGA ATI M10P/M9+X)L
C215
0.1U_0402_10V6K
1
2
C869
0.1U_0402_10V6K
1
2
C199
0.1U_0402_10V6K
1
2
C194
0.1U_0402_10V6K
1
2
C203
0.1U_0402_10V6K
1
2
C209
10U_0805_6.3V6M
1
2
C220
0.1U_0402_10V6K
1
2
R280 M10@0_0603_5%1 2
C2022.2U_0603_6.3V4Z
1
2
C863
0.1U_0402_10V6K
1
2
C192
22U_1206_10V4Z
1
2
C868
0.1U_0402_10V6K
1
2
C208
0.1U_0402_10V6K
1
2
C201
0.01U_0402_16V7K
1
2
L17
CHB1608U301_06031 2
C217
0.1U_0402_10V6K
1
2
C213
0.1U_0402_10V6K
1
2
L20
CHB1608U3011 2
R281 M9@0_0603_5%1 2
C862
0.1U_0402_10V6K
1
2
C870
0.1U_0402_10V6K
1
2
C216
0.1U_0402_10V6K
1
2
C200
0.01U_0402_16V7K
1
2
L21
CHB1608U3011 2
C193
0.1U_0402_10V6K
1
2
C865
0.1U_0402_10V6K
1
2
C212
0.1U_0402_10V6K
1
2
C205
0.1U_0402_10V6K
1
2
C207
0.1U_0402_10V6K
1
2
C196
0.01U_0402_16V7K
1
2
C871
0.1U_0402_10V6K
1
2
C968
0.1U_0402_10V6K
1
2
C214
10U_0805_6.3V6M
1
2
C866
0.1U_0402_10V6K
1
2
C195
0.01U_0402_16V7K
1
2
R278 M10@0_0402_5%1 2
L15
CHB1608U301_06031 2
C967
0.1U_0402_10V6K
1
2
L14
CHB1608U301_06031 2
C210
0.1U_0402_10V6K
1
2
C92
0.1U_0402_10V6K
1
2
C197
22U_1206_10V4Z
1
2
I/O P
OW
ER
M10-P/(M9+X) (4/6)
U6D
SA002160E00(0301021300)
VDDR1B1VDDR1B30VDDR1A15VDDR1A21VDDR1A28VDDR1A3VDDR1A9VDDR1AA1VDDR1AA4VDDR1AA7VDDR1AA8VDDR1AD4VDDR1D5VDDR1D8VDDR1D11VDDR1D13VDDR1D14VDDR1D17VDDR1D20VDDR1D23VDDR1D26VDDR1E27VDDR1F4VDDR1G7VDDR1G10VDDR1G13VDDR1G15VDDR1G19VDDR1G22VDDR1G27VDDR1H10VDDR1H13VDDR1H15VDDR1H17VDDR1H19VDDR1H22VDDR1J1VDDR1J23VDDR1J24VDDR1J4VDDR1J7VDDR1J8VDDR1L27VDDR1L8VDDR1M4VDDR1N4VDDR1N7VDDR1N8VDDR1R1VDDR1T4VDDR1T7VDDR1T8VDDR1V4VDDR1V7VDDR1V8VDDR1/(CLKAFB)D19VDDR1/(CLKBFB)R4
VDDC15/(VDDC18)AC11VDDC15/(VDDC18)AC20VDDC15/(VDDC18)H11VDDC15/(VDDC18)H20VDDC15/(VDDC18)L23VDDC15/(VDDC18)P8VDDC15/(VDDC18)Y23VDDC15/(VDDC18)Y8
TPVDDAK12TPVSSAJ12
AVSSNAH23AVSSQAD24
VDDRH0 F18VDDRH1 N6
VSSRH0 F19VSSRH1 M6
VDDR4 AC10VDDR4 AC9VDDR4 AD10VDDR4 AD9VDDR4 AG7
VDDP AA23VDDP AA24VDDP AB30VDDP AC23VDDP AC27VDDP AE30VDDP AF27VDDP J30VDDP M23VDDP M24VDDP N30VDDP P23VDDP P27VDDP T23VDDP T24VDDP T30VDDP U27VDDP V23VDDP V24VDDP W30VDDP Y27
LVSSR AF20LVSSR AF15LVSSR AE19LVSSR AE16LPVSS AJ19
VSS1DI AE23VSS2DI AE21
VDD1DI AE24VDD2DI AE22
TXVDDR AF13TXVDDR AF14
TXVSSR AG13TXVSSR AG14TXVSSR AH12
AVDDAH24A2VDDAG21A2VDDAH21A2VDDQAF22
A2VSSNAH22A2VSSNAJ21A2VSSQAF23
MPVDD A7MPVSS A6
PVSS AJ28PVDD AK28
VDDR3 AC19VDDR3 AC21VDDR3 AC22VDDR3 AC8VDDR3 AD19VDDR3 AD21VDDR3 AD22VDDR3 AD7
LVDDR_25/(LVDDR_18_25) AE20LVDDR_25/(LVDDR_18_25) AE17
LVDDR_18 AF21LVDDR_18 AE15
LPVDD AJ20
C9312.2U_0603_6.3V4Z1
2
C219
0.1U_0402_10V6K
1
2
C204
1U_0603_10V6K
1
2
R282 M9@0_0805_5%1 2
L16
CHB1608U301_06031 2
C970
0.1U_0402_10V6K
1
2
R279 M10@0_0805_5%1 2
C211
10U_0805_6.3V6M
1
2
C198
0.1U_0402_10V6K
1
2
L19
CHB1608U301_06031 2
C867
0.01U_0402_16V7K
1
2
C969
0.1U_0402_10V6K
1
2
C218
10U_0805_6.3V6M
1
2
C206
10U_0805_6.3V6M
1
2
L18
CHB1608U301_06031 2
R277 M10@0_0402_5%1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+2.5VS
+VGA_CORE
+VGA_CORE
+VGA_CORE
+VGA_CORE_CI
+VGA_CORE_CI
+2.5VS
+VGA_CORE
+1.2VS_VGA
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
ATI M10-P/M9+X POWER-B
21 66, 07, 2003星期四 八月
Compal Electronics, Inc.
As close as ppossible to related pin
(20 mil)
POWERINTERFACE
As close as ppossible to related pin
480MIL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
(12A,480mils ,Via NO.=24)
+ C221
@47U_D2_6.3VM
1
2
C2390.01U_0402_16V7K
1
2
C2300.01U_0402_16V7K
1
2
C2380.01U_0402_16V7K
1
2
C2360.1U_0402_10V6K
1
2
CO
RE
POW
ER
M10-P/(M9+X) (5/6)
U6E
SA002160E00(0301021300)
VSSA10VSSA16VSSA2VSSA22VSSA29VSSAA30VSSAB1VSSAB23VSSAB24VSSAB27VSSAB4VSSAB7VSSAB8VSSAC12VSSAC14VSSAC16VSSAC18VSSAC4VSSAD12VSSAD16VSSAD18VSSAD25VSSAD30VSSAE27VSSAG11VSSAG15VSSAG18VSSAG22VSSAG27VSSAG5VSSAG9VSSAJ1VSSAJ30VSSAK2VSSAK29VSSC1VSSC28VSSC3VSSC30VSSD10VSSD12VSSD15VSSD18VSSD21VSSD24VSSD25VSSD27VSSD4VSSD6VSSD9VSSE4VSSF27
VSS G12VSS G16
VSS H4VSS H8VSS H9VSS H12VSS H14VSS H18VSS H21VSS H23VSS H27VSS K1VSS K23VSS K24VSS K27VSS K30VSS K7VSS K8VSS L4VSS M30VSS M7VSS M8VSS N23VSS N24VSS N27VSS P4VSS R23VSS R24VSS R30VSS R7VSS R8VSS T1VSS T27VSS U23VSS U4VSS U8VSS V30VSS W23VSS W24VSS W27VSS W7VSS W8VSS Y4VSS G9
VSS G24VSS G21VSS G18
C2480.1U_0402_10V6K
1
2
C2450.1U_0402_10V6K
1
2
C2270.1U_0402_10V6K
1
2
L22
CHB1608U3011 2
JOPEN5PAD-OPEN 4x4m1 2
C2370.1U_0402_10V6K
1
2
C2290.01U_0402_16V7K
1
2
C2500.01U_0402_16V7K
1
2
CO
RE
POW
ER
M10-P/(M9+X) (6/6)
M10-P&M9+XCOMMON
M10-PONLY
M9+XONLY
U6F
SA002160E00(0301021300)
VDDC AD15VDDC AD13VDDC AC17VDDC AC15VDDC AC13
VDDCM12VDDCM13VDDCM14VDDCM17VDDCM18VDDCM19VDDCN12VDDCN13VDDCN14VDDCN17VDDCN18VDDCN19VDDCP12VDDCP13VDDCP14VDDCP17VDDCP18VDDCP19VDDCU12VDDCU13VDDCU14VDDCU17VDDCU18VDDCU19VDDCV12VDDCV13VDDCV14VDDCV17VDDCV18VDDCV19VDDCW12VDDCW13VDDCW14VDDCW17VDDCW18VDDCW19
VDDCI T12VDDCI M15VDDCI W16VDDCI R19
VSS R12VSS R13VSS T13VSS R14VSS T14VSS N15VSS P15VSS R15VSS T15VSS U15VSS V15VSS W15VSS H16VSS M16VSS N16VSS P16VSS R16VSS T16VSS U16VSS V16VSS R17VSS T17VSS R18VSS T18VSS T19
VDDCAB22VDDCAB9VDDCJ10VDDCJ12VDDCJ14VDDCJ15VDDCJ16VDDCJ17VDDCJ19VDDCJ21VDDCK22VDDCK9VDDCM22VDDCM9VDDCP22VDDCP9VDDCR22VDDCR9VDDCT22VDDCT9VDDCU22VDDCU9VDDCV22VDDCV9VDDCY22VDDCY9
VSS AA22VSS AA9VSS J11VSS J13VSS J18VSS J20VSS J22VSS J9VSS L22VSS L9VSS N22VSS N9VSS W22VSS W9
C2440.1U_0402_10V6K
1
2
C2350.1U_0402_10V6K
1
2
C2340.1U_0402_10V6K
1
2
C2280.1U_0402_10V6K
1
2
C2460.1U_0402_10V6K
1
2
C2470.1U_0402_10V6K
1
2
C2420.1U_0402_10V6K
1
2
C2310.01U_0402_16V7K
1
2
C22322U_1206_10V4Z
1
2
C23222U_1206_10V4Z
1
2
C24322U_1206_10V4Z
1
2
C22422U_1206_10V4Z
1
2
C2250.1U_0402_10V6K
1
2
C240
10U_0805_6.3V6M
1
2
+C222
100U_D2_10M_R45
1
2
C2410.1U_0402_10V6K
1
2
C2330.1U_0402_10V6K
1
2
C2490.01U_0402_16V7K
1
2
C2260.1U_0402_10V6K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NMDA30
NMDA7
NDQSA3
NDQMA3
NMAA2NMDA52
NMDA17
NMCLKA1#
NDQMA7
NMRASA#
NMDA43
NMAA5NMDA49
NDQSA4
NMDA56
VREF_2
NDQMA5
NMDA21
NMDA61
NMDA41NMDA10
NMAA5
NMDA34
NMAA12
NMAA10
NMWEA#
NMDA[0..63]
NMDA38
NMCSA0#
NMAA8
NMAA6
NMAA1
NMDA19
NMDA22
NMAA9
NMAA7
NMDA1
NMDA44
NMCLKA1
NMDA57
NMDA4
NMDA50
NDQMA1
NMAA13
NMDA13
NMAA13
NMAA7
NMDA42
NMDA2
NMAA4
NMDA29
NDQSA1
NMDA14
NMAA12
NMDA53NMAA3
NMDA62
NMDA28
NMAA1NMAA2
NMDA35
NMCKEA
NMDA3
NDQMA2
NMDA54
NMRASA#
NMDA51
NDQSA[0..7]
NMAA8
NMDA45
NMDA47
NMDA39
NMAA4
NMDA24
NMDA15
NMCSA0#
NMDA25
NMAA11
NMDA36
NMDA6
NMDA9
NDQSA5
NDQSA7
NMDA31
NMDA27
NMDA16
NMCASA#
NMAA0
NMDA26
NDQSA0
NMCKEA
NMCASA#
NMAA0
NMDA18
NMDA55
NMDA37
NMDA46
NMDA32
NDQMA0
NMCLKA0
NMDA11
NMDA59
NMDA23
NMDA0
VREF_1
NMAA[0..13]
NMAA11
NDQSA6
NMAA9
NMDA40
NMDA20 NMAA3
NMDA8NMWEA#
NMAA6
NMDA33
NDQMA[0..7]
NDQSA2
NMDA58
NMDA5
NMDA48NMDA63
NDQMA4
NMDA12
NMAA10
NDQMA6
NMDA60
NMCLKA0#
NMCSA1#
NMCSA1#
NMCLKA1#<18>
NMCLKA1<18>
NDQSA[0..7]<18>
NMCSA0#<18>NMWEA#<18>
NMCLKA0<18>
NDQMA[0..7]<18>
NMAA[0..13]<18>
NMCKEA<18>
NMDA[0..63]<18>
NMRASA#<18>
NMCLKA0#<18>
NMCASA#<18>
NMCSA1#<18>
+2.5VS+2.5VS
+2.5VS+2.5VS
+2.5VS +2.5VS
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
VGA DDR FOR CHANNEL A
22 66, 07, 2003星期四 八月
Compal Electronics, Inc.
(25mil)
VGA DDR FOR CHANNELA
As close as ppossible to related pin
(25mil)
As close as ppossible to related pin
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C5060.1U_0402_10V6K
1
2
C504
10U_0805_10V3M
1
2
C5120.1U_0402_10V6K
1
2
U28
K4D263238A-GC
DQ0 B7DQ1 C6DQ2 B6DQ3 B5DQ4 C2DQ5 D3DQ6 D2DQ7 E2DQ8 K13DQ9 K12
DQ10 J13DQ11 J12DQ12 G13DQ13 G12DQ14 F13DQ15 F12DQ16 F3DQ17 F2DQ18 G3DQ19 G2DQ20 J3DQ21 J2DQ22 K2DQ23 K3DQ24 E13DQ25 D13DQ26 D12DQ27 C13DQ28 B10DQ29 B9DQ30 C9DQ31 B8
A0N5A1N6A2M6A3N7A4N8A5M9A6N9A7N10A8/APN11A9M8A10L6A11M7BA0N4BA1M5
DM0B3DM1H12DM2H3DM3B12
DQS0B2DQS1H13DQS2H2DQS3B13
VREFN13MCLM13RFU1L9RFU2M10
RAS#M2CAS#L2WE#L3CS#N2
CKEN12
CKM11CK#M12
VDD D7VDD D8VDD E4VDD E11VDD L4VDD L7VDD L8VDD L11
VDDQ C3VDDQ C5VDDQ C7VDDQ C8VDDQ C10VDDQ C12VDDQ E3VDDQ E12VDDQ F4VDDQ F11VDDQ G4VDDQ G11VDDQ J4VDDQ J11VDDQ K4VDDQ K11
VSSQ
B4VS
SQB1
1VS
SQD
4VS
SQD
5VS
SQD
6VS
SQD
9VS
SQD
10VS
SQD
11VS
SQE6
VSSQ
E9VS
SQF5
VSSQ
F10
VSSQ
G5
VSSQ
G10
VSSQ
H5
VSSQ
H10
VSSQ
J5VS
SQJ1
0VS
SQK5
VSSQ
K10
VSS
THF6
VSS
THF7
VSS
THF8
VSS
THF9
VSS
THG
6VS
S TH
G7
VSS
THG
8VS
S TH
G9
VSS
THH
6VS
S TH
H7
VSS
THH
8VS
S TH
H9
VSS
THJ6
VSS
THJ7
VSS
THJ8
VSS
THJ9
VSSE7VSSE8VSSE10VSSK6VSSK7VSSK8VSSK9VSSL5VSSL10VSSE5
NCC4NCC11NCH4NCH11NCL12NCL13NCM3NCM4NCN3
C507
10U_0805_10V3M
1
2
R62656.2_0402_1%
C5150.1U_0402_10V6K
1
2
R489
1K_0402_1%
12
R488
1K_0402_1%
12
C5160.1U_0402_10V6K
1
2
R62756.2_0402_1%
R491
1K_0402_1%
12
C62910P_0402_50V8K
1
2
U29
K4D263238A-GC
DQ0 B7DQ1 C6DQ2 B6DQ3 B5DQ4 C2DQ5 D3DQ6 D2DQ7 E2DQ8 K13DQ9 K12
DQ10 J13DQ11 J12DQ12 G13DQ13 G12DQ14 F13DQ15 F12DQ16 F3DQ17 F2DQ18 G3DQ19 G2DQ20 J3DQ21 J2DQ22 K2DQ23 K3DQ24 E13DQ25 D13DQ26 D12DQ27 C13DQ28 B10DQ29 B9DQ30 C9DQ31 B8
A0N5A1N6A2M6A3N7A4N8A5M9A6N9A7N10A8/APN11A9M8A10L6A11M7BA0N4BA1M5
DM0B3DM1H12DM2H3DM3B12
DQS0B2DQS1H13DQS2H2DQS3B13
VREFN13MCLM13RFU1L9RFU2M10
RAS#M2CAS#L2WE#L3CS#N2
CKEN12
CKM11CK#M12
VDD D7VDD D8VDD E4VDD E11VDD L4VDD L7VDD L8VDD L11
VDDQ C3VDDQ C5VDDQ C7VDDQ C8VDDQ C10VDDQ C12VDDQ E3VDDQ E12VDDQ F4VDDQ F11VDDQ G4VDDQ G11VDDQ J4VDDQ J11VDDQ K4VDDQ K11
VSSQ
B4VS
SQB1
1VS
SQD
4VS
SQD
5VS
SQD
6VS
SQD
9VS
SQD
10VS
SQD
11VS
SQE6
VSSQ
E9VS
SQF5
VSSQ
F10
VSSQ
G5
VSSQ
G10
VSSQ
H5
VSSQ
H10
VSSQ
J5VS
SQJ1
0VS
SQK5
VSSQ
K10
VSS
THF6
VSS
THF7
VSS
THF8
VSS
THF9
VSS
THG
6VS
S TH
G7
VSS
THG
8VS
S TH
G9
VSS
THH
6VS
S TH
H7
VSS
THH
8VS
S TH
H9
VSS
THJ6
VSS
THJ7
VSS
THJ8
VSS
THJ9
VSSE7VSSE8VSSE10VSSK6VSSK7VSSK8VSSK9VSSL5VSSL10VSSE5
NCC4NCC11NCH4NCH11NCL12NCL13NCM3NCM4NCN3
R490
1K_0402_1%
12
C628
10P_0402_50V8K
1
2
C510
10U_0805_10V3M
1
2
C5080.1U_0402_10V6K
1
2
C5050.1U_0402_10V6K
1
2
C5090.1U_0402_10V6K
1
2
C513
10U_0805_10V3M
1
2
C5110.1U_0402_10V6K
1
2
C5170.1U_0402_10V6K
1
2
R62556.2_0402_1%
C5140.1U_0402_10V6K
1
2
R62856.2_0402_1%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NMDB5
NMDB49
NDQSB3
NMAB4
NMDB8NMDB33
VREF_4NMDB53
NMAB8
NMAB6
NMDB25
NMAB10NMAB11
NMDB12
NDQMB4
NMDB57
NMDB43NMAB4
NMDB40
NDQMB7
NMAB2
NMDB28
NMDB1
NMAB10
NMDB6
NMDB22NMAB9
NMDB9
NMAB6
NMAB13
NMDB34
NDQMB2
NMDB54
NMDB41
NMDB50NMDB26
NMDB13
NMDB44
NMAB12
NMDB56
NDQMB1
NDQMB5
NMDB32
NDQMB[0..7]
NMAB0
NMDB29VREF_3
NMDB2
NDQSB1
NMDB37
NMDB7
NMCKEB
NMAB5
NMDB62NMDB23
NMDB10NDQSB0
NMDB55
NMAB3
NDQSB2NMDB35
NMDB19
NMDB45
NMDB63NMAB7
NDQMB3
NMDB30
NMAB1
NMCLKB1NMCLKB0
NMAB11
NMDB16
NMAB5NMDB3
NMDB51
NMAB1
NMAB[0..13]
NMCASB#
NMDB59
NDQMB0
NMAB9
NMDB38
NMDB36
NMDB14
NDQSB[0..7]
NMDB31
NDQSB4
NMDB20
NMAB0NMDB46
NMDB17
NMRASB#
NMDB39
NMAB12
NMCASB#NMWEB#
NMDB42
NDQSB6
NMDB60
NDQSB7
NMAB2NMDB4
NMDB48NMRASB#
NMAB8
NMCKEB
NMDB15
NMDB21
NMDB52
NMAB7
NMDB58
NMDB24
NMAB13
NMDB61
NMDB11
NMAB3
NMDB47
NDQMB6
NMDB18
NMDB27
NMCSB0#
NMDB0
NDQSB5
NMDB[0..63]
NMCLKB0# NMCLKB1#
NMCSB1# NMCSB1#
NMWEB#NMCSB0#
NMRASB#<19>
NMCLKB1#<19>
NMCKEB<19>
NMCSB0#<19>
NMCASB#<19>
NDQMB[0..7]<19>
NMCLKB0<19> NMCLKB1<19>
NDQSB[0..7]<19>
NMCLKB0#<19>
NMAB[0..13]<19>
NMWEB#<19>
NMDB[0..63]<19>
NMCSB1#<19>
+2.5VS
+2.5VS
+2.5VS
+2.5VS
+2.5VS
+2.5VS
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
VGA DDR FOR CHANNEL B
23 66, 07, 2003星期四 八月
Compal Electronics, Inc.
(25mil)
As close as ppossible to related pinAs close as ppossible to related pin
VGA DDR FOR CHANNELB
(25mil)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C5390.1U_0402_10V6K
1
2
C63110P_0402_50V8K
1
2
C5370.01U_0402_16V7K
1
2
U30
K4D263238A-GC
DQ0 B7DQ1 C6DQ2 B6DQ3 B5DQ4 C2DQ5 D3DQ6 D2DQ7 E2DQ8 K13DQ9 K12
DQ10 J13DQ11 J12DQ12 G13DQ13 G12DQ14 F13DQ15 F12DQ16 F3DQ17 F2DQ18 G3DQ19 G2DQ20 J3DQ21 J2DQ22 K2DQ23 K3DQ24 E13DQ25 D13DQ26 D12DQ27 C13DQ28 B10DQ29 B9DQ30 C9DQ31 B8
A0N5A1N6A2M6A3N7A4N8A5M9A6N9A7N10A8/APN11A9M8A10L6A11M7BA0N4BA1M5
DM0B3DM1H12DM2H3DM3B12
DQS0B2DQS1H13DQS2H2DQS3B13
VREFN13MCLM13RFU1L9RFU2M10
RAS#M2CAS#L2WE#L3CS#N2
CKEN12
CKM11CK#M12
VDD D7VDD D8VDD E4VDD E11VDD L4VDD L7VDD L8VDD L11
VDDQ C3VDDQ C5VDDQ C7VDDQ C8VDDQ C10VDDQ C12VDDQ E3VDDQ E12VDDQ F4VDDQ F11VDDQ G4VDDQ G11VDDQ J4VDDQ J11VDDQ K4VDDQ K11
VSSQ
B4VS
SQB1
1VS
SQD
4VS
SQD
5VS
SQD
6VS
SQD
9VS
SQD
10VS
SQD
11VS
SQE6
VSSQ
E9VS
SQF5
VSSQ
F10
VSSQ
G5
VSSQ
G10
VSSQ
H5
VSSQ
H10
VSSQ
J5VS
SQJ1
0VS
SQK5
VSSQ
K10
VSS
THF6
VSS
THF7
VSS
THF8
VSS
THF9
VSS
THG
6VS
S TH
G7
VSS
THG
8VS
S TH
G9
VSS
THH
6VS
S TH
H7
VSS
THH
8VS
S TH
H9
VSS
THJ6
VSS
THJ7
VSS
THJ8
VSS
THJ9
VSSE7VSSE8VSSE10VSSK6VSSK7VSSK8VSSK9VSSL5VSSL10VSSE5
NCC4NCC11NCH4NCH11NCL12NCL13NCM3NCM4NCN3
C5290.1U_0402_10V6K
1
2
C5350.1U_0402_10V6K
1
2
R632
56.2_0402_1%
C53322U_1206_10V4Z
1
2
R494
1K_0603_1%
12
C5320.01U_0402_16V7K
1
2
C5380.1U_0402_10V6K
1
2
R62956.2_0402_1%
C63010P_0402_50V8K
1
2
U31
K4D263238A-GC
DQ0 B7DQ1 C6DQ2 B6DQ3 B5DQ4 C2DQ5 D3DQ6 D2DQ7 E2DQ8 K13DQ9 K12
DQ10 J13DQ11 J12DQ12 G13DQ13 G12DQ14 F13DQ15 F12DQ16 F3DQ17 F2DQ18 G3DQ19 G2DQ20 J3DQ21 J2DQ22 K2DQ23 K3DQ24 E13DQ25 D13DQ26 D12DQ27 C13DQ28 B10DQ29 B9DQ30 C9DQ31 B8
A0N5A1N6A2M6A3N7A4N8A5M9A6N9A7N10A8/APN11A9M8A10L6A11M7BA0N4BA1M5
DM0B3DM1H12DM2H3DM3B12
DQS0B2DQS1H13DQS2H2DQS3B13
VREFN13MCLM13RFU1L9RFU2M10
RAS#M2CAS#L2WE#L3CS#N2
CKEN12
CKM11CK#M12
VDD D7VDD D8VDD E4VDD E11VDD L4VDD L7VDD L8VDD L11
VDDQ C3VDDQ C5VDDQ C7VDDQ C8VDDQ C10VDDQ C12VDDQ E3VDDQ E12VDDQ F4VDDQ F11VDDQ G4VDDQ G11VDDQ J4VDDQ J11VDDQ K4VDDQ K11
VSSQ
B4VS
SQB1
1VS
SQD
4VS
SQD
5VS
SQD
6VS
SQD
9VS
SQD
10VS
SQD
11VS
SQE6
VSSQ
E9VS
SQF5
VSSQ
F10
VSSQ
G5
VSSQ
G10
VSSQ
H5
VSSQ
H10
VSSQ
J5VS
SQJ1
0VS
SQK5
VSSQ
K10
VSS
THF6
VSS
THF7
VSS
THF8
VSS
THF9
VSS
THG
6VS
S TH
G7
VSS
THG
8VS
S TH
G9
VSS
THH
6VS
S TH
H7
VSS
THH
8VS
S TH
H9
VSS
THJ6
VSS
THJ7
VSS
THJ8
VSS
THJ9
VSSE7VSSE8VSSE10VSSK6VSSK7VSSK8VSSK9VSSL5VSSL10VSSE5
NCC4NCC11NCH4NCH11NCL12NCL13NCM3NCM4NCN3
C5190.1U_0402_10V6K
1
2
C5200.1U_0402_10V6K
1
2
C52822U_1206_10V4Z
1
2
C5250.1U_0402_10V6K
1
2
R63056.2_0402_1%
C5340.1U_0402_10V6K
1
2
C5240.1U_0402_10V6K
1
2
C5220.01U_0402_16V7K
1
2
R497
1K_0603_1%
12
C5270.01U_0402_16V7K
1
2
R495
1K_0603_1%
12
C5300.1U_0402_10V6K
1
2
R631
56.2_0402_1%
R496
1K_0603_1%
12
C5310.01U_0402_16V7K
1
2
C52322U_1206_10V4Z
1
2
C5210.01U_0402_16V7K
1
2
C5260.01U_0402_16V7K
1
2
C5360.01U_0402_16V7K
1
2
C51822U_1206_10V4Z
1
2
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
CLK_BCLK#
MEM_66MCLK_48M
AGP_66M
FS3
+3V_VDD
CLK_BCLK
CLK_NB#
CLK_NB
VSSA
SMB_CK_DAT2SMB_CK_CLK2
CLK_IREF
PCI33/66#
FS1
FS2FS3
PCI33/66#
CLK_BCLK
CLK_BCLK#
AGP_EXT_66M
FS4
FS0
FS4
XTALIN_CLK
XTALOUT_CLK
24/48#
CLK_SD
FS2
CK_BCLK
CK_BCLK#
FS1FS0
CLK_NB_BCLK <11>
CLK_NB_BCLK# <11>
CK_BCLK <4>
CK_BCLK# <4>
CLK_SB_48M<27>CLK_MEM_66M <11>
CLK_ALINK_SB <26>
CK_ITP <5>
CK_ITP# <5>
CLK_SD_48M<31>
SMB_CK_DAT2<14,15,27>SMB_CK_CLK2<14,15,27>
CLK_AGP_66M <11>CLK_AGP_EXT_66M <17>
VTT_PWRGD<27,46,48>
CLK_14M_CODEC<37>CLK_SB_14M<27>
REFCLK1_NB<11>
CLK_LPC_48M<39>
BSEL0<5,13>
BSEL1<5,13>
CLK_14M_APIC<26>
+3VS
+3VS
+3V_CLK
+3V_CLK
+3VS
+3V_CLK
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
Clock Generator
24 66, 07, 2003星期四 八月
Compal Electronics, Inc.
Width=40 mils
1330 0 0 1 0
PCI33/66# = HIGH
FS2 MEMFS1
200
FS3
200
A-LINK FREQ
Note: 0 = PULL LOW1 = PULL HIGH
66MHZ
PCI33/66# = LOW 33MHZ
CLOCK FREQUENCY SELECT TABLE
FS0
133
CPUFS4 With Spread Enabled…
0 0 0 0 1 *
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0 0 0 0 0 100 100Spreaf OFF OR Center spread +/-0.3%
L12
CHB2012U121_08051 2
R224
4.7K_0402_5%
12
R196 49.9_0402_1%1 2
R228
@10K_0402_5%
12
R202 49.9_0402_1%1 2
R201 33_0402_1%1 2
C127 10P_0402_50V8K1 2
R213 33_0402_1%1 2
C120
0.1U_0402_10V6K
1
2
R219
10K_0402_5%
12
R996 68_0402_5%1 2
C124
0.1U_0402_10V6K
1
2
R1068 @33_0402_1%1 2
R210 M9_M10@33_0402_1%1 2
R215 33_0402_1%1 2
R1056 10K_0402_5%1 2
C130 10P_0402_50V8K1 2
R197 49.9_0402_1%1 2
C125
0.1U_0402_10V6K
1
2
R221
@10K_0402_5%
12
R998
10K_0402_5%
12
C123
0.1U_0402_10V6K
1
2
R962 10K_0402_5%1 2
C122
0.1U_0402_10V6K
1
2
U5
ICS951402AGT_TSSOP48
XIN6
XOUT7
VDD
REF
1
FS0/REF02 FS1/REF13 FS2/REF24
GN
DR
EF5
GN
DXT
AL8
VDD
XTAL
9
PCI33/66#SEL11
PCI_STOP#12
VDD
PCI
13
FS3/PCICLK_F0 14FS4/PCICLK_F1 15
GN
DPC
I18
VDD
PCI
19G
ND
PCI
24
VDD
SD48
SDRAMOUT 47
GN
DSD
46
CPU_STP#45
CPUT1 44
CPUC1 43
VDD
CPU
42
GN
DC
PU41
CPUC0 39
CPUT0 40
IREF38
VSSA 37
VDDA 36
SCLK35SDATA34
VTTPWRGD/PD#10
AGPCLK0 32
VDD
AGP
30
AGPCLK1 31
VDD
48M
29
48MHz_028
24/48#SEL26
GN
D48
M25
48MHz_127
GN
DA
GP
33
PCICLK0 16PCICLK1 17PCICLK2 20PCICLK3 21PCICLK4 22PCICLK5 23
R226
10K_0402_5%
12
R963
@1M_0402_5%
12
R209 33_0402_1%1 2
R997 33_0402_1%1 2
R193 @0_0402_5%
C118
10U_0805_6.3V6M
1
2
R227
10K_0402_5%
12
R204 33_0402_1%1 2
R223
10K_0402_5%
12
R195 33_0402_1%1 2
D83 RB751V_SOD32321
R203 49.9_0402_1%1 2
C126
0.1U_0402_10V6K
1
2
Y2
14.318MHZ
12
R999
4.7K_0402_5%
12
C119
0.1U_0402_10V6K
1
2
R225
10K_0402_5%
12
R194 @0_0402_5%
D84 RB751V_SOD32321
R206 33_0402_1%1 2
R1111 10K_0402_5%1 2
R220
@10K_0402_5%
12
R218
475_0402_1%
12
R200 33_0402_1%1 2
L11
HB-1M2012-121JT03_0805
1 2
R205 33_0402_1%1 2
C128
0.1U_0402_10V6K
1
2
C121
0.1U_0402_10V6K
1
2
R208 33_0402_1%1 2
R222
@10K_0402_5%
12
C129
10U_0805_6.3V6M
1
2
R207 33_0402_1%1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CRT_G
3VDDCCL
CRT_R
CRT_B
3VDDCDA
3VDDCCL
3VDDCDA
ENABLT#
DISPOFF#
CRTL_G
CRTL_B
CRTL_RM_SEN#
CRT_VCC
TXB1-
TXA1-TXB0+
TXACLK+
TXB2-
TXACLK-
TXB0-
LCDVDD_A
TXA2-
TXBCLK+
TXB1+
TXA0+
TXB2+TXBCLK-
TXA1+
TXA2+
TXA0-
TXB2+_NB
TXB0+_NB
TXBCLK+_NBTXBCLK-_NB
TXB1-_NB
TXB0-_NB
TXA2+_NB
TXB2-_NB
TXA0-_NB
TXB1+_NB
TXACLK-_NB
TXA2-_NB
TXA1+_NBTXA1-_NB
TXA0+_NB
TXACLK+_NB
DISPOFF#
DAC_BRIGINVT_PWMDISPOFF#
DDC_CLKDDC_DAT
DDC_CLKDDC_DAT
ENAVDD
LCDVDD_A
CRT_HSYNCRFL
CRT_VSYNCRFL
CRT_HSYNC
CRT_VSYNC
CRT_R<11,17>
CRT_G<11,17>
CRT_B<11,17>
3VDDCDA<11,17>
3VDDCCL<11,17>
ENABLT#<10,17>
BKOFF#<46>
ENAVDD<10,17,46>
M_SEN#<46>
M10_BKOFF#<17>
TXA1-<17>TXA1+<17>
TXA0-<17>
TXB0+ <17>
TXBCLK- <17>
TXA2+<17>
TXB1+<17>TXB1-<17>
TXBCLK+ <17>
TXA2-<17>
TXB2+<17>TXB2-<17>
TXA0+<17>
TXB0- <17>
TXACLK-<17>TXACLK+<17>
TXA0+_NB<11>
TXA2-_NB<11>
TXB1-_NB<11>
TXA1-_NB<11>
TXB1+_NB<11>
TXACLK-_NB<11>
TXB0-_NB <11>
TXBCLK-_NB <11>
TXA2+_NB<11>
TXB2-_NB<11>TXBCLK+_NB <11>
TXB0+_NB <11>
TXB2+_NB<11>
TXACLK+_NB<11>
TXA0-_NB<11>
TXA1+_NB<11>
INVT_PWM <46>DAC_BRIG <46>
DDC_DAT <10,17>DDC_CLK <10,17>
CRT_HSYNC<11,17>
CRT_VSYNC<11,17>
+3VS
+3VS
R_CRT_VCC+5VS CRT_VCC
INVPWR_B+
+12VALW+5VS
+3VS
LCDVDD
+12VALW
LCDVDD
+3VS+12VALW
B+
+5VS
LCDVDD
INVPWR_B+
INVPWR_B+
+3VS
+3VS
+3VS
+3VS
CRT_VCC
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
LCD,CRT,TV-OUT & Inverter BD CONN.
Custom25 66, 07, 2003星期四 八月
Compal Electronics, Inc.
LCD CONN
CRT CONNECTOR
SI2302DS: N CHANNELVGS: 4.5V, RDS: 85 mOHMVGS: 2.5V, RDS: 115mOHMId(MAX): 2.8AVGS(MAX): +-8V
SI2301DS: P CHANNELVGS: -4.5V, RDS: 130 mOHMVGS: -2.5V, RDS: 190mOHMId(MAX): 2.3AVGS(MAX): +-8V
TFT LCD CONN.
TFT LCD CONN.
AT LEAST 60 MIL
AT LEAST 60 MIL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PIR BOM 92.07.30
PIR BOM 92.07.30
D43
DAN217_SOT23
231
C117
220P_0402_25V8K
1
2
R1013
M9@10K_5%
12
C108
10P_0402_50V8K
1
2
C890.047U_0402_16V4Z
1
2
G
D
S
Q8
M9@2N7002 1N_SOT232
13
R185
75_0402_5%
12
D21DAN217_SOT23
2 31
G
D S
Q13
2N7002 1N_SOT23
2
1 3
C101
10P_0402_50V8K
1
2
R191
4.7K_0402_5%
C87
0.1U_0402_10V6K
1
2C90
0.1U_0402_10V6K
1
2
D23DAN217_SOT23
2 31
G
D S
Q14
2N7002 1N_SOT23
2
1 3
C618
10U_0805_10V3M
1
2
F1
FUSE_1A
21
C107
220P_0402_25V8K1
2
R1153 20_0402_5%1 2
R187
75_0402_5%
12
L5 FCM2012C-800_08051 2
R175
100K_0402_5%
C620
0.01U_0402_50V7K
1
2
R1007
2.2K_0402_5%
12
C116
220P_0402_25V8K
1
2
D16 RB751V_SOD32321
D17
RB411D_SOT23
2 1
R182100K_0402_5%
L9
FBM-L10-160808-300LM-T1 2
C91
4.7U_0805_10V4Z
1
2
R1118
4.7K_0402_5%
G
D
SQ10
2N7002_SOT23
2
13
JP6
SUYIN_7849S-15G2T-HC
611
17
1228
1339
144
1015
5
C100
10P_0402_50V8K
1
2
R180
1K_0402_1%
12
L6 FCM2012C-800_08051 2
C102
10P_0402_50V8K
1
2
C104
22P_0402_25V8K
1
2
G
D
SQ112N7002_SOT23
2
13
C619
1000P_0402_50V8J
1
2
R1154 20_0402_5%
1 2
U5874AHCT1G125GW
2 4
13
5
R192
4.7K_0402_5%
C970.1U_0402_10V6K
1
2
C864.7U_0805_10V4Z
1
2
C109
10P_0402_50V8K
1
2
R1008
2.2K_0402_5%
12
R1117
4.7K_0402_5%
R174
4.7K_0402_5%
12
R181
150K_0402_5%
D22DAN217_SOT23
2 31
L2
KC FBM-L11-201209-221LMAT_08051 2
L41
KC FBM-L11-201209-221LMAT_08051 2
R186
75_0402_5%
12
C103
22P_0402_25V8K
1
2
L10
FBM-L10-160808-300LM-T1 2
D42
DAN217_SOT23
231
U57 74AHCT1G125GW
2 4
13
5
C105
22P_0402_25V8K
1
2
G
D
S Q9SI2302DS 1N_SOT23
2
13
L3 FCM2012C-800_08051 2
22K
22K Q12
DTC124EK_SOT23
2
13
JP27
M9-M10@JST BM40B-SRDS
1133557799111113131515171719192121232325252727292931313333353537373939
2 24 46 68 8
10 1012 1214 1416 1618 1820 2022 2224 2426 2628 2830 3032 3234 3436 3638 3840 40
C88
0.1U_0402_10V6K
1
2
D41 M10@RB751V_SOD32321
R1115
2.2K_0402_5%
12
JP28
NAGP@JST BM40B-SRDS
1133557799111113131515171719192121232325252727292931313333353537373939
2 24 46 68 8
10 1012 1214 1416 1618 1820 2022 2224 2426 2628 2830 3032 3234 3436 3638 3840 40
R1150
1K_0402
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
A_AD[0..31]
A_CBE#[0..3]
PCI_FRAME#
PCI_PAR
PCI_SERR#
PCI_TRDY#PCI_DEVSEL#PCI_STOP#
PCI_IRDY#
PCI_PERR#
PCI_PIRQD#PCI_PIRQC#PCI_PIRQB#PCI_PIRQA#
PCI_REQ#3
PCI_GNT#2
PCI_REQ#1
PCI_GNT#4
PCI_GNT#0
PCI_REQ#4
PCI_GNT#1
PCI_REQ#0
PCI_REQ#2
PCI_GNT#3
LPC_AD3LPC_AD2LPC_AD1
LPC_DRQ#0
LPC_AD0
CLK_ALINK_SB
H_CPUSLP#
H_SMI#
H_A20M#
H_INTR
H_IGNNE#
H_NMI
H_STPCLK#
H_NMI
H_INTR
LPC_FRAME#
LPC_DRQ#1
SIRQ
PCI_CLKRUN#
H_INIT#
H_INIT#
PCI_RST#
NBRST# NB_RST#
CPURSTIN#
OVCUR#5
H_A20M#
A_SERR#
SBCLK_STP#
CLK_14M_APIC
PCI_CLK_R
PCI_AD4
PCI_USB20
PCI_CBE#3
A_SBREQ#
A_CBE#0
A_AD19
LPC_DRQ#1
PCI_AD25
PCI_AD21
PCI_AD16
PCI_AD12
PCI_AD0
LPC_FRAME#
PCI_CBE#2
PCI_MINI
PCI_PIRQC#
A_OFF#
A_AD29
A_AD21
A_AD5
H_CPUFERR#
PCI_AD26
H_A20M#
RTCX2
A_CBE#2
A_AD30
A_AD8
A_AD0
GPIO0
PCI_REQ#4
PCI_AD31
PCI_AD20
PCI_AD13
PCI_AD10
PCI_AD5
LPC_AD1
PCI_IRDY#
H_CPUFERR#
A_ACAT#
A_AD26
PCI_AD17
PCI_LAN
SBCLK_STP#
A_AD16
RTCX2
PCI_AD18
PCI_AD8PCI_AD7
PCI_AD2
PCI_SIO
A_PAR
A_AD22
A_AD14
PCI_GNT#4
PCI_AD24
PCI_GNT#2
PCI_REQ#2
SB_APIC_D0OVCUR#5
A_STROBE#
A_AD28
NBRST#
CLK_ALINK_SB
PCI_AD28
PCI_AD15
PCI_AD9
SIRQ
LPC_AD3LPC_AD2
PCI_PERR#
PCI_CBE#1
PCI_PIRQA#
A_AD25
PCI_AD3
LPC_AD0
PCI_PCM
A_AD18
PCI_AD22
LPC_DRQ#0
PCI_STOP#
PCI_CBE#0
PCI_1394
PCICLK_STP#
A_DEVSEL#
A_AD20
A_AD13A_AD12
RTCX1
PCI_AD19
PCI_GNT#1
PCI_AD11
PCI_GNT#3
A_AD15
PCI_AD27
PCI_FRAME#
RTCX1
A_SERR#
A_AD27
A_AD17
PCI_AD[0..31]
PCIRST#
PCI_AD1
PCI_DEVSEL#
A_END#
A_AD23
A_AD9
A_AD7
A_AD1
PCI_CBE#[0..3]PCI_AD30
PCI_AD6
PCI_EC
PCI_GNT#0
PCI_REQ#3
PCI_TRDY#
OVCUR#4
A_CBE#1
A_AD31
A_AD10
A_AD2
PCI_AD23
PCI_REQ#1
SB_APIC_D1
CPURSTIN#
A_SBGNT#
A_CBE#3
A_AD11
PCI_AD29
PCI_AD14
PCI_CLKRUN#
PCI_SERR#PCI_REQ#0
PCI_PAR
PCI_PIRQD#
A_AD24
A_AD6
A_AD3
GPIO2
A_AD4PCI_CLK_FB
PCIRST#
PCI_PIRQB#
GPIO1
OVCUR#4
GPIO0
GPIO2
A_SBREQ#<10>
A_AD[0..31]<10,13>
A_CBE#[0..3]<10,13>
A_STROBE#<10>
A_SBGNT#<10>
A_DEVSEL#<10>A_ACAT#<10>A_END#<10>
A_PAR<10,13>
PCI_PIRQA#<10,17,31,35,36>
H_STPCLK#<5>
H_PWRGOOD<5>
H_A20M#<5>H_IGNNE#<5>
H_INIT#<5>
PCI_CBE#[0..3] <31,34,35,36,43>
PCI_AD[0..31] <29,31,34,35,36,43>
H_INTR<5>
H_FERR#<5>
PCI_RST# <11,30,31,34,35,36,43,46>
NB_RST# <8,17,39>
DPRSLPVR<56>
H_RESET#<5,8>
PCI_PIRQC#<36,43>PCI_PIRQD#<34,36>
CLK_PCI_1394 <35>
CLK_PCI_SIO <39>CLK_PCI_EC <46>CLK_PCI_MINI <43>CLK_PCI_PCM <31>CLK_PCI_LAN <34>
CLK_PCI_USB20 <36>
CLK_14M_APIC<24>
CPUCLK_STP#<5,11,56>
PCI_GNT#2 <31>PCI_GNT#1 <34>
PCI_PERR# <31,34,35,36,43>
LPC_AD0 <39,46>
PCI_GNT#4 <36,43>
PCI_REQ#0 <35>
LPC_DRQ#1 <39>
LPC_AD2 <39,46>
PCI_PIRQB#<31>
CLK_ALINK_SB<24>
PCI_REQ#2 <31>
H_NMI<5>
PCI_SERR# <31,34,35,36,43>
PCI_STOP# <31,34,35,36,43>
LPC_FRAME# <39,46>
PCI_REQ#4 <36,43>
H_SMI#<5>LPC_AD1 <39,46>
PCI_GNT#0 <35>
PCI_FRAME# <31,34,35,36,43>
PCI_CLKRUN# <31,34,35,36,43>
PCI_DEVSEL# <31,34,35,36,43>
H_CPUSLP#<5>
PCI_GNT#3 <36,43>
SIRQ <31,39,46>
PCI_IRDY# <31,34,35,36,43>
PCI_REQ#1 <34>
A_OFF#<10>
PCI_PAR <31,34,35,36,43>PCI_TRDY# <31,34,35,36,43>
LPC_AD3 <39,46>
PCI_REQ#3 <36,43>
H_PROCHOT# <5,51>
CHGRTC
+VCC_CORE
+RTCVCC
BATT1.1
+3VS
+3VS
+3V
+3VALW +3VALW
+3VALW
+VCC_CORE
+VCC_CORE
+3VS
+3VS
+3VS
+RTCVCC
+3VS
Title
Size Document Number Rev
Date: Sheet o fLA-1811 0.7
SB200M(1/4)- PCI/CPU/LPC
26 66, 07, 2003星期四 八月
Compal Electronics, Inc.
+
W=15mils
No short
-
Layout note:Trace length of PCI_CLK_R + PCI_CLK_FB shouldbe less than 200 mils.
W=20mils
PULL DOWN FOR S3
PLACE CLOSE TO CPU SOCKET
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
W=20mils
PIR BOM 92.06.23
PIR LAYOUT 92.07.30
RP17
8.2K _8P4R_0804_5%
1 82 73 64 5
R1066 @300_0402_1%1 2
R152 200_0402_5%1 2
R124 33_0402_5%1 2
R1155 10K_0402_5%12
R1156 10K_0402_5%12
R154 200_0402_5%1 2
C973@15P_0402_50V8J
D93RB751V_SOD3232 1
C872
0.1U_0402_10V6K
1
2
Y1
32.768KHZ_12.5P_MC-306
12
43
U45F
SN74LVC14APWLE_TSSOP14
O 12I13
P14
G7
RP13810K_0804_8P4R_5%1 8
2 73 64 5
R126 33_0402_5%1 2
R1067 1K_0402_1%1 2
R150 200_0402_5%1 2
R1151
10K_0402_5%
12
R125 8.2K_0402_5%
R1000
470_0402_5%
12
C76 @22P_0402_50V8J1 2
R138
8.2K_0402_5%
R168
1K_0402_5%
R1059 10K_0402_5%1 2
R40
1K_0402_5%1
2
R149 200_0402_5%1 2
Q5 MMBT3904_SOT232
3 1
R1143@10_0402_5%
12
C82
12P_0402_50V8K
1
2
C78 180P_0603_50V8J12
RP14
8.2K _8P4R_0804_5%
1 82 73 64 5
R132
470_0402_5%
12
R171
20M_0603_5%
1 2
R131330_0402_5%
RP15
8.2K _8P4R_0804_5%
1 82 73 64 5
R127 33_0402_5%1 2
G
D
S
Q118@2N7002_SOT23
2
13
U45E
SN74LVC14APWLE_TSSOP14
O 10I11
P14
G7
R134
@10_0402_5%
12
R1157 10K_0402_5%12
Q98 @MMBT3904_SOT23
2
3 1
RP18
8.2K _8P4R_0804_5%
1 82 73 64 5
R128 33_0402_5%1 2
RP21
100K_1206_8P4R_5%
1 82 73 64 5
R130 33_0402_5%1 2
R145
@4.7K_0402_5%12
U45D
SN74LVC14APWLE_TSSOP14
O 8I9
P14
G7
R146 4.7K_0402_5%12
C79 180P_0603_50V8J12
R172
20M_0603_5%
12
C617 180P_0603_50V8J12
R122 33_0402_5%1 2
R921
4.7K_0402_5%
12
C80
1U_0603_10V6K1
2
R137
8.2K_0402_5%
R169
330_0402_5%
R1064 10K_0402_5%1 2
C77
@15P_0402_50V8J
R1002 47K_0402_5%1 2
R158 200_0402_5%1 2
C81
12P_0402_50V8K
1
2
R946 8.2K_0402_5%
C956 180P_0603_50V8J12
R1021 33_0402_5%1 2
R153 200_0402_5%1 2
RP16
8.2K _8P4R_0804_5%
1 82 73 64 5
R156 200_0402_5%1 2
JOPEN1
12
R123 33_0402_5%1 2
R151 200_0402_5%1 2
R966
10K_0402_5%
12
A-L
INK
INTE
RFA
CE
Part 1 of 3SB200 SB
PC
I IN
TER
FAC
EL
PC
RTC
CP
UXT
AL
PC
I CLK
S
U3A
South bridge SB200
PCICLKFB22A_RST#R22
A_AD0H22A_AD1P23A_AD2L23A_AD3N23A_AD4N22A_AD5M23A_AD6M22A_AD7K22A_AD8M21A_AD9M20A_AD10L21A_AD11K21A_AD12L20A_AD13N21A_AD14K23A_AD15K20A_AD16F23A_AD17G21A_AD18F20A_AD19H21A_AD20F22A_AD21F21A_AD22G20A_AD23E21A_AD24E20A_AD25D23A_AD26D22A_AD27E22A_AD28D20A_AD29C23A_AD30D21A_AD31C22A_CBE#0L22A_CBE#1J23A_CBE#2G22A_CBE#3E23A_STROBE#H20A_DEVSEL#J21A_ACAT#G23A_END#H23A_PARJ20A_OFF#J22A_SERR#P22
PCI_STP#R23
A_SBREQ#B21A_SBGNT#B20
CPU_STP#/DPSLP#N20
A_INTA#C20INTB#P20INTC#B23INTD#P21
RTC_CS#/USBOC3#/GPIO2 AC8
RTC_ALE/USBOC4#/GPIO3 AB7RTC_WR#/RTC_CLKOUT AB8
USBOC5#/GPM1 AA2
X1AC12
X2AC11
VBAT AC10
INTR/LINT0B17
SMI#C16
STPCLK#E16
NMI/LINT1B16
FERR#E19
IGNNE#D17A20M#D18
SLP#F19
INITC17
CPURSTIN#B18
APIC_D0C19APIC_D1C18APIC_CLKB19
GPIO1/ROMCS# AB5
PCICLK0 B15PCICLK1 D16PCICLK2 A14PCICLK3 A15
PCIRST# C15
CBE#0/ROMA10 B3CBE#1/ROMA1 C5
CBE#2/ROMWE# A7CBE#3/RTC_RD# D10
FRAME# B7DEVSEL#/ROMA0 A6
IRDY# C7TRDY#/ROMOE# D7
PAR A5STOP# B6PERR# C6
REQ#0 B12REQ#1 C12REQ#2 D13
REQ#3/PDMAREQ0# A12
GNT#0 A13GNT#1 B13GNT#2 C14
GNT#3/PDMAGNT0# D14
SERR# D6
CLKRUN# A20
LAD0 Y14LAD1 AA14LAD2 AB14LAD3 AA13
LFRAME# AB13LDRQ#0 AC14
SERIRQ AC13
RTC_GND AB11
PCICLK4 A16PCICLK5 A17PCICLK6 D15
AD0/ROMA18 B1AD1/ROMA17 C1AD2/ROMA16 A1AD3/ROMA15 D2AD4/ROMA14 B2AD5/ROMA13 C2AD6/ROMA12 A2AD7/ROMA11 D3
AD8/ROMA9 C3AD9/ROMA8 A3
AD10/ROMA7 D4
AD12/ROMA5 C4AD13/ROMA4 A4AD14/ROMA3 D5AD15/ROMA2 B5AD16/ROMD0 C8AD17/ROMD1 D8AD18/ROMD2 B8AD19/ROMD3 A8AD20/ROMD4 C9AD21/ROMD5 D9AD22/ROMD6 B9AD23/ROMD7 A9
AD24/RTC_AD7 C10AD25/RTC_AD6 B10AD26/RTC_AD5 D11AD27/RTC_AD4 A10AD28/RTC_AD3 C11AD29/RTC_AD2 B11AD30/RTC_AD1 D12AD31/RTC_AD0 A11
AD11/ROMA6 B4
REQ#4/PLLBP33/PDMAREQ1# C13
GNT#4/PLLBP50/PDMAGNT1# B14
LDRQ#1 Y13
SSMUXSEL/GPIO0E17DPRSLPVRE18
PCICLK7 A18PCICLK_FB A19
CPU_PWRGDE4
U45B
SN74LVC14APWLE_TSSOP14
O 4I3
P14
G7
R100147K_0402_5%
12
BATT1
RTCBATT
1 2
R1065 10K_0402_5%1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LPC_SMI#
AC97_SDOUT_R
AC97_RST#
AC97_SDIN0
CLK_SB_48M
AC97_BITCLK
AC97_SYNC_R
LPC_PME#SB_AC_IN
SB_SCI#
USB_RCOMP
SUS_STAT#
SB_EC_SMI#
SB_TEST1
SB_PM_BATLOW#
SB_PWRGD
SLP_S5#SLP_S3#
PWRBTN_OUT#
SB_TEST0
SB_LID_OUT#
OVCUR#1
OVCUR#1
USB20P5-
PWR_STRP
AC97_BITCLK
AC97_SDIN1AC97_SDIN0
AC97_RST#
PCI_ACT_REQ#
SB_EC_SWI#
SB_GA20SB_KBRST#
LPC_SMI#
LPC_PME#
IDESAA0IDESAA1IDESAA2
IDEIORDYAIDEIRQA
IDEDA7
IDEDA13
IDEDA9
IDEDA0IDEDA1
IDEDA15IDEDA14
IDEDA8
IDEDA4IDEDA5IDEDA6
IDEDA12
IDEDA10IDEDA11
IDEDA2IDEDA3
IDEDACK#AIDEREQAIDEIOR#AIDEIOW#AIDECS#A1IDECS#A3
IDEREQBIDEDACK#B
IDESAB1
IDEIRQBIDEIORDYB
IDESAB0
IDEIOR#B
IDECS#B3
IDEIOW#BIDECS#B1
IDESAB2
IDEDB0IDEDB1IDEDB2IDEDB3
IDEDB7
IDEDB4IDEDB5IDEDB6
IDEDB11
IDEDB8IDEDB9IDEDB10
IDEDB15
IDEDB12IDEDB13IDEDB14
AC97_SDOUT
AC97_SDIN1
SB_SPKR
AC97_SDIN2AC97_SYNC
AC97_SDIN2
USB20P3-
USB20P0-
IDERSTHD#
CLK_SB_14M
EC_RSMRST#
32KHZ_S5_OUT
MII_TXD3MII_TXD2MII_TXD1MII_TXD0
MII_TXEN
SB_EEDOSB_EECLK
SPDIF_OUT
SMB_CK_CLK2_SBSMB_CK_DAT2SMB_CK_CLK2
SMB_CK_DAT2_SB
CLK_SB_48M
AC97_BITCLK
IDERSTCD#
SB_SCI#
SB_LID_OUT#SB_EC_THERM#SB_PM_BATLOW#
AGP_BUSY#_RAGP_STP#_R
USB20P5+
SB_AC_IN
SB_EC_SMI#SB_EC_SWI#
SB_EC_THERM#
SB_KBRST#
SB_GA20
SUS_STAT#
PCI_ACT_REQ#
SLP_S3#PWRBTN_OUT#
SLP_S5#
AGP_STP#_R
VGATE
CLK_SB_14M
GHI
AGP_BUSY#AGP_BUSY#_R
AGP_BUSY#_R
USB20P0+USB20P1-USB20P1+
USB20P0-
USB20P1-
USB20P0+
SB_PM_BATLOW#
SB_EC_THERM#
SB_EC_SWI#
PM_BATLOW#
EC_THERM#
EC_SWI#
ACINSB_AC_IN
SB_KBRST#
SB_GA20 GA20
KBRST#
EC_SMI#
LID_OUT#SB_LID_OUT#
SB_EC_SMI#
SB_SCI# SCI#
IDERSTHD#
IDERSTCD#
AGP_STP#
SB_TEST0SB_TEST1
AGP_BUSY#AGP_STP#
LPC_SMI# USB_SMI#
USB20P4-
USB20P2+
USB20P2-
USB20P1+
USB20P3+
USB20P4+
SMB_CK_DAT2SMB_CK_CLK2_SBSMB_CK_DAT2_SB
SMB_CK_CLK2
EC_FLASH#
IDERST_HD#
IDERST_CD#
GHI
USB20P3-
USB20P2-USB20P3+
USB20P2+
USB20P5+USB20P5-
USB20P4+USB20P4-
SLP_S5# <46>SLP_S3# <46>
PWRBTN_OUT# <46>SB_PWRGD <48>
SUS_STAT# <8>
AC97_SYNC <29,37,44>AC97_RST# <37,44>
AC97_BITCLK <37,44>
AC97_SDIN1 <44>
AC97_SDOUT <29,37,44>AC97_SDIN0 <37>
SB_SPKR<37>
CLK_SB_48M<24>
USB20P5-<44>
USB20P5+<44>
CLK_SB_14M<24>
EC_RSMRST#<46>
OVCUR#0<44>
32KHZ_S5_OUT<29>
SB_EEDO<29>
SPDIF_OUT <29,37>
MII_TXD1<29>
SB_EECLK<29>
MII_TXEN<29>
MII_TXD2<29>
MII_TXD0<29>
MII_TXD3<29>
EC_FLASH#<47>
IDEIOR#A <30>
IDESAA0 <30>IDEIRQA <30>
IDECS#A1 <30>
IDEDACK#A <30>
IDEIORDYA <30>
IDESAA1 <30>IDESAA2 <30>
IDECS#A3 <30>
IDEREQA <30>
IDEIOW#A <30>
IDESAB2 <30>
IDEREQB <30>
IDECS#B3 <30>IDECS#B1 <30>
IDEIOR#B <30>IDEIOW#B <30>
IDESAB1 <30>
IDEIORDYB <30>IDEIRQB <30>IDESAB0 <30>
IDEDACK#B <30>
IDEDB[0..15] <30>
IDEDA[0..15] <30>
OVCUR#1<44>
AGP_BUSY# <10,17>
IDERST_CD#<30>
IDERST_HD#<30>
AGP_STP#<10,17>
VTT_PWRGD <24,46,48>
USB_SMI# <36>
EC_THERM# <46>
PM_BATLOW# <46>
EC_SWI# <46>
GA20 <46>
KBRST# <46>
ACIN <46,50,53>
EC_SMI# <46>
SCI# <46>
LID_OUT# <46>
USB20P0+<44>
USB20P0-<44>
USB20P2-<44>
USB20P2+<44>
USB20P3-<44>
USB20P4-<41>
USB20P4+<41>
USB20P3+<44>
USB20P1-<44>
USB20P1+<44> PWR_STRP <29>
CPU_GHI#<5>
SMB_CK_CLK2 <14,15,24>SMB_CK_DAT2 <14,15,24>
+3VS
+2.5V
+3V
+3V
+3VALW
+3VS
+3VS
+3VS
+5VS
+3V
Title
Size Document Number Rev
Date: Sheet o fLA-1811 0.7
SB200M(2/4) - IDE/USB/MII
27 66, 07, 20星期四 八月 03
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Note: Place close to U3 (ATI SB)For ATI USB2.0 only .
L
PIR BOM & LAYOUT 92.07.30
PIR BOM 92.07.30
R952@10K_0402_5%
12
R120 10K_0402_5%1 2
RP107
10K_0804_8P4R_5%
1 82 73 64 5
RP12 2.2K_0804_8P4R_5%
1 82 73 64 5
RP108
10K_0804_8P4R_5%
1 82 73 64 5
R951 10K_0402_5%12
R71
@10_0402_5%
12
RP13 8.2K _8P4R_0804_5%
1 82 73 64 5
R68 10K_0402_5%1 2
D7 RB751V_SOD3232 1
D77RB751V_SOD323
2 1
D4 RB751V_SOD3232 1
D6 RB751V_SOD3232 1C73
@15P_0402_50V8J
R6312.4K_0603_1%
D11 RB751V_SOD3232 1
R950 10K_0402_5%12
RP11 10K_0804_8P4R_5%
1 82 73 64 5
R948 10K_0402_5%12
G
D S
Q89 2N7002 1N_SOT23
2
1 3
D9 RB751V_SOD3232 1
RP112
15K_1206_8P4R_5%
1 82 73 64 5
RP109
10K_0804_8P4R_5%
1 82 73 64 5
SEC
ON
DAR
Y AT
A 66
/100
PRIM
ARY
ATA
66/1
00AC
PI /
WAK
E U
P EV
ENTS
Part 2 of 3SB200 SB
AC
97
US
B IN
TER
FAC
EE
THER
NET
MII
EE
PR
OM
CLK
/ R
ST
GPI
OG
PIO
_XTR
A
U3B
South bridge SB200
TALERT#/ETH_TALERT# AB4
PME#/EXT_EVNT0# AC9RI#/EXT_EVNT1# AC7
SLP_S3# AA11SLP_S5# AB10
PWR_BTN# AA10
PCI_REQACT# C21SUS_STAT# Y10
TEST1 AA5
32KHZ_IN/GPM3W11USBOC1#/GPM4AB1SPEAKER/GPM5Y4FANOUT0/GPM6AA1
RSMRST#AB9
GEVENT5#/ETH_VALERT# Y8
GPOC0#/SCL0 AA12GPOC1#/SDA0 W12GPOC2#/SCL1 Y12GPOC3#/SDA1 AB12
PWR_GOOD Y11
PIDE_IORDY AB17PIDE_IRQ AC16
PIDE_A0 AB15PIDE_A1 AB16PIDE_A2 AC15
PIDE_DACK# Y16PIDE_DRQ AA17PIDE_IOR# AA16
PIDE_IOW# AC17PIDE_CS1# Y15PIDE_CS3# AA15
PIDE_D0 AC18PIDE_D1 AA18PIDE_D2 AC19PIDE_D3 AA19PIDE_D4 AC20PIDE_D5 AA20PIDE_D6 AC21PIDE_D7 AB21PIDE_D8 AA21PIDE_D9 Y20
PIDE_D10 AB20PIDE_D11 Y19PIDE_D12 AB19PIDE_D13 Y18PIDE_D14 AB18PIDE_D15 Y17
SIDE_IORDY AA23SIDE_IRQ AA22
SIDE_A0 AC23SIDE_A1 Y21SIDE_A2 AB23
SIDE_DACK# Y22SIDE_DRQ W21SIDE_IOR# Y23
SIDE_IOW# W20SIDE_CS1# AC22SIDE_CS3# AB22
SIDE_D0 W23SIDE_D1 V21SIDE_D2 V23SIDE_D3 U21SIDE_D4 U23SIDE_D5 T21SIDE_D6 T23SIDE_D7 R21SIDE_D8 R20SIDE_D9 T22
SIDE_D10 T20SIDE_D11 U22SIDE_D12 U20SIDE_D13 V22SIDE_D14 V20SIDE_D15 W22
AC_BITCLK E1AC_SDOUT E2
AC_SDIN0 Y1AC_SDIN1 Y2AC_SDIN2 Y3AC_SYNC E3AC_RST# V5
SPDIF_OUT E5
USBCLK/CLK48P3
USB_HSDP0+F1
TEST0 AA6
GEVENT6#/ETH_FALERT# AA7GEVENT7#/ETH_CALERT# AB6
LPC_SMI#/GEVNT4# W5LPC_PME#/GEVNT3# Y6
KB_RST#/GEVNT1# AA4GA20_IN/GEVNT0# Y5
SMB_ALERT#/GEVNT2# AB3
USB_RCOMPR1
USB_ATEST1N4USB_ATEST0N3USBOC0#/GPM7P4
USB_FLDP0+F2USB_HSDM0-G1USB_FLDM0-G2
USB_HSDP5+M2USB_FLDP5+M1USB_HSDM5-N2USB_FLDM5-N1
USB_HSDP4+L4USB_FLDP4+L3USB_HSDM4-M4USB_FLDM4-M3
USB_HSDP3+K2USB_FLDP3+K1USB_HSDM3-L2USB_FLDM3-L1
USB_HSDP2+H2USB_FLDP2+H1USB_HSDM2-J2USB_FLDM2-J1
USB_HSDP1+G3USB_FLDP1+J3USB_HSDM1-H3USB_FLDM1-K3
MCOLR5MCRSW1MDCKV4MDIOV2
RX_CLKT1
RXD3T3RXD2U2RXD1T5RXD0W4
RX_DVT2RX_ERRU1
TX_CLKT4
TXD3U4TXD2V1TXD1U3TXD0V3
TX_ENW2
PHY_RST#U5 PHY_PDW3
EE_CSP2EE_DIR3EE_DOR2EE_CKR4
OSC_INA23
SIO_CLKW6
FANOUT1/USBOC2#/GPM2AA3 BLINK/GPM0AB2
USB_VREFOUTP1
CLK_25MY7
GPIO_X0/AGP_STP#AC1GPIO_X1/AGP_BUSY#AC6GPIO_X2/GHI#AC2GPIO_X3/VGATEAC3GPIO_X4AC4GPIO_X5AC5
RTC_IRQ#/PWR_STRP AA8
D3 RB751V_SOD3232 1
D8 RB751V_SOD3232 1
D10 RB751V_SOD3232 1
RP110
10K_0804_8P4R_5%
1 82 73 64 5
R92
@10_0402_5%
12
R117 33_0402_5%
R1003
33_0402_5%
12
D13 RB751V_SOD3232 1
R119 33_0402_5%
D14 RB751V_SOD3232 1
R112 100K_0402_5%
R1062 0_0603_5%1 2
R934 1K_0603_5%1 2
R947 10K_0402_5%12
C74
@15P_0402_50V8J
RP111
15K_1206_8P4R_5%
1 82 73 64 5
R111 8.2K_0402_5%
D2 RB751V_SOD3232 1
RP113
15K_1206_8P4R_5%
1 82 73 64 5
R121 10K_0402_5%1 2
D5 RB751V_SOD3232 1
R64
@10_0402_5%
12
R69 4.7K_0402_5%1 2
RP140 8.2K _8P4R_0804_5%
1 82 73 64 5
C75
@15P_0402_50V8J
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+3VS +3VS
+2.5VS
+2.5V
+3V
+2.5VS
+2.5VALW
+3VALW
+2.5VS
+3V_AVDDUSB
+3V_AVDDUSB
+3V_AVDDC
+3V_AVDDC
+2.5V_AVDDCK
+2.5VS
+2.5V_AVDDCK
+3V
+3V
+3V
+2.5V
+3VS
+2.5VS
+3V
+3V_AVDDUSB
+3V_AVDDC
+2.5V_AVDDCK
+2.5V
+5VS
+3VS
Title
Size Document Number Rev
Date: Sheet o fLA-1811 0.7
SB200M(3/4) - PWR
28 66, 07, 2003星期四 八月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ATI request
ATI request
ATI request
ATI request
ATI request
ATI request
ATI requestCLOSE TOL6,H6,J6
C35
0.1U_0402_10V6K
1
2
C887
@10U_0805_10V6K
C34
0.1U_0402_10V6K
1
2
C46
0.1U_0402_10V6K
1
2
+C888
@47U_B_6.3VM
1
2
C24
22U_1206_16V4Z_V1
1
2
R1114
1K_0402_5%
12
C27
0.1U_0402_10V6K
1
2
C66
0.1U_0402_10V6K
1
2
C63
0.1U_0402_10V6K
1
2
C64
0.1U_0402_10V6K
1
2
C51
0.1U_0402_10V6K
1
2
C49
22U_1206_16V4Z_V1
1
2
C53
0.1U_0402_10V6K
1
2
C877
@0.01U_0402_16V7Z
1
2
R62 0_0805_5%1 2
Part 3 of 3SB200 SB
POW
ER
U3C
South bridge SB200
VSS N10VSS M9VSS M6VSS M15VSS M14VSS M13VSS M12VSS M11VSS M10VSS L19VSS L18VSS L14VSS L13VSS L12VSS L11VSS L10VSS K19VSS K18VSS K14VSS K13VSS K12VSS K11VSS K10VSS J9VSS J19VSS J18VSS J15VSS J12VSS G6VSS F9VSS F6VSS F18VSS F14VSS F13VSS F10VSS E9
VDDQE11VDDQE12VDDQE15VDDQE7VDDQE8VDDQF11VDDQF12VDDQF15VDDQF16VDDQF17VDDQF7VDDQF8VDDQG18VDDQG19VDDQH18VDDQH19VDDQM18VDDQM19VDDQN18VDDQN19VDDQT18VDDQT19VDDQU18VDDQU19VDDQV17VDDQV18
VREF_CPUD19
5V_VREFD1
STB_3.3VW9STB_3.3VW10
VDD_COREK15
VDD_COREJ11
VDD_COREJ14
VDD_COREL15
VDD_COREN15
VDD_COREK9
VDD_COREJ10
VDD_COREJ13
VDD_COREL9
VSS E6VSS E14VSS E13VSS E10
STB_3.3VV11 STB_3.3VV10 STB_3.3VV9 STB_3.3VU6 STB_3.3VT6
AVDD_CKA21
AVSSCK A22
AVDDTX0F4AVDDTX1J4AVDDTX2K5AVDDRX0F3AVDDRX1K4AVDDRX2L5
AVSSTX0 F5AVSSTX1 H4AVSSTX2 K6
AVSSRX1 J5AVSSRX0 G4
AVSSRX2 M5
VSS N11VSS N12VSS N13VSS N14VSS N6VSS P10VSS P11VSS P12VSS P13
STB_2.5VW13 STB_2.5VV13 STB_2.5VR6 STB_2.5VP6
VDD_COREN9VDD_COREP15VDD_COREP9
AVDDCP5
VDD_USBJ6 VDD_USBH6 VDD_USBL6
VSS_USB H5VSS_USB G5
AVSSC N5
VDDQW17VDDQW18
VSS P14VSS P18VSS P19VSS R12VSS R15VSS R18VSS R19
VDD_CORER10VDD_CORER11VDD_CORER13VDD_CORER14
VSS R9VSS V14VSS V15VSS V16VSS V19VSS V6VSS V7VSS V8VSS W14VSS W15VSS W16VSS W19
S5_2.5VY9
S5_3.3VAA9
STB_2.5VV12
VSS W7VSS W8
C40
22U_1206_16V4Z_V1
1
2
C69
0.1U_0402_10V6K
1
2
C47
0.1U_0402_10V6K
1
2
C67
0.1U_0402_10V6K
1
2
C59
1U_0603_10V6K
1
2
C30
0.1U_0402_10V6K
1
2
C882
@0.1U_0402_16V7K
C55
0.1U_0402_10V6K
1
2
C32
0.1U_0402_10V6K
1
2
C878
@0.01U_0402_16V7Z
1
2
C62
22U_1206_16V4Z_V1
1
2
C28
0.1U_0402_10V6K
1
2
C72
0.1U_0402_10V6K
1
2
C880
@0.01U_0402_16V7Z
1
2
C874
@0.01U_0402_16V7Z
1
2
C65
0.1U_0402_10V6K
1
2
C39
0.1U_0402_10V6K
1
2
C70
0.1U_0402_10V6K
1
2
C29
0.1U_0402_10V6K
1
2
C883
@0.1U_0402_16V7K
C42
0.1U_0402_10V6K
1
2
C58
0.1U_0402_10V6K
1
2
C48
0.1U_0402_10V6K
1
2
C57
0.1U_0402_10V6K
1
2
C44
0.1U_0402_10V6K
1
2
C843
1U_0603_10V6K
1
2
C886
@0.1U_0402_16V7K
C876
@0.01U_0402_16V7Z
1
2
C881
@0.01U_0402_16V7Z
1
2
C36
0.1U_0402_10V6K
1
2
C885
@0.1U_0402_16V7K
C25
0.1U_0402_10V6K
1
2
C873
@0.01U_0402_16V7Z
1
2
C60
0.1U_0402_10V6K
1
2
C43
0.1U_0402_10V6K
1
2
C68
0.1U_0402_10V6K
1
2
C37
0.1U_0402_10V6K
1
2
C966
0.1U_0402_16V7K
D90
RB751V_SOD323
2 1
C56
0.1U_0402_10V6K
1
2
R61 0_0805_5%1 2
C879
@0.01U_0402_16V7Z
1
2
C26
0.1U_0402_10V6K
1
2
C71
1U_0603_10V6K
1
2
R60 0_0805_5%1 2
C50
0.1U_0402_10V6K
1
2
C875
@0.01U_0402_16V7Z
1
2
C45
0.1U_0402_10V6K
1
2
C41
0.1U_0402_10V6K
1
2
C2322U_1206_16V4Z_V1
1
2
C889
@22U_1206_16V4Z_V1
1
2
C31
0.1U_0402_10V6K
1
2
C54
22U_1206_16V4Z_V1
1
2
C52
0.1U_0402_10V6K
1
2
C33
0.1U_0402_10V6K
1
2
C38
0.1U_0402_10V6K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PWR_STRP<27>SB_EEDO<27>
SB_EECLK<27>AC97_SYNC<27,37,44>
AC97_SDOUT<27,37,44>SPDIF_OUT<27,37>
MII_TXEN<27>MII_TXD3<27>MII_TXD2<27>MII_TXD1<27>MII_TXD0<27>
32KHZ_S5_OUT<27>
PCI_AD26<26,31,34,35,36,43>
+3VS+3VALW +3V +3V +3VS +3VS +3V +3V +3V +3V +3V +3VALW
+3VS
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
SB200M(4/4) - STRAPS
29 66, 07, 2003星期四 八月
Compal Electronics, Inc.
SIO 24MHzUSEDEBUGSTRAPS
CPU_STP#
STRAPHIGH
ROM ONLPCBUS
ROM ONPCI BUS
DEFAULT
INIT ACTIVEHIGH
DEFAULT
PROCESSOR FREQ MULTIPLIER
SIO 48MHzAUTOPWRON
ETHERNET TXD[3:0]AC_SDOUT SPDIF_OUTPWR_STRP
ENABLESPEEDSTEP
DISABLESPEEDSTEP
DEFAULT
REQUIRED SYSTEM STRAPS AC_SYNC
INIT ACTIVELOW (PIII)
33MHz NBBUS
EEDO
DEFAULT
DEFAULT DEFAULT
EECK
HI SPEEDA-LINKSTRAP
LOW
IGNOREDEBUGSTRAPSDEFAULT
DISABLECPU FREQSETTING
ENABLE CPUFREQSETTING
TX_ENIGN DEBUG SPEEDSTEP FREQLTCH
MANUALPWR ON
DEFAULT
32KHZ_S532KHZOUTPUTFROM SB200(INT RTC)
32KHZ INPUTTO SB200(EXT RTC)
DEFAULT
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R967
10K_0402_5%
12
R42
10K_0402_5%
R48
10K_0402_5%
12
R37
@10K_0402_5%
R44
10K_0402_5%
R35
@10K_0402_5%
R39
@10K_0402_5%
R59
@10K_0402_5%
R45
10K_0402_5%
R57
@10K_0402_5%
R41
10K_0402_5%
12
R54
@10K_0402_5%
R50
10K_0402_5%1
2R51
10K_0402_5%
12
R58
@10K_0402_5%
R46
10K_0402_5%
12
R953
@10K_0402_5%
12
R43
10K_0402_5%
R52
10K_0402_5%
12
R55
@10K_0402_5%
R34
10K_0402_5%
12
R36
@10K_0402_5%
R38
@10K_0402_5%
R56
@10K_0402_5%
R47
@10K_0402_5%
R49
10K_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SD_D15
IDEDA[0..15]
PD_A2
SD_SBA2
SD_SIOW#
PD_IRQA
PD_DACK#
SD_D1
PD_A1
PD_CS#3IDESAA2
SD_D2
PD_IOR#
SD_DACK#
PD_A0
SD_SBA1
SD_SIOR#
SD_SBA0
PD_IOW#
SD_SCS3#
SD_DREQ
SD_D4
IDESAB1
SD_D14
SD_D12
PD_DREQ#
IDESAB0
SD_D3
SD_D11
SD_D9
SD_IDERST#
SD_D0
HD_IDERST#
SD_D13
IDECS#A3
SD_D5
SD_D8SD_D7
SD_D10SD_D6
IDESAA0IDESAA1
HDD_LED#
CDLED#
PD_D4PD_D5
PD_A2
PD_D12
PD_A0PD_A1
PD_D14
HDD_LED#
PD_D11
PCSEL
HD_IDERST#
PD_IOR#
PD_DACK#
PD_D3
PD_IOW#
PD_D9
PD_D1
PD_D6
PD_D2
PD_DREQ#
PD_CS#3
PD_D15
PD_D13
PD_CS#1
PD_D10
PD_D8
PD_IRQA
PD_IORDY
PD_D7
PD_D0
SD_DREQ
CDROM_L
SD_D9
SD_SIOW#
SD_D4
CDLED#
SD_IDERST#
SD_DACK#
SD_SBA2
SD_D11
SD_D3
SD_CSEL
SD_D8
SD_D2
SD_D6
SD_SIORDY
SD_D0
SD_IRQ15
SD_D12
SD_SCS3#SD_SCS1#
SD_D1SD_D14SD_D15
SD_D7
SD_SBA1
CD_AGND
SD_D13
SD_D10
SD_SIOR#
CDROM_R
SD_DREQ
SD_SBA0
SD_D5
IDEDB[0..15]
IDEDB0
IDEDB10
IDEDB7
IDEDB2
IDEDB3
IDEDB5
IDEDB1IDEDB14
IDEDB11
IDEDB13
IDEDB15
IDEDB6
IDEDB9
IDEDB8
IDEDB12
IDEDB4
PD_D14PD_D1
PD_D0PD_D15
IDEDA6IDEDA9
IDEDA8IDEDA7
PD_D9
PD_D8PD_D6
PD_D7
IDEDA3IDEDA12
IDEDA2IDEDA13
PD_D3PD_D12
PD_D2PD_D13
PD_IORDY
SD_SIORDY
SD_SCS1#
PD_CS#1
SD_IRQ15
IDEDA10
IDEDA14
IDEDA4IDEDA11
IDEDA1
IDEDA0
IDEDA5
IDEDA15
PD_D11PD_D10PD_D5
PD_D4
IDECS#A3<27>
IDEIOW#A<27>
IDEIRQA<27>
IDEREQA<27>
IDEDA[0..15]<27>
IDEDACK#A<27>
PCI_RST#<11,26,31,34,35,36,43,46>
IDERST_CD#<27>
IDERST_HD#<27>
IDEIOR#A<27>
IDESAA0<27>IDESAA1<27>IDESAA2<27>
ACT_LED# <45>
CD_AGND <37>
CDROM_R <37>CDROM_L<37>
IDECS#B3<27>
IDESAB0<27>
IDESAB2<27>
IDEIRQB<27>
IDEIOW#B<27>IDEIOR#B<27>
IDESAB1<27>
IDEREQB<27>
IDEDACK#B<27>
IDEDB[0..15]<27>
IDEIORDYA<27>
IDEIORDYB<27>
IDECS#B1<27>
IDECS#A1<27>
+5VS
+5VS
+5VS+5VS
+5VS
+5VS
+5VS
+5VS
+5VS+5VS
+5VS
+5VS +5VS+5VS
+5VS+5VS
+3VS
+3VS
+5VS
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
HDD & CDROM Connector
30 66, 07, 2003星期四 八月
Compal Electronics, Inc.+5VCD trace to CONN W=100mils
W=100mils
HDD/CD-ROM Module
Placea caps. near CDROM CONN.
W=100mils
+5VCD trace to CONN W=100milsPlacea caps. near CDROM CONN.
Placea caps. near HDD CONN.
W=80mils
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PIR BOM 92.07.30
R970 33_0402_5%1 2
C5
0.1U_0402_10V6K
1
2
C12@47P_0402_25V8K
1 2
C2
10U_0805_16V4Z
1
2
R26 33_0603_1%
C17
1000P_0402_50V7K
1
2
U1C
74HCT08PW_TSSOP14
I09
I110 O 8
RP3 33_0804_8P4R_5%1 82 73 64 5
R613 @100K_0402_5%1 2
C84.7U_0805_10V4Z
1
2
U1B
74HCT08PW_TSSOP14
I04
I15 O 6
R9 470_0402_5%1 2RP4 33_0804_8P4R_5%
1 82 73 64 5
RP9 33_0804_8P4R_5%1 82 73 64 5
R31 33_0603_1%
U1A
74HCT08PW_TSSOP14
I01
I12 O 3
P14
G7
R310K_0402_5%
12
C19
1U_0603_10V6K
1
2
RP7 33_0804_8P4R_5%1 82 73 64 5
R338.2K_0402_5%
12
JP1
SUYIN_200006FA044S503ZU
1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 44
R15
10K_0402_5%1 2
C3
10U_0805_16V4Z
1
2
R32
5.6K_0402_5%
12
RP124 33_0804_8P4R_5%1 82 73 64 5
R614470_0402_5%
12
RP1 33_0804_8P4R_5%1 82 73 64 5
C18
10U_0805_16V4Z
1
2
R1110 @10K_0402_5%1 2
C21
1000P_0402_50V7K
1
2
JP2
CD-ROM CONN.
1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 50
C20
0.1U_0402_10V6K
1
2
RP8 33_0804_8P4R_5%1 82 73 64 5
R24
10K_0402_5%1 2
C14
10U_0805_16V4Z
1
2
C11 @10U_0805_6.3V6M12
RP2 33_0804_8P4R_5%1 82 73 64 5
RP10 33_0804_8P4R_5%1 82 73 64 5
R18 33_0603_1%
R25
4.7K_0402_5%
12
R969 33_0402_5%1 2
U1D
74HCT08PW_TSSOP14
I012
I113 O 11
R11 33_0603_1%
C2233P_0402_25V8K1 2
C1
1000P_0402_50V7K
1
2
C15
1U_0603_10V6K
1
2
RP5 33_0804_8P4R_5%1 82 73 64 5
R84.7K_0402_5%
12
R9688.2K_0402_5%
12
C6
4.7U_0805_10V4Z
1
2
RP125 33_0804_8P4R_5%1 82 73 64 5
C91U_0603_25V4Z
1
2
R19
5.6K_0402_5%
12
R4 33_0402_5%1 2
C4
1U_0603_10V6K
1
2
RP6 33_8P4R_0804_5%1 82 73 64 5
C16
0.1U_0402_10V6K
1
2
R61110K_0402_5%
12
C7
1U_0603_25V4Z
1
2
C610 0.1U_0402_10V6K
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
S2_D[0..15]
S2_A[0..25]
S1_A[0..25]
S1_D[0..15]
PCI_AD[0..31]
PCI_CBE#[0..3]
S1_A21
S1_A7
S2_D7
S2_A4
S1_A18
S1_A10
PC
I_C
BE
#0
PC
I_A
D3
PC
I_A
D16
PC
I_A
D19
PC
I_A
D23
S2_D15
S2_A20
S2_A12
S1_D8
PC
I_A
D24
S2_D12
S2_D2
S1_D12
S1_D2
S1_A19
S1_A4
PC
I_C
BE
#3
PC
I_A
D0
PC
I_A
D10
PC
I_A
D28
S2_A8
S1_A1
PC
I_A
D1
PC
I_A
D11
S2_D0
S2_A15
S2_A23
S1_A9
S1_A17
S1_A24
S1_A2
PC
I_A
D2
PC
I_A
D15
PC
I_A
D31
S2_D10
S2_A10
S2_A3S2_A2
PC
I_A
D20
_R
S1_D7
S1_A11
PC
I_A
D6
PC
I_A
D22
S2_D11
S2_D1
S2_A19
S2_A11
S1_D11
S1_D1
S1_A13
PC
I_C
BE
#2
PC
I_A
D9
PC
I_A
D27
PC
I_A
D30
S2_D5
S2_A6
S1_D15
S2_A7
S1_D6
S1_D0
S1_A16S1_A15
S1_A23
PC
I_A
D14
S2_D9
S2_A14
S2_A22
S1_A5
S1_A3
PC
I_A
D5
PC
I_A
D12
PC
I_A
D18
PC
I_A
D21
S2_D14
S2_A9
S2_A1
S1_D10
PC
I_C
BE
#1
PC
I_A
D8
PC
I_A
D26
PC
I_A
D29
S2_A18
S2_D4
S2_A25
S1_D14
S1_D4
S2_A5
S1_D5
S1_A22
S1_A8
S1_A25
S1_A6
S1_A0
PC
I_A
D13
S2_D13
S2_D8
S2_A21
S2_A13S1_A14
PC
I_A
D4
PC
I_A
D7
PC
I_A
D17
PC
I_A
D20
S2_A0
S1_D9
PC
I_A
D25
S2_D3
S1_D13
S1_D3
S1_A20
S1_A12
S2_D6
S2_A16S2_A17
S2_A24
CLK_PCI_PCM
PCI_AD20
PCI_REQ#2 <26>
PCM_PME# <34,36,43,46,47>
PCI_PAR <26,34,35,36,43>PCI_FRAME# <26,34,35,36,43>PCI_TRDY# <26,34,35,36,43>PCI_IRDY# <26,34,35,36,43>PCI_STOP# <26,34,35,36,43>PCI_DEVSEL# <26,34,35,36,43>
PCI_PERR# <26,34,35,36,43>PCI_SERR# <26,34,35,36,43>
PCI_GNT#2 <26>CLK_PCI_PCM <26>PCI_RST# <11,26,30,34,35,36,43,46>
S2_INPACK#<32,33>
S2_WAIT#<32,33>
S2_CE1#<32,33>
S2_WP<32>
S2_CE2#<32>
S2_WE#<32,33>
S2_IORD#<32>
S2_OE#<32,33>S2_REG#<32,33>
S2_RST<32,33>
S2_VS1<32,33>S2_VS2<32,33>
S2_CD1#<32,33>S2_CD2#<32,33>
S2_BVD1<32,33>
S2_BVD2<32,33>
S1_BVD2 <32>
S1_WP <32>
S1_VS2 <32>
S1_IOWR# <32>
S1_RDY# <32>
S1_CD1# <32>
S1_BVD1 <32>
S1_VS1 <32>
S1_INPACK# <32>
S1_WAIT# <32>
S1_RST <32>
S1_OE# <32>
S1_WE# <32>
S1_REG# <32>S1_IORD# <32>
S2_IOWR#<32>
PCM_SUSP#<46>
PCI_CLKRUN#<26,34,35,36,43>
SIRQ<26,39,46>
S2_RDY#<32,33>
CLK_SD_48M <24>
PCI_PIRQA#<10,17,26,35,36>PCI_PIRQB#<26>
CARD_LED#<42>
S2_D[0..15]<32,33>
S2_A[0..25]<32,33>
S1_D[0..15]<32>
PCI_CBE#[0..3]<26,34,35,36,43>
RTCCLK<32>
S1_CD2# <32>
SLDATA<32>
SLATCH<32>PCM_SPK#<37>
S1_A[0..25]<32>
PCI_AD[0..31]<26,29,34,35,36,43>
S1_CE1# <32>S1_CE2# <32>
G_RST# <32,36,46>
+3V
+S1_VCC
+S2_VCC
+3V+3VS
+3V
+3V
+3V
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
CardBus Controller OZ6912/CB1410 & Socket
31 66, 07, 2003星期四 八月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C899
0.01U_0402_16V7K
1
2
R8330_0402_5%
12
C903
0.01U_0402_16V7K
1
2
R1018@10K_0402_5%
CARDBUS CONTROLLERPCI1520 PBGA 209
SLOT B
SLOT A
PCI INTERFACE
POWER
GROUND
FUNCTION
U37
PCI1520GHK_PBGA209
VCC
AP1
9
A_CAD15/A_IOWR# R14A_CAD13/A_IORD# V15
A_CAD11/A_OE# W15
A_CAD10/A_CE2# U14
A_CC/BE3#/A_REG# K14
A_CC/BE0#/A_CE1# V14
A_CSERR#/A_WAIT# H18
A_CREQ#/A_INPACK# K17
A_CGNT#/A_WE# P18
A_CSTSCHG/A_STSCHG# H14A_CCLKRUN#/A_IOIS16# H15
A_CINT#/A_IREQ# H19
A_CRST#/A_RESET L15
A_CAUDIO/A_SPKR# H17
A_CCD1#/A_CD1# U11A_CCD2#/A_CD2# G18
A_CVS1/A_VS1# J15A_CVS2/A_VS2# L18
VCC
PA1
0
MFU
NC
0D
19M
FUN
C1
A16
MFU
NC
2E1
4M
FUN
C3
F13
MFU
NC
4B1
5M
FUN
C5
A15
MFU
NC
6C
14N
CW
11
B_CAD26/B_A0R8B_CAD25/B_A1W7B_CAD24/B_A2V7B_CAD23/B_A3P8B_CAD22/B_A4V6B_CAD21/B_A5U6B_CAD20/B_A6V5
B_CAD19/B_A25R6
B_CAD18/B_A7U5
B_CAD17/B_A24W4
B_CAD16/B_A17M3
B_CAD14/B_A9M2
B_CAD12/B_A11L6 B_CAD9/B_A10K6
B_CC/BE2#/B_A12T1
B_CC/BE1#/B_A8M6
B_CPAR/B_A13N2
B_CFRAME#/B_A23R3 B_CTRDY#/B_A22R2
B_CIRDY#/B_A15P5
B_CSTOP#/B_A20P2B_CDEVSL#/B_A21P3
B_CBLOCK#/B_A19N3
B_CPERR#/B_A14N6
B_CCLK/B_A16P6
B_RSVD/B_D2P10
B_CAD31/B_D10V11 B_CAD30/B_D9R10
B_CAD29/B_D1U10
B_CAD28/B_D8V10
B_CAD27/B_D0W10
B_CAD8/B_D15K3
B_CAD7/B_D7K2
B_CAD6/B_D13J3
B_CAD5/B_D6J5
B_CAD4/B_D12J1
B_CAD3/B_D5J2
B_CAD2/B_D11H2
B_CAD1/B_D4H1 B_CAD0/B_D3H3
B_RSVD/B_D14J6
B_RSVD/B_A18M5
VCC
BR
1
B_CAD15/B_IOWR#M1B_CAD13/B_IORD#L5
B_CAD11/B_OE#L3
B_CAD10/B_CE2#L2
B_CC/BE3#/B_REG#U7
B_CC/BE0#/B_CE1#K5
B_CSERR#/B_WAIT#W9
B_CREQ#/B_INPACK#R7
B_CGNT/B_WE#N5
B_CSTSCHG/B_STSCHG#U9B_CCLKRUN/B_IOIS16#R9
B_CINT#/B_IREQ#V8
B_CRST#/B_RESETW5
B_CAUDIO/B_SPKR#V9
B_CCD1#/B_CD1#H5B_CCD2#/B_CD2#P9
B_CVS1/B_VS1#U8B_CVS2/B_VS2#P7
AD31
E12
AD30
C12
AD29
A11
AD28
B11
AD27
E11
AD26
F11
AD25
F12
AD24
B10
AD23
F10
AD22
B9AD
21C
9AD
20F9
AD19
E9AD
18A8
AD17
B8AD
16C
8AD
15B5
AD14
E6AD
13C
5AD
12A4
AD11
B12
AD10
D1
AD9
E3AD
8F5
AD7
E2AD
6F3
AD5
F2AD
4G
5AD
3F1
AD2
H6
AD1
G3
AD0
G2
C/B
E3#
B14
C/B
E2#
F8C
/BE1
#F6
C/B
E0#
G6
A_CAD26/A_A0 J14A_CAD25/A_A1 J17A_CAD24/A_A2 J18A_CAD23/A_A3 K15A_CAD22/A_A4 K18A_CAD21/A_A5 L14A_CAD20/A_A6 L17
A_CAD19/A_A25 L19
A_CAD18/A_A7 M19
A_CAD17/A_A24 M18
A_CAD16/A_A17 W16
A_CAD14/A_A9 U15
A_CAD12/A_A11 P14A_CAD9/A_A10 R13
A_CC/BE2#/A_A12 M17
A_CC/BE1#/A_A8 T19
A_CPAR/A_A13 P15
A_CFRAME#/A_A23 M15A_CTRDY#/A_A22 N17
A_CIRDY#/A_A15 N18
A_CSTOP#/A_A20 P17A_CDEVSL#/A_A21 N15
A_CBLOCK#/A_A19 N14
A_CPERR#/A_A14 R18
A_CCLK/A_A16 M14
A_RSVD/A_D2 F17
A_CAD31/A_D10 E19A_CAD30/A_D9 G15
A_CAD29/A_D1 F18
A_CAD28/A_D8 G14
A_CAD27/A_D0 G17
A_CAD7/A_D7 U13A_CAD5/A_D6 R12A_CAD3/A_D5 U12
A_CAD2/A_D11 R11
A_CAD1/A_D4 W12A_CAD0/A_D3 P11
A_RSVD/A_D14 V13
GN
DA6
GN
DA9
GN
DA1
4G
ND
E1G
ND
K1G
ND
P1G
ND
R19
GN
DW
6G
ND
F19
GN
DW
14
VCC
A7VC
CA1
2VC
CG
1VC
CG
19VC
CJ1
9VC
CN
1VC
CN
19VC
CW
8VC
CW
13
A_CAD4/A_D12 V12A_CAD6/A_D13 P12
A_RSVD/A_A18 R17
A_CAD8/A_D15 P13
SUSP
END
#C
15D
ATA
E17
CLO
CK
F15
LATC
HE1
8SP
KRO
UT
F14
2.5V
K19
VR_E
N#
L1N
CE5
RI_
OU
T#/P
ME
#E1
3G
RST
#C
11PR
ST#
C13
PCLK
C10
GN
T#B1
3R
EQ
#A1
3SE
RR
#C
6PE
RR
#E7
IDSE
LE1
0D
EVSE
L#F7
STO
P#B6
IRD
Y#B7
TRD
Y#C
7FR
AME#
E8PA
RA5
C898
0.01U_0402_16V7K
1
2
R940@0_0402_5%
12
C909
@0.1U_0402_10V6K1
2
C845
0.1U_0402_10V6K
1
2
C849
0.1U_0402_10V6K
1
2
C847
0.1U_0402_10V6K
1
2
C850
0.1U_0402_10V6K
1
2
C902
0.01U_0402_16V7K
1
2
C900
0.01U_0402_16V7K
1
2
C910@0.1U_0402_10V6K
1
2
JP24A1
CARDBUS HOUSING
R634
0_0402_5%
12
R1020@10K_0402_5%
C6350.1U_0402_10V6K
1 2
R1098100_0402_5%
1 2
C851
0.1U_0402_10V6K
1
2
C848
0.1U_0402_10V6K
1
2
C901
0.01U_0402_16V7K
1
2
C846
0.1U_0402_10V6K
1
2
R633
1620@0_0402_5%
12
C633
0.1U_0402_10V6K1
2R939
0_0402_5%
12
C634
0.1U_0402_10V6K1
2
S1_A[0..25]S2_D[0..15]
S1_D[0..15]
S2_A[0..25]
S1_D10
S1_D11
S1_CD2#
S1_D9
S1_WAIT#
S1_A23
S1_CE2#
S1_IORD#
S1_D14
S1_BVD2S1_REG#
S1_D15
S1_A24
S1_IOWR#S1_A17
S1_D12S1_D13
S1_A21
S1_A22
S1_RST
S1_A20
S1_INPACK#
S1_A25
S1_VS1
S1_BVD1
S1_VS2
S1_A19
S1_D8
S1_A18
S1_D3
S1_A1
S1_A12
S1_RDY#
S1_A15
S1_D4
S1_A6
S1_A2
S1_A10
S1_D6
S1_A0
S1_D2
S1_CE1#
S1_A16
S1_A8
S1_OE#
S1_A4
S1_D5
S1_D7
S1_A9
S1_WE#
S1_WP
S1_A11
S1_A7
S1_A13S1_A14
S1_A5
S1_D1S1_D0
S1_A3
S1_CD1#
S2_A0
S2_A16
S2_D13
S2_D11
S2_A4
S2_A2
S2_RST
S2_A23
S2_CE1#S2_D14
S2_A10
S2_RDY#
S2_A22
S2_D12
S2_A13
S2_D10S2_D1
S2_D8
S2_WE#
S2_A9
S2_WAIT#
S2_A7S2_A12 S2_A24
S2_VS2
S2_D5
S2_A6
S2_OE#
S2_A1
S2_A5
S2_D7
S2_A17
S2_A19
S2_D6
S2_CD1#
S2_BVD1
S2_IORD#
S2_D15
S2_A11
S2_INPACK#
S2_D9
S2_VS1
S2_IOWR#
S2_D4
S2_A8
S2_D2
S2_D3
S2_A3
S2_A25
S2_A21
S2_REG#
S2_A20S2_A14
S2_WP
S2_A15
S2_CD2#
S2_A18
S2_CE2#
S2_D0
S2_BVD2
S1_D[0..15]<31>
S2_D[0..15]<31,33>S1_A[0..25]<31>
S2_A[0..25]<31,33>
SLDATA<31>RTCCLK<31>
SLATCH<31>G_RST#<31,36,46>
S1_WAIT# <31>S1_RST <31>
S1_CE2# <31>
S1_CD1# <31>
S1_BVD2 <31>
S1_VS1 <31>
S1_INPACK# <31>S1_REG# <31>
S1_CD2# <31>
S1_BVD1 <31>
S1_IOWR# <31>
S1_VS2 <31>
S1_IORD# <31>
S1_WP<31>
S1_CE1#<31>
S1_OE#<31>
S1_WE#<31>S1_RDY#<31>
S2_VS2 <31,33>S2_RST <31,33>
S2_CE2# <31>
S2_WE#<31,33>
S2_WP<31>
S2_IORD# <31>
S2_CD2# <31,33>
S2_IOWR# <31>
S2_BVD1 <31,33>
S2_REG# <31,33>
S2_CD1# <31,33>
S2_CE1#<31,33>
S2_OE#<31,33> S2_VS1 <31,33>
S2_WAIT# <31,33>S2_INPACK# <31,33>
S2_BVD2 <31,33>
S2_RDY#<31,33>
+S1_VCC
+S2_VCC+S2_VPP
+S1_VPP
+5V
+12VALW
+S1_VPP+S2_VPP
+S2_VCC+S1_VPP+S1_VPP
+S1_VCC
+S2_VPP+S2_VPP+S2_VCC +S2_VCC
+S1_VCC
+S1_VCC
+5V
+3V
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
CARD BUS SOCKET
Compal Electronics, Inc.
32 66,星期四 07, 2003八月
SOCKETCARDBUSPCMCIA POWER CTRL.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
U38
TPS2224A
5V 15V 2
DATA3CLOCK4LATCH5
NC 6
12V 7
AVPP8
AVCC9AVCC10 GND 11
RESET#12
5V 24
NC 23NC 22
SHDN#21
12V 20
BVPP19
BVCC18 BVCC17
NC 16
OC#15 3.3V 143.3V 13
C646
4.7U_0805_10V4Z
1
2
C639 4.7U_0805_10V4Z1 2
C648
4.7U_0805_10V4Z
1
2
C644 4.7U_0805_10V4Z1 2
C650
0.1U_0402_10V6K
1
2C653
4.7U_0805_10V4Z
1
2
JP29
FOX_WZ21131-G2-P4
GND69GND71GND73GND75GND77GND79GND81GND83
GND 70GND 72GND 74GND 76GND 78GND 80GND 82GND 84
1122334455667788991010111112121313141415151616171718181919202021212222232324242525262627272828292930303131323233333434
35 3536 3637 3738 3839 3940 4041 4142 4243 4344 4445 4546 4647 4748 4849 4950 5051 5152 5253 5354 5455 5556 5657 5758 5859 5960 6061 6162 6263 6364 6465 6566 6667 6768 68
R1004
@0_0603_5%
12
C647
0.1U_0402_10V6K
1
2
C641 4.7U_0805_10V4Z1 2
C642 4.7U_0805_10V4Z1 2
C640 4.7U_0805_10V4Z1 2
C6541520@1000P_0402_50V7K
1
2
C652
1520@1000P_0402_50V7K
1 2
C6491000P_0402_50V7K
1
2
JP30
1520@FOX_WZ21131-G2-P4
GND69GND71GND73GND75GND77GND79GND81GND83
GND 70GND 72GND 74GND 76GND 78GND 80GND 82GND 84
1122334455667788991010111112121313141415151616171718181919202021212222232324242525262627272828292930303131323233333434
35 3536 3637 3738 3839 3940 4041 4142 4243 4344 4445 4546 4647 4748 4849 4950 5051 5152 5253 5354 5455 5556 5657 5758 5859 5960 6061 6162 6263 6364 6465 6566 6667 6768 68
C637 @2.2U_0805_10V4Z1 2
C643
4.7U_0805_10V4Z
1
2
C636
1000P_0402_50V8J
1 2
C638 4.7U_0805_10V4Z1 2
C645
4.7U_0805_10V4Z
1
2
C651
4.7U_0805_10V4Z
1
2
R6354.7K_0402_5%1 2
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
SM_CLE
SM_WE#
DQRYDRV
SD_CD#
MC_CD#
SQRY4
SD_CMD
SM_WE#
SM_CE#
SD_CLK/MS_CLK
SM_LVD
SM_D4
SM_D7
SM_R/B#
SD_DATA2
SM_WP#
S2_A25
SM_D3/MS_BS
MC_WP#
SM_RE#
SQRY3
SD_CD/DATA3
SD_DATA1SM_RE#
MC_WP#
SM_D6
SM_ALE
SM_D0/MS_RFU7
SM_ALE
MC_WP#
SM_D5
SM_D4
SM_D5
SM_D0/MS_RFU7
SM_WP#
SD_CD#
SD_DATA0
SM_D1/MS_RFU5
S2_A22
SM_R/B#
SD_DATA1
SM_D3/MS_BS
SM_D2/MS_SDIOSM_D6
SM_D1/MS_RFU5SM_D7
SM_LVD
SM_CLESM_CE#
SD_DATA0SD_CLK/MS_CLK
SD_WP
SM_CD#
SD_DATA2SD_CD/DATA3SD_CMD
SQRY6
SQRY2SQRY5
SQRY1
SQRY10SQRY9SQRY8SQRY7
SM_D2/MS_SDIO
MC_CD#S2_A22<31,32>
S2_A25<31,32>
S2_A15<31,32>
S2_A10<31,32>
S2_D15<31,32>
S2_D11<31,32>
S2_D6<31,32>S2_D12<31,32>
S2_A13<31,32>
S2_A14<31,32>
S2_D5<31,32>
S2_D13<31,32>
S2_WE#<31,32>S2_OE#<31,32>
S2_A16<31,32>S2_A19<31,32>
S2_A8<31,32>
S2_D14<31,32>S2_D7<31,32>
S2_A24<31,32>S2_A12<31,32>
S2_CE1#<31,32>
S2_A21<31,32>S2_RDY#<31,32>
S2_A20<31,32>
S2_REG#<31,32>S2_RST<31,32>S2_A18<31,32>
S2_BVD2<31,32>
S2_D9<31,32>S2_D10<31,32>
S2_D8<31,32>S2_BVD1<31,32>
S2_CD1#<31,32> S2_VS1 <31,32>
S2_CD2#<31,32>
S2_VS2<31,32>
S2_INPACK#<31,32>S2_WAIT#<31,32>
+3VS
+S2_VCC
+S2_VCC
+S2_VCC
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
4 IN 1 CARD READER SOCKET
33 66, 07, 20星期四 八月 03
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R6411620@10K_0402_5%
12
R639 1620@0_0402_5%1 2
RP146
1620@47K_0804_8P4R_5%
18
27
36
45
R989 1620@0_0402_5%1 2
RP144
1620@47K_0804_8P4R_5%
18
27
36
45
C655
1620@0.1U_0402_10V6K1
2
RP130 1620@0_0804_8P4R_5%
1 82 73 64 5
R637
@10K_0402_5%
12
R665
@0_0402_5%1 2
R638
1620@43K_0402_5%
12
D45
1620@BAT54C_SOT23~D
1
3
2
R648 1620@0_0402_5%1 2
R646
1620@43_0402_5%
12
RP143
1620@47K_0804_8P4R_5%
18
27
36
45
RP145
1620@47K_0804_8P4R_5%
18
27
36
45
JP31
1620@TAI_SOL 4 IN 1 MEMORY CONNECTOR
SSFDC_10P/SD_6P/SD_3P(GND)1SD_SW_CD12SD_SW_WP13SD_8P(DAT1)4SD_7P(DAT0)5SD_5P(CLK)6SD_2P(CMD)7SD_1P(DAT3)8SD_9P(DAT2)9SSFDC_12P & SD_4P(VCC)10SSFDC_11P(CD)11SSFDC_13P(D4)12SSFDC_9P(D3)13SSFDC_14P(D5)14SSFDC_8P(D2)15SSFDC_15P(D6)16SSFDC_7P(D1)17SSFDC_16P(D7)18SSFDC_6P(D0)19SSFDC_17P(LVD)20SSFDC_5P(WP_IN)21SSFDC_4P(WE)22SSFDC_19P(BSY)23SSFDC_3P(ALE)24SSFDC_20P(RE)25SSFDC_2P(CLE)26SSFDC_21P(CE)27SSFDC_WP2(SW_WP2)28SSFDC_CD2(SW_CD2)29SSFDC_22P/MS_3P/MS/9P(VCC)30MS_2P(BS)31MS_4P(SDIO)32MS_5P(RESERVED1)33MS_6P(INS)34MS_7P(RESERVED2)35MS_8P(SCLK)36MS_10P & MS_1P/SSFDC_1P &SSFDC_18P(GND)37
R6401620@0_0402_5%
1 2
RP128 1620@0_0804_8P4R_5%
1 82 73 64 5
C656
1620@0.1U_0402_10V6K
1
2
RP131 1620@0_0804_8P4R_5%
1 82 73 64 5
R988 1620@0_0402_5%1 2
RP132 1620@0_0804_8P4R_5%
1 82 73 64 5
RP133 1620@0_0804_8P4R_5%
1 82 73 64 5
R647
1620@10K_0402_5%12
RP134 1620@0_0804_8P4R_5%
1 82 73 64 5
R649 1620@0_0402_5%1 2
RP129 1620@0_0804_8P4R_5%
1 82 73 64 5
R658
1620@0_0402_5%1 2
R987 1620@0_0402_5%1 2
RP141 1620@0_0804_8P4R_5%
1 82 73 64 5
Q531620@MMBT3904_SOT23
2
31
D441620@BAT54C_SOT23~D1
3
2
R636
@10K_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RJ45_TXX+
LAN_RX-
PCI_AD24
PCI_AD20
EESK
RJ45_RXX-
XTALFBPCI_CBE#0
PCI_AD3
RJ45_TXX-
PCI_AD16
PCI_CBE#[0..3]
PCI_AD26
ACTIVITY#
RJ45_RXX-
PCI_AD27 LAN_RX-
PCI_AD6
CLKOUT
LANGND
PCI_AD29
PCI_CBE#3
ACTIVITY#
LAN_TX-
PCI_AD8
PCI_AD[0..31]
PCI_AD31
LAN_TX-PCI_AD30
PCI_AD19
EEDO
PCI_AD5
LAN_TX+
PCI_AD15
LINK10_100#
LAN_IO
LAN_TX+
RJ45_RXX+
PCI_AD23
PCI_CBE#2
EECS
RJ45_TXX+
PCI_CBE#1
PCI_AD10
PCI_AD25
PCI_AD1
EEDI
PCI_AD17
RJ45_GND
LAN_RX+
PCI_AD2
PCI_AD18
PCI_AD7
PCI_AD19
RJ45_TXX-
PCI_AD13PCI_AD14
LAN_RX+
LINK10_100#
PCI_AD9
PCI_AD0
PCI_AD21
PCI_AD12
PCI_AD28
PCI_AD11
PCI_AD4
RJ45_RXX+
PCI_AD22
ISOB
CLKOUT XTALFB
RJ45_GND
PCI_CBE#[0..3]<26,31,35,36,43>
PCI_CLKRUN#<26,31,35,36,43>
PCI_DEVSEL#<26,31,35,36,43>
PCI_FRAME#<26,31,35,36,43>
RJ45_RXX-<41>
PCI_AD[0..31]<26,29,31,35,36,43>
PCI_RST#<11,26,30,31,35,36,43,46>
PCI_PAR<26,31,35,36,43>
RJ45_TXX-<41>
RJ45_RXX+<41>
PCI_PERR#<26,31,35,36,43>
PCI_REQ#1<26>
PCI_STOP#<26,31,35,36,43>
PCI_TRDY#<26,31,35,36,43>PCI_IRDY#<26,31,35,36,43>
RJ45_TXX+<41>
ONBD_LAN_PME#<31,36,43,46,47>
PCI_GNT#1<26>
PCI_SERR#<26,31,35,36,43>
PCI_PIRQD#<26,36>
CLK_PCI_LAN<26>
RJ45_GND<41>
LANIO
LANIO
LANVDD
LANVDD
LANVDD
LANIO
LANIO
+3VS
LANIO
LANIO+3VALW
LANIO
LANIO
LANVDD
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
LAN RealTech8101BL
34 66, 07, 2003星期四 八月
Compal Electronics, Inc.
1. LAN_RD+, LAN_RD- should be equal length as possible2. LAN_TD+, LAN_TD- should be equal length as possible
CHASSIS GND
4. The distance between RJ45(Conn.) and Magnetic(U24) should be as short as possible
Layout Recommend :
T=10mil
Termination plane should be copledto chassis ground and also dependson safety concern
1:1
3. The Maximum trace length between LAN chip(U22) and Magnetic(U24) is 12cm(4.7")
T=10mil
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Please close to LAN IC
Close to U39 pin58
C658
0.1U_0402_10V6K
1
2
C6750.1U_0402_10V6K
1
2
C6790.1U_0402_10V6K
1
2
L43
KC FBM_L11-201209-601LMT 08051 2
C674
0.1U_0402_10V6K1
2
C6781000P_1206_2KV7K
1
2
C665
1U_0603_10V6K
1
2
C661
0.1U_0402_10V6K
1
2
Y5
25MHZ_20P_1BX25000CK1A
1 2
PCI I/F
Power
Power
LAN I/F
AC-Link
U39
RTL8101L_LQFP100
AD047AD146AD245AD343AD442
GND 31
AD541AD640AD739AD836AD935AD1034AD1133AD1232AD1330AD1429AD1528AD1615AD1714AD1813AD1912AD2011AD2110AD229AD238AD2496AD2593AD2692AD2791AD2889AD2987AD3086AD3185
C/BE#384
IDSEL98
GND 2
C/BE#217
FRAME#18IRDYB#19TRDY#20
GND 16
DEVSEL#21STOP#23
PERR#25SERR#26
PAR24
C/BE#127 C/BE#038
GND 73GND 66GND 62
CLKRUN#50
EECS 55EESK 54EEDI 53EEDO 52
GND 44
ISOLATE# 74
RTSET 65
LWAKE 64
RTT3 63
PME#57
GND 88
LED0 78LED1 77LED2 76
X1 61
X2 60
INTA#80
RST#81PCICLK97
GNT#82 REQ#83
TXD+ 72TXD- 71
RXIN+ 68RXIN- 67
VDD6VDD22VDD37VDD49VDD90VDD95
VDD25 48VDD25 94
AC_RST# 1AC_SYNC 3AC_DOUT 4
AC_DIN 5AC_BCK 7
NC 69
GPIO1 99GPIO0 100
VCTRL 56
AVDD25 58
AVDD 59
AVDD 70
AVDD 75
ROMCS# 51
INTB# 79
C667
10U_0805_10V4Z
1
2
R698 5.6K_0402_5%1 2
C663
0.1U_0402_10V6K
1
2
R701 15K_0402_5%1 2
C673
0.1U_0402_10V6K1
2
JP32
AMP RJ45 with LED
PR1-2
PR1+1
PR2+3
PR3+4
PR3-5
PR2-6
PR4+7
PR4-8
Green LED+9
Green LED-10
Amber LED+11
Amber LED-12
SHLD1 13
SHLD2 14
SHLD4 16
SHLD3 15
C660
0.1U_0402_10V6K
1
2
C6700.1U_0402_10V6K
1
2
R70049.9_0402_1%
12
C657
0.1U_0402_10V6K
1
2
R70749.9_0402_1%
12
C659
0.1U_0402_10V6K
1
2
U41
NS0013_16P
RD+1 RD-2 CT3
CT6 TD+7 TD-8 TX- 9TX+ 10CT 11
CT 14RX- 15RX+ 16
R704 5.6K_0603_1%12
R702 1K_0402_5%12
R70675_0402_1%
12
R1006
0_0805_5%
1 2
R70575_0402_1%
12
C669
1000P_1206_2KV7K
1 2
C676
0.1U_0402_10V6K
1
2
C672
0.1U_0402_10V6K1
2
R69675_0402_1%
12
R695 300_0603_5%1 2
R703 100_0402_5%1 2
R69775_0402_1%
12
R694 300_0603_5%1 2
R69949.9_0402_1%
12
C662
0.1U_0402_10V6K
1
2
C6770.1U_0402_10V6K
1 2
C682@10P_0402_50V8K
1
2
C666
1U_0603_10V6K
1
2
R709@22_0402_5%
12
U40
AT93C46-10SI-2.7_SO8CS1 SK2 DI3 DO4
VCC 8NC 7NC 6GND 5
C680
27P_0402_50V8J
1
2
C664
0.1U_0402_10V6K1
2
C681
27P_0402_50V8J1
2
R70849.9_0402_1%
12
C6714.7U_0805_10V4Z
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCI_AD16
CLK_PCI_1394
SCL_1394
XTPB0+XTPA0-
CLK_PCI_1394
SDA_1394
XTPA0+
XTPB0-
XTPBIAS0
PCI_AD[0..31]
PCI_AD30
PCI_AD24
PCI_AD2
PCI_AD7
PCI_AD14
PCI_AD25
PCI_AD11
PCI_AD26
PCI_AD9
PCI_AD29
PCI_AD3
PCI_AD21
PCI_AD10
PCI_AD18
PCI_AD20
PCI_AD16PCI_AD15
PCI_AD13
PCI_AD5PCI_AD4
PCI_AD22
PCI_AD31
PCI_AD1PCI_AD0
PCI_AD23
PCI_AD6
PCI_AD27
PCI_AD17
PCI_AD19
PCI_AD12
PCI_AD8
PCI_AD28
SDA_1394SCL_1394
PCI_IRDY#<26,31,34,36,43>
PCI_PIRQA#<10,17,26,31,36>
PCI_FRAME#<26,31,34,36,43>
PCI_TRDY#<26,31,34,36,43>PCI_DEVSEL#<26,31,34,36,43>
CLK_PCI_1394<26>
PCI_STOP#<26,31,34,36,43>
PCI_GNT#0<26>
PCI_SERR#<26,31,34,36,43>
PCI_PERR#<26,31,34,36,43>
PCI_CLKRUN#<26,31,34,36,43>PCI_PAR<26,31,34,36,43>
PCI_CBE#0<26,31,34,36,43>PCI_CBE#1<26,31,34,36,43>PCI_CBE#2<26,31,34,36,43>PCI_CBE#3<26,31,34,36,43>
PCI_RST#<11,26,30,31,34,36,43,46>
PCI_REQ#0<26>
PCI_AD[0..31]<26,29,31,34,36,43>
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
IEEE 1394 CONTROLLER
35 66,星期四 07, 2003八月
Compal Electronics, Inc.
Near 1394 IC
ID: AD16
CLOSE CHIP
The connector depend ondefferent project
EEPROM cancel,need SystemSupport
Close Chip
30ppm
Connect ToShielding GND
G_RST# connect to PCIRST#
** GPIO2 and GPIO3 defaults as an inputand if it is not implemented, it isrecommended that it be pulled low toground with a 220 ohm resistor.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
RP135
4.7K_1206_8P4R_5%
1 82 73 64 5
C687
0.1U_0402_10V6K
1
2
C690
0.1U_0402_10V6K
1
2
C686
0.1U_0402_10V6K
1
2
C683
0.1U_0402_10V6K
1
2
JP33
AMP_440168-21234
5678
R711 10K_0402_5%12 C689
0.1U_0402_10V6K
1
2
R72256.2_0402_1%
12
R72356.2_0402_1%
12
C697
0.01U_0402_16V7K
1
2
C705
0.1U_0402_10V6K
1
2
R717 100_0402_5%1 2
C688
0.1U_0402_10V6K
1
2
C698 22P_0402_25V8K
1 2
X324.576MHz_16P_3XG-24576-43E1
12
C703
@10P_0402_25V8K
1
2
C692
1000P_0402_50V7K
1
2
C7000.1U_0402_10V6K
1 2
C684
0.1U_0402_10V6K
1
2
R720
56.2_0402_1%
12
C685
0.1U_0402_10V6K
1
2
C699 22P_0402_25V8K
1 2
R715 1K_0402_5%1 2
C702
220P_0402_50V7K
1
2
R7166.34K_0603_1%
1 2
C704
0.1U_0402_10V6K
1
2
L44BLM21A601SPT_0805
1 2
RP142
220_0804_8P4R_5%
1 82 73 64 5
C693
1000P_0402_50V7K
1
2
C696
4.7U_0805_10V4Z
1
2
C695
1000P_0402_50V7K
1
2
C694
1000P_0402_50V7K
1
2
C691
1000P_0402_50V7K
1
2
C701
1U_0603_10V6K
1
2
PHY PORT 1
POWER CLASS
EEPROM 2 WIRE BUS
FILTER
OSCILLATOR
BIAS CURRENT
PCI BUS INTERFACE
TSB43AB21/(TSB43AB22)
U42
TSB43AB21_PQFP128
CY
CLE
OU
T/C
AR
DB
US
86C
NA
96TE
ST1
710
TES
T16
11
CY
CLE
IN87
VD
DP
20V
DD
P35
VD
DP
48V
DD
P62
VD
DP
78
PCI_AD2531 PCI_AD2432 PCI_AD2337 PCI_AD2238 PCI_AD2140 PCI_AD2041 PCI_AD1942 PCI_AD1843 PCI_AD1745 PCI_AD1646 PCI_AD1561 PCI_AD1463 PCI_AD1365 PCI_AD1266 PCI_AD1167 PCI_AD1069 PCI_AD970 PCI_AD871 PCI_AD774 PCI_AD676 PCI_AD577 PCI_AD479 PCI_AD380 PCI_AD281 PCI_AD182 PCI_AD084
PCI_C/BE334PCI_C/BE247PCI_C/BE160PCI_C/BE073PCI_CLK16PCI_GNT18PCI_REQ19PCI_IDSEL36PCI_FRAME49PCI_IRDY50PCI_TRDY52PCI_DEVSEL53PCI_STOP54PCI_PERR56PCI_INTA/CINT13PCI_PME/CSTSCHG21PCI_SERR57PCI_PAR58PCI_CLKRUN12PCI_RST85
G_RST14
GPIO389GPIO290
PLL
GN
D1
8R
EG
_EN
9A
GN
D10
9A
GN
D11
0A
GN
D11
1A
GN
D11
7A
GN
D12
6A
GN
D12
7A
GN
D12
8D
GN
D17
DG
ND
23R
EG
1830
DG
ND
33D
GN
D44
DG
ND
55D
GN
D64
DG
ND
68D
GN
D75
DG
ND
83R
EG
1893
DG
ND
103
DVDD 15DVDD 27DVDD 39DVDD 51DVDD 59DVDD 72DVDD 88DVDD 100
PLLVDD 7AVDD 1AVDD 2AVDD 107AVDD 108AVDD 120
CPS 106
NC/(TPBIAS1) 125NC/(TPA1+) 124NC/(TPA1-) 123NC/(TPB1+) 122NC/(TPB1-) 121
R0 118
R1 119
X0 6
X1 5
FILTER0 3
FILTER1 4
SDA 92
SCL 91
PC0 99PC1 98PC2 97
TPBIAS0 116TPA0+ 115TPA0- 114
TPB0 + 113TPB0 - 112
TEST9 94TEST8 95
TEST3 101TEST2 102TEST1 104TEST0 105
PCI_AD3122 PCI_AD3024 PCI_AD2925 PCI_AD2826 PCI_AD2728 PCI_AD2629
R726
@10_0402_5%
12
R721
56.2_0402_1%
12
R727
5.11K_0402_1%
12
1
1
2
2
3
3
4
4
5
5
1 1
2 2
3 3
4 4PCI_GNT#PCI_REQ#4PCI_REQ#3
PCI_GNT#4PCI_GNT#3
USB20_NEC_P3-USB20_NEC_P3+USB20_NEC_P4-USB20_NEC_P4+
PCI_CLKRUN#
CLK_PCI_USB20
USB20_NEC_P1-USB20_NEC_P1+
USB20_NEC_P0-USB20_NEC_P0+
USB20_NEC_P2-USB20_NEC_P2+
PCI_AD23
USB20_NEC_P1-_R
USB20_NEC_P4+_R
PCI_AD4
PCI_AD17
PCI_AD20
PCI_PIRQA#
USB20_NEC_P0-_R
PCI_AD7
PCI_IRDY#
PCI_AD19
PCI_GNT#
USB20_NEC_P3+
USB20_NEC_P1-
PCI_AD15
PCI_STOP#
PCI_AD26
PCI_CBE#[0..3]
PCI_PAR
PCI_SERR#
PCI_PIRQC#
OVCUR_USB20#0
PCI_AD0
PCI_AD3
PCI_AD6
PCI_CBE#2
PCI_AD30
OVCUR_USB20#3
PCI_AD1
PCI_AD24
PCI_AD28
PCI_AD13
PCI_AD21
PCI_PIRQD#
PCI_REQ#
PCI_FRAME#
PCI_AD22
PCI_AD[0..31]
USB20_NEC_P2+_R
PCI_AD9
PCI_CBE#3
PCI_AD27
OVCUR_USB20#1
PCI_AD5
PCI_AD8
PCI_AD16
OVCUR_USB20#4
PCI_AD2
PCI_PERR#
PCI_AD25
PCI_AD31
USB20_NEC_P3+_R
USB20_NEC_P3-_R
PCI_AD12
PCI_AD14
PCI_AD23
USB20_NEC_P4-_R
PCI_CBE#0
PCI_AD10
PCI_CBE#1
PCI_DEVSEL#PCI_REQ#
USB20_NEC_P2-_R
USB20_NEC_P0+_R
PCI_TRDY#
PCI_AD18 USB20_NEC_P1+_R
CLK_PCI_USB20
PCI_AD11
PCI_AD29
USB20_NEC_P1+
USB20_NEC_P4-USB20_NEC_P4+
USB20_NEC_P2-
USB20_NEC_P0+
USB20_NEC_P2+
USB20_NEC_P3-
USB20_NEC_P0-
PCI_REQ#3<26,43>PCI_REQ#4<26,43>PCI_GNT#3<26,43>PCI_GNT#4<26,43>
PCI_PIRQA#<10,17,26,31,35>PCI_PIRQC#<26,43>PCI_PIRQD#<26,34>
USB20_NEC_P1- <44>
USB20_NEC_P2- <44>
USB20_NEC_P3- <44>
USB20_NEC_P4- <41>
PCI_AD[0..31]<26,29,31,34,35,43>
PCI_CLKRUN#<26,31,34,35,43>
USB20_PME#<31,34,43,46,47>
PCI_CBE#[0..3]<26,31,34,35,43>
PCI_FRAME#<26,31,34,35,43>
PCI_DEVSEL#<26,31,34,35,43>
PCI_IRDY#<26,31,34,35,43>PCI_TRDY#<26,31,34,35,43>
PCI_PAR<26,31,34,35,43>
PCI_STOP#<26,31,34,35,43>
CLK_PCI_USB20<26>
PCI_SERR#<26,31,34,35,43>OVCUR_USB20#1 <44>
USB20_NEC_P0- <44>
PCI_RST#<11,26,30,31,34,35,43,46>
G_RST#<31,32,46>
USB_SMI#<27>
USB20_NEC_P1+ <44>
USB20_NEC_P3+ <44>
USB20_NEC_P0+ <44>
PCI_PERR#<26,31,34,35,43>
USB20_NEC_P2+ <44>
OVCUR_USB20#0 <44>
USB20_NEC_P4+ <41>
+3V +3V_USB20
+3V +3V_USB20
+3V
+3V
+3V
+3V_USB20
+3V
+3VS+3V
Title
Size Document Number Rev
Date: Sheet o fLA-1811 0.7
NEC uPD720101 - USB2.0 Controller
36 66, 08, 2003星期五 八月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
L Note: PLACE CLOSE TO U54 .For NEC USB2.0 only .
LNote: PLACE CLOSE TO U54 .For NEC USB2.0 only .
PIR BOM 92.07.30
C965NEC@16P_0603_50V8J
1
2
R1037 NEC@15K_0402_5%1 2
R1031 NEC@42.2_0603_1%1 2
R1042 NEC@1.5K_0402_5%1 2
R1033 NEC@42.2_0603_1%1 2
C929
NEC@10U_0805_10V4Z
1
2
R1030 NEC@42.2_0603_1%1 2
C923
NEC@0.1U_0402_10V6K
1
2
R1026 NEC@36_0603_1%1 2
R1105NEC@100_0402_5%
12
R1039 NEC@10K_0402_5%1 2
C919
NEC@0.1U_0402_10V6K
1
2
Y7NEC@30MHZ_30PPM
1 2
R1035 NEC@42.2_0603_1%1 2
R1060 NEC@0_0402_5%1 2
R1112 NEC@100_0402_5%1 2
RP148
NEC@15K_1206_8P4R_5%
1 82 73 64 5
U55
@AT24C02N-10SC-2.7_SO8
A0 1A1 2
SDA5 SCL6
VCC8
A2 3GND 4
WC7
C964NEC@16P_0603_50V8J
1
2
R1025 NEC@36_0603_1%1 2
RP147
NEC@15K_1206_8P4R_5%
1 82 73 64 5
C920
NEC@0.1U_0402_10V6K
1
2
R1061 @0_0402_5%1 2
R1127NEC@1.5K_0402_5%
12
R1048 @0_0402_5%1 2R1046 @1.5K_0402_5%
1 2
C928
NEC@10U_0805_10V4Z
1
2
R1029 NEC@42.2_0603_1%1 2
R1052 @0_0402_5%1 2
C927
NEC@0.1U_0402_10V6K
1
2
USB 2.0 CONTROLLERuPD720101F1-EA8FBGA144
U54
NEC@UPD720101F1-EA8_FBGA144
VDD
P2
NTEST1 M8VD
DD
7
TEST L8
XT1/SCLK L9XT2 P8
LEGCL7
VDD
P3
VSS
B1
VCCRST#C9
SMI#L6
N.C.P6N.CM6
PME#D9
PCLKA8VBBRST#B8
VDD
P12
VSS
N1
VDD
_PC
IH
3
INTA#C7INTB#B7INTC#A7
GNT0#D6 REQ0#C6
AD31A6AD30B6
VSS
P10
AD29C5AD28A5AD27C4AD26B5AD25A4AD24B4
CBE3#C3
IDSELB3
VDD
A13
VSS
N14
VSS
D8
AD23C1
SMC M7
AD22C2AD21D2AD20D1AD19D3
VDD
A12
AD18E1AD17E3AD16F2
CBE2#F1
FRAME#F3IRDY#F4TRDY#G1
DEVSEL#G2
VDD
_PC
IM
4STOP#G3
PERR#H2SERR#H1
PARJ4
CBE1#J3
VSS
H14
AD15J1AD14J2AD13K3
VDD
A3
AD12K1AD11L3AD10K2AD9L1AD8L2
CBE0#M2
AD7M1AD6N3
VSS
B14
VSS
D12
VDD
E2
AD5M3AD4N4AD3P4AD2N5AD1P5AD0M5
CRUN#N6
VDD
_PC
IC
8
SRDTA N9SRCLK M9
SRMOD P9
OCI1 B12
PPON1 C12
OCI5 B9
OCI2 B11
OCI4 A10
AMC P7
OCI3 B10
VDD
N8
VSS
A2
PPON2 A11PPON3 C11PPON4 C10
TEB N7
PPON5 A9
NANDTEST M10
VSS
B2
RSDM5 E13DM5 D14
VDD
G12
DP5 C13RSDP5 C14
VSS
N13
VDD
L13
VSS
B13
VSS
M11
RSDM1 M14DM1 M13
VDD
J13
DP1 L14RSDP1 K13
VSS
L12
RSDM2 K14DM2 K12
VDD
H13
DP2 J14RSDP2 J12
VSS
H12
VDD
F13
VSS
N2
AVD
DN
10AV
SSP1
3AV
DD
N12
AVSS(R) N11RREF P11
AVSS
M12
VSS
G4
RSDM3 H11DM3 G11DP3 G13
RSDP3 G14
VSS
J11
RSDM4 F12DM4 F14
VDD
D13
DP4 E12RSDP4 E14
VSS
F11
VDD
H4
R1032 NEC@42.2_0603_1%1 2
R1036 NEC@15K_0402_5%1 2
C925
NEC@10U_0805_10V4Z
1
2
R1028
@10_0402_5%
12
R1034 NEC@42.2_0603_1%1 2
R1051 NEC@0_0402_5%1 2C926
NEC@0.1U_0402_10V6K
1
2
C915
@15P_0402_50V8J
R1038
NEC@9.1K_0402_1%
12
R1040 NEC@10K_0402_5%1 2
C922
NEC@0.1U_0402_10V6K
1
2
R1050 @0_0402_5%1 2
R1049
NEC@0_0603_5%1 2
C924
NEC@10U_0805_10V4Z
1
2
R1024 @0_0402_5%1 2
R1045 NEC@1.5K_0402_5%1 2
R1043 NEC@1.5K_0402_5%1 2
R1054NEC@0_0603_5%
1 2
C918
@0.1U_0402_10V6K
1
2
C916
@0.1U_0402_10V6K
1
2
R1041 NEC@1.5K_0402_5%1 2
C917
@0.1U_0402_10V6K
1
2
R1027 NEC@42.2_0603_1%1 2
R1047 NEC@0_0402_5%1 2
C921
NEC@0.1U_0402_10V6K
1
2R1053 NEC@0_0402_5%1 2
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
AFILT3AFILT2
LINE_OUTR
LINE_OUTL
CLK_14M_CODECCDGNDA
MDMIC
AFILT1
CDROM_R_R
CD_GNA
AFILT4
CDROM_R_L
CDROM_RC_R
CDROM_RC_L
MONO_IN
MONO_INR
MONO_INRMONO_IN1
MD_SPKR MD_SPKRC
+5VAMP_CODEC
AUD_REF
PCM_SPK#<31>
SPDIFO<41>
AC97_SYNC<27,29,44>
MUTE_LED<38,44>
AC97_SDIN0 <27>
AC97_BITCLK <27,44>
AC97_RST#<27,44>
CLK_14M_CODEC <24>
SB_SPKR<27>
L_HP <38>
R_HP <38>CDROM_L<30>
MIC1<38>
CDROM_R<30>
AC97_SDOUT<27,29,44>
MD_SPK<44>
CD_AGND<30>
LINE_OUTR <38>
LINE_OUTL <38>
MD_MIC <44>
BEEP#<46>
MIC2<38>
HPS<38>
GNDA <38,41>
CONA#<41,46>
SPDIF_OUT<27,29>
+3VALW
+3VALW
CODEC_REF
+3VALW
VDDA_CODEC
+5VS
VDDA_CODEC+5VAMP_CODEC
+3VALW
+3VALW
+3VS
+3VS
+5VAMP_CODEC
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
AC97 CODEC
Custom37 66, 02, 2003星期二 九月
Compal Electronics, Inc.
External
X
External
X
14.318MHZ
X
R767 R766 FREQ. SEL
Stuff
48MHZ
Crystal
Stuff
GND
24.576MHZ
GNDA
W=40Mil
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Stuff
PIR LAYOUT 92.07.30
PIR BOM & LAYOUT 92.07.30
C743 @15P_0402_50V8J
C726
10U_0805_6.3V6M
1
2
R765@0_1206_5%
1 2
R1165@0_1206_5%
1 2
C731 1U_0603_25V4Z1 2
C735 2.2U_0603_6.3V4Z1 2
R1166@0_1206_5%
1 2
C730
10U_0805_10V4Z
1
2
R733
10K_0402_1%
12
G
DSQ101 2N7002_SOT23
2
13
C749
@0.1U_0402_16V4Z
1
2
R7540_0402_5%
12
C722
1U_0603_10V6K
12
R752 4.7K_0402_5%1 2
C904 1U_0603_10V6K1 2
R11670_1206_5%
1 2
R748 4.7K_0402_5%12
C717
4.7U_0805_10V4Z
1
2
C724
0.1U_0402_10V6K
1
2
U46
SI9182DH-AD_MSOP8
VIN4
SD8
VOUT 5
GND 3
SENSE or ADJ 6
ERROR7 CNOISE 1
DELAY2
C712
1U_0603_10V6K
12
R739
560_0402_5%
1 2
R755 2.7K_0402_5%1 2
D46
RB751V_SOD323
21
R757 2.7K_0402_5%12
C750
270P_0402_50V7K
1 2
JOPEN6
12
C719
1U_0603_25V4Z
1 2R1063
39K_0603_1%1 2
R750 33_0402_5%12
R956
10K_0402_5%
12
R740
0_0805_5%1 2
R11680_1206_5%
1 2
R749 4.7K_0402_5%1 2
C905
@0.1U_0402_16V4Z
1
2
C725
0.1U_0402_10V6K
1
2
R769
0_0402_5%
12
R766 4.7K_0402_5%1 2
C752 270P_0402_50V7K1 2
C714 1U_0603_10V6K12
R73710K_0603_1%
12C
BE
Q56
2SC2411K_SOT23
1
2
3
C747
0.1U_0402_16V4Z1
2
C728
0.1U_0402_10V6K
1
2
R751 4.7K_0402_5%12
U45C
SN74LVC14APWLE_TSSOP14
O 6I5
P14
G7
C734 2.2U_0603_6.3V4Z1 2
R1103
@0_0402_5%
12
U45A
SN74LVC14APWLE_TSSOP14
O 2I1
P14
G7
C751 270P_0402_50V7K1 2
C737 1U_0603_10V6K1 2
U18B
SN74LVC32APWLE_TSSOP14
A4
B5 O 6P
14G
7
R762 @4.7K_0402_5%1 2R761 @0_0402_5%12
C729
0.1U_0402_10V6K
1
2
C718
0.1U_0402_10V6K
1
2
R742@10K_0402
12
R736
30K_0603_1%
1 2
JOPEN7
12C744
270P_0402_50V7K
1 2C746
0.1U_0402_10V6K
1
2
R732
560_0402_5%
1 2R731
10K_0402_1%
1 2
R767 4.7K_0402_5%1 2
R763 33_0402_5%1 2
R7462.2K_0402_5%12
C723
0.1U_0402_10V6K
1
2
R770
@4.7K_0402_5% 12
U32F
SN74LVC14APWLE_TSSOP14
O 12I13
P14
G7
R729
@100K_0402_1%
12
R741
560_0402_5%
1 2
JOPEN8
12
L98
CHB1608B121_0603
1 2
C713
0.22U_0603_10V7K
1
2
C721
1U_0603_10V6K
12
C736 2.2U_0603_6.3V4Z1 2
R758
@10_0402_5%
12
C7270.1U_0402_10V6K
1
2
R753 33_0402_5%12
L99
CHB1608B121_06031 2
C745
1U_0603_10V6K
1
2
C715
4.7U_0805_10V4Z
1
2R738
10K_0402_5%
1 2
R764 33_0402_5%1 2
U47
AD1981B_LQFP48
AUX_L14
AUX_R15
JS017
JS116
LINE_IN_L23
LINE_IN_R24
CD_L18
CD_R20
CD_GND19
MIC121
MIC222
PHONE13
NC 12
LINE_OUT_L 35
LINE_OUT_R 36
MONO_OUT 37
RESET#11
SYNC10
BIT_CLK 6
SDATA_OUT5
SDATA_IN 8
XTL_IN 2
XTL_OUT 3
AFILT1 29AFILT2 30
VREFOUT 28
VREF 27
DVD
D1
1
DVD
D2
9
AVD
D1
25
AVD
D2
38
AFILT4 32
ID146
EAPD47
SPDIFO48
DVSS14DVSS27
HP_LOUT_L 39
HP_LOUT_R 41
AFILT3 31
AVSS4 33
AVD
D4
34
AVD
D3
43
AVSS3 44
ID045
AVSS2 40AVSS1 26
NC 42
C742 0_0402_5%1 2
C720
0.01U_0402_16V7K
1
2
C979
@0.1U_0402_10V6K
1
2
C716
0.1U_0402_10V6K
1
2
R771
4.7K_0402_5%12
R735
10K_0402_1%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SPKR+
SPKL+
SPKR-
SPKL-
INTSPK_CL+
LINE_C_OUTR
LINE_C_OUTL
INTSPK_CR+INTSPK_CL+
INTSPK_CR+
SPKL+
SPKR-
SPKL-SPKR+
LINE_OUTL<37>
LINE_OUTR<37>
EC_MUTE#<46>
L_HP<37>
R_HP<37>
MIC2<37>
DOCK_LOUT_R<41>DOCK_LOUT_L<41>
VOLBTN+# <41,44,46>VOLBTN-# <41,44,46>WIRELESS_BTN <42,46>
WIRELESS_LED# <42,43,44>MUTE_LED <37,44>
HPS <37>
MIC1<37>
+5VAMP
+5VAMP+5VAMPP
+3VS
+5VS +5VAMP
CODEC_REF+5VS
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
AMP & Audio Jack
38 66, 02, 2003星期二 九月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AUDIO CONNECTOR
HEADPHONE OUT/LINE OUT
Av(inv)
1
GAIN1
1
Gain Settings
1 0
GAIN0
0
0 6 dB0
1
21.6 dB
15.6 dB
10 dB
10 dB
R973
100K_0402_5%
12
C762
47P_0402_50V8J
1
2
L103 BLM11A121SPT_08051 2
D78RB751V_SOD323
21
U52
TI6017A2_TSSOP20
GN
D4
1G
ND
311
GN
D2
13G
ND
120
VDD
16PV
DD
115
RIN-17
BYPASS 10
NC 12
LOUT- 8
LOUT+ 4
ROUT- 14
ROUT+ 18
RIN+7
LIN-5
LIN+9
GAIN0 2
GAIN1 3
PVD
D2
6
SHUTDOWN19
C894 0.1U_0402_16V7K1 2
R975 0_0402_5%1 2
C763
47P_0402_50V8J
1
2
C761
47P_0402_50V8J
1
2
+C774 100U_D2_10VM1 2
R1164
1K_0402_5%
12
L57
0_12061 2
C896 0.1U_0402_16V7K1 2
C893
0.047U_0603_10V7K
1 2
R971
@100K_0402_5%
12
R972
100K_0402_5%
12
C8970.47U_0603_10V7K1
2
C892
0.1U_0402_10V6K
1
2
JP34
ACES_85205-0400
11223344
L100 BLM11A121SPT_08051 2
C764
47P_0402_50V8J
1
2
R974
@100K_0402_5%
12
R1158
1K_0402_5%
12
C895
0.047U_0603_10V7K
1 2
L101 BLM11A121SPT_08051 2
+C773 100U_D2_10VM1 2
R734
0_1206_5%
1 2
C891
0.1U_0402_10V6K
1
2L102 BLM11A121SPT_08051 2
C890
10U_0805_10V3M
1
2
JP41
ACES_88028-1600_16P
1 23 45 67 89 1011 1213 1415 16
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CLK_PCI_SIO CLK_LPC_48M
SOUT2
RTS1# DTR1# SOUT1
RI1#
CTS2#DSR2#
SOUT2SIN2
DCD1#
SOUT1
SIN1
DTR1#
RTS1#
DSR1#
CTS1#
LPD0LPD1LPD2LPD3LPD4LPD5LPD6LPD7
LPTSTB#
LPTINIT#LPTAFD#
LPTBUSYLPTACK#
LPTSLCTIN#LPTERR#
LPTPE
LAD0LAD1LAD2LAD3 TRACK0#
RDATA#WP#
DSKCHG#
CLK_LPC_48M
INDEX#CLK_PCI_SIOSERIRQ
LFRAME#
HWMVCC
HWMVCC
CTS1#
RI1#
DCD2#
RI2#
SIN2
SIN1
DCD2#RI2#
CTS2#DSR2#
DSR1#DCD1#
LPTSLCT
FIR_DET#
IRTXOUT <45>IRRX <45>
IRMODE <45>
LPD0 <40>LPD1 <40>LPD2 <40>LPD3 <40>LPD4 <40>LPD5 <40>LPD6 <40>LPD7 <40>
LPTAFD# <40>LPTINIT# <40>
LPTSTB# <40>
LPTPE <40>
LPTERR# <40>
LPTBUSY <40>
LPTSLCTIN# <40>
LPTACK# <40>
LPC_AD0<26,46>LPC_AD1<26,46>LPC_AD2<26,46>LPC_AD3<26,46>
CLK_LPC_48M <24>
CLK_PCI_SIO<26>SIRQ<26,31,46>
NB_RST#<8,17,26>
LPC_FRAME#<26,46>
HDSEL# <40>
TRACK0# <40>
3MODE# <40>
INDEX# <40>
DRV0# <40>
RDATA# <40>WP# <40>
FDDIR# <40>STEP# <40>
WGATE# <40>
DSKCHG# <40>
WDATA# <40>
MTR0# <40>
MDC_DET#<44>
LPC_DRQ#1<26>
LPTSLCT <40>
RI1# <41>
DCD1# <41>
SOUT1 <41>
SIN1 <41>
DTR1# <41>
RTS1# <41>
DSR1# <41>
CTS1# <41>
+3VS+3VS+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
Title
Size Document Number R ev
Date: Sheet o f
LA-1811 0.7
LPC SUPER I/O VIA VT1211
39 66, 星期四 八 07, 2003月
Compal Electronics, Inc.
Base address 1:2Eh/2FhBase address 0:4Eh/4Fh 1:Test Mode
0:Normal Opreation1:Enable Flash Rom0: Enable ROM I/F as GPIO
Super I/O strapping for VT1211For Winbond 48M strapping
W
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PIR BOM & LAYOUT 92.07.30
C788
@15PF_0402
12
R794
@10K_0402
12
R11084.7K_0402_5%
12
R784@10K_04021 2
C784
0.1U_0402_10V6K
1
2
R79710K_0402_1%
12
R792
@10K_0402
12
RP151 4.7K_0804_8P4R_5%
1 82 73 64 5
C7820.1U_0402_10V6K
1
2
R7962.2K_0402_5%
12
R1174
FIR@10K_0402
12
R783
@4.7K_0402_5%
12
C781
10U_0805_10V4Z
1
2
RP152 4.7K_0804_8P4R_5%
1 82 73 64 5
R1173
10K_0402
12
LPC
PARA
LLEL
PAR
T
GAME PORT
SERI
AL P
OART
1
SERI
AL P
OART
2
IR
FDD
HARDWARE MONITOR
U51
VT1211_LQFP128
INDEX#PD0 42TRK00#/PD1 41
WRTPRT#/PD2 40RDATA#/PD3 39
DSKCHG#/PD4 38PD5 37PD6 36PD7 35
WGATE#/SLCT 29WDATA#/PE 30
MTR1#/BUSY 31DS1#/ACK# 32
STEP#/SLCTIN# 34DIR#/PINIT# 43
HDSEL#/ERR# 33
DRVDEN0/AUTOFD# 44STB# 46
IRRX 64IRTX 65
VC
C5
GN
DD
18G
ND
D60
GN
DD
90
GN
DA
112
LRESET#28PCICLK19SERIRQ21LDRQ#20LFRAME#27
LAD026LAD125LAD224LAD323
DCD1# 53DSR1# 48
SIN1 51RTS1# 49SOUT1 52CTS1# 47DTR1# 50
RI1# 54
JBCX/GP13125
JACY/GP15123
JAB1/GP10128
JAB2/GP17121
JACX/GP12126
JBCY/GP14124
JBB11/GP11127
JBB2/GP16122
OVFAN/MSI/WDTO 119
VC
C45
VC
C75
GN
DD
99V
CC
A10
5
CLKIN 17
DTDP111 DTDN110
UIC5109 UIC4108 UIC3107
VREF106
UIC1103UIC2104
FANOUT1116 FANOUT2/GP20115 FANIO1/DTEST114 FANIO2/GP21113
OVTEMP#117BEEP118
VC
C22
GP24/IRRX1 100
XD0/GP3094XD1/GP3193XD2/GP3292XD3/GP3391XD4/GP3489XD5/GP3588XD6/GP3687XD7/GP3786XA0/GP4085XA1/GP4184XA2/GP4283XA3/GP4382XA4/GP4481XA5/GP4580XA6/GP4679XA7/GP4778XA8/GP5077XA9/GP5176XA10/GP5274XA11/GP5373XA12/GP5472XA13/GP5571XA14/GP5670XA15/GP5769XA16/GP6068XA17/GP6167XA18/GP6266
GP23/ATEST/OVFAN/COPEN 101
SMI# 98GP25/MEMW# 97GP26/MEMR# 96
GP27/ROMCS# 95
INDEX# 2MTRA# 3DRVB# 4DRVA# 6MTRB# 7
DIR# 8STEP# 9
WDATA# 10WGATE# 11
TRK0# 12WPT# 13
RDATA# 14HDSEL# 15
DSKCHG# 16DSEL0# 1
OVOLT/MSO/DSEL1 120
GP22/ITMOFF//OVOLT/PLED 102
GP71/SMBDT/DCD2# 62GP72/SMBCK/SOUT2 61
GP73/VID0/SIN2 59GP74/VID1/DTR2# 58GP75/VID2/RTS2# 57GP76/VID3/DSR2# 56GP77/VID4/CTS2# 55
GP70/SCLK/ITMOFF/RI2# 63
R79510K_0402_1%
12
C789
@10P_0402_50V8J
1
2
C786
0.1U_0402_10V6K1
2
R793
@10K_0402
12
R11094.7K_0402_5%
12
L55
0_0805_5%1 2
C787
0.1U_0402_10V6K
1
2
C785
0.1U_0402_10V6K
1
2
R790
@33_0402
12
R791
@10_0402_5%
12
R787 4.7K_0402_5%1 2
R798
4.7K_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FD6
LPTAFD# AFD/3M#
LPTSTB#
FD0
FD7
LPTERR#
FD5
LPD2
LPTSLCT
LPD3
LPD7
SLCTIN#
LPTACK#
PWRPRN
FD5
LPTINIT#
FD3
PRNINIT#
FD7
FD0
FD5
LPTERR#
LPTSLCTIN#
LPD[0..7]
FD1
LPTPEAFD/3M#
FD2
LPD0
LPD6
FD6
AFD/3M#
FD1
PRNINIT#
FD7
FD4
FD4
LPD4
SLCTIN#
FD4LPD5
SLCTIN#
LPTACK#
LPTBUSY
FD2
FD3
LPTERR#
LPTPE
LPD1
LPTSLCT
PRNINIT#
FD6
LPTBUSY
DSKCHG#
TRACK0#WP#INDEX#
FD4
FD7
FD5FD6
FD1
FD3
FD0
FD2
FD1FD2
FD0
FD3
LPTACK#LPTBUSY
LPTSLCTLPTPE
INDEX#
DRV0#
DSKCHG#
3MODE#
MTR0#
FDDIR#
WDATA#
HDSEL#
WGATE#
WP#
TRACK0#
RDATA#
STEP#
RDATA#
WDATA#
FDDIR#MTR0#
DRV0#DSKCHG#
HDSEL#
TRACK0#
RDATA#WP#
WDATA#
3MODE#
WGATE#
STEP#
INDEX#
LPD[0..7]<39>
LPTACK#<39>
LPTINIT#<39>
LPTSLCTIN#<39>
LPTSTB#<39>
LPTAFD#<39>
LPTBUSY<39>
LPTERR#<39>
LPTSLCT<39>
LPTPE<39>
INDEX#<39>
FDDIR#<39>
DSKCHG#<39>
RDATA#<39>
MTR0#<39>
HDSEL#<39>
3MODE#<39>
WDATA#<39>
WGATE#<39>
TRACK0#<39>
WP#<39>
STEP#<39>
DRV0#<39>
+5V_PRN
+5V_PRN
+5V_PRN
+5V_PRN
+5VS
+5V_PRN
+5V_PRN
+5VS
+5VS
+5VS
+5VS
+5VS
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
Pallel port and FDD
B
40 66星期 , 02, 2003二 九月
w=10mils
w=10
mils
Parallel Port FDD CONN.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Compal Electronics, Inc.
RP123
68_1206_16P8R_5%
12345678 9
10111213141516
R801
33_0402_5%12
JP38
ACES_85201-2605
11223344556677889910101111121213131414151516161717181819192020212122222323242425252626
CP13
220P_1206_8P4C_50V8K
234 5
6781
C792
47P_0402_50V8J
1 2
CP11
220P_1206_8P4C_50V8K
234 5
6781
C975
220P_0402_25V8K
1 2
R1160
330_0402_5%
R803 33_0402_5%1 2
C793
0.1U_0402_10V6K1
2
R1159
330_0402_5%
CP17
220P_1206_8P4C_50V8K
234 5
6781
CP12
220P_1206_8P4C_50V8K
234 5
6781
R800 33_0402_5%1 2
C790
4.7U_0805_10V4Z
1
2
CP16
220P_1206_8P4C_50V8K
234 5
6781
C976
220P_0402_25V8K
1 2
JP39SUYIN_070536FR025S204AU
1325122411231022
921
820
719
618
517
416
315
214
1
CP14
220P_1206_8P4C_50V8K
234 5
6781
C794
0.1U_0402_10V6K
1
2
C791
0.1U_0402_10V6K
1
2
CP15
220P_1206_8P4C_50V8K
234 5
6781
RP122
2.7K_1206_10P8R_5%
109876
12345
D48
1SS355_SOD323
12
RP120
2.7K_1206_10P8R_5%
109876
12345
R802 33_0402_5%1 2
RP119
330_0804_8P4R_5%
1 82 73 64 5
R799
2.7K_0402_5%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SPDIFO
DOCK_LOUT_L
USB4+
DOCK_LOUT_RDOCK_PRESENT
TV_GND
USB20_NEC_P4-USB20_NEC_P4+
USB20P4+USB20P4-
USB4-
USB4-USB4+
DOCK_PRESENT
SPDIFO
RTS1# <39>CTS1# <39>
RI1# <39>
TV_LUMA<11,17,48>TV_COMPS<11,17,48>
DSR1# <39>RJ45_RXX-<34>RJ45_RXX+<34>
TV_CRMA<11,17,48>
SOUT1 <39>SIN1 <39>
DCD1# <39>DTR1# <39>RJ45_GND<34>
TV_GND<48>
RJ45_TXX-<34>RJ45_TXX+<34>
DOCK_LOUT_L <38>DOCK_LOUT_R <38>
SPDIFO <37>JACK_DET# <46>
USB20P4+<27>USB20P4-<27>
USB20_NEC_P4-<36>USB20_NEC_P4+<36>
VOLBTN-#,46>
CONA#<37,46>
VOLBTN+# <38,44,46>
USB_VCCA
DOCKVINDC_IN
+5VS
USB_VCCA
DOCKVINDOCKVIN
+3V
+3VALW
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
SPR Connector
41 66, 07, 2003星期四 八月
Compal Electronics, Inc.
SPR 36 PIN For X7
RJ45_GND TRACE AT LEAST 20 MIL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Note: PLACE CLOSE TO SPR PORT (JP40)L
L
Note: PLACE CLOSE TO SPR PORT (JP40)
CF5
1
H18HOLEA
1
H1HOLEA
1
H10HOLEA
1
H20HOLEA
1
R880
470_0402_5%
12
H28HOLEA
1
R1090 ATI@0_0402_5%1 2
CF16
1
CF4
1
H22HOLEA
1
C804
1000P_0402_50V7K
1
2
C805
1000P_0402_50V7K
1
2
C801
@1000P_0402_50V7K
1
2
C971
1000P_0402_50V7K
1
2
FM51
R1093 NEC@0_0402_5%1 2
CF2
1
CF15
1
H8HOLEA
1
CF25
1
CF20
1
H30HOLEA
1
H17HOLEA
1
C798
@10U_0805_16V4Z_V1
1
2
H6HOLEA
1
FM31
H31HOLEA
1
R1092 NEC@0_0402_5%1 2
CF6
1
R1141 200_0402_5%1 2
CF18
1
CF7
1
H19HOLEA
1
H23HOLEA
1
CF13
1
H27HOLEA
1
CF11
1
CF27
1
C800
0.1U_0402_10V6K
1
2
JP40
FOX_QL11183-C6HQ
1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 32
33 34
35 36BOSS
137
BOSS
238
CF17
1
R1139 @10K_0603_5%
C972
1000P_0402_50V7K
1
2
H24HOLEA
1
R879
10K_0402_5%
12
FM21
CF9
1
CF21
1
FM11
H13HOLEA
1
L56
KC FBM-L18-453215-900LMA90T_18121 2
R1140 200_0402_5%1 2
FM61
H7HOLEA
1
CF24
1
H9HOLEA
1
CF3
1
Q65MMBT3904_SOT23
2
31
R1131 1K_0603_5%1 2
CF8
1
H3HOLEA
1
H11HOLEA
1
CF22
1
CF1
1
H14HOLEA
1
C963
@0.01U_0402_50V7K
1
2
H12HOLEA
1
H4HOLEA
1
CF19
1
H26HOLEA
1
H25HOLEA
1
R1161
0_0805_5%1 2
FM41
CF14
1
H2HOLEA
1
CF12
1
H21HOLEA
1
CF26
1
CF23
1
H5HOLEA
1
H16HOLEA
1
R1091 ATI@0_0402_5%1 2
CF10
1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
KSI0KSO16
PWR_BACK#
KSI1
KSI2
WIRELESS_BTN
KSI3
WIRELESS_LED#
PWR_ACTIVE_PAV#
CARD_LED#
PRES_LEDVCC
PAV_LEDVCC
PAV_LEDVCC
PAV_LEDVCC
PAV_LEDVCC
PRES_LEDVCC
PAV_LEDVCC
PRES_LEDVCC
PWR_ACTIVE_PRES#
PRES_LEDVCC
PAV_LEDVCC
PAV_LEDVCC
PAV_LEDVCC
TP_OFF_LED#<46>
PWR_BACK#<46>
KSO16<46>
KSI1 <45,46>
KSI0 <45,46>
KSI2 <45,46>
KSI3 <45,46>
WIRELESS_BTN <38,46>
WIRELESS_LED#<38,43,44>
PWR_ACTIVE_PAV#<46>
CARD_LED#<31>
NUMLED#<46>
PRES_LEDVCC <44,46>
PAV_LEDVCC <44>CAPSLED#<46>
PWR_ACTIVE_PRES#<46>
+3VS
+5V
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
LED INDICATOR
B
42 66星期 , 07, 2003四 八月
FOR POWER BUTTONBACKLIGHT ( PAV)
FOR 3 PROGRAMINGBUTTON BACKLIGHT(PAV)
FOR CARDREADER INDICATOR ( PAV /PRES )
FOR WIRLESS LED( PAV )
3 FORPROGRAMING
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
FOR TP ON OFF
FOR WIRELESS ON OFF
Compal Electronics, Inc.
FOR POWER BUTTONBACKLIGHT ( PRES )
PIR BOM 92.07.30
PIR BOM 92.07.30
PIR BOM 92.07.30
PIR BOM 92.07.30
PIR BOM 92.07.30
PIR BOM 92.07.30
PIR BOM 92.07.30
PIR BOM 92.07.30
R1057
PAV@1K_0402_5%
12
R882
27_0402_5%1 2
D52PAV@HSMB-C172 BLUE_0805
21
C842
@.1UF_04021
2
Q68
PDTA114EK_SC59
C1
E3
B2
Q62
PAV@PDTA114EK_SC59
C1
E3
B2
R881 PAV@91_0402_5%1 2
D53
PAV@HSMB-C172 BLUE_0805
21
C810
@.1UF_0402
12 C811
@.1UF_040212
D65
PAV@HSMB-C172 BLUE_0805
21
D55
PAV@HSMB-C172 BLUE_0805
21
SW4 PAV@TC010-PS11CET_5P
2
3
1
4
5
D56PRES@HSMG-C170_GRN_0805
21
D63PRES@HSMG-C170_GRN_0805
21
R889PAV@91_0402_5%
12
R1014
10K_0402_5%
12
D58PRES@HSMG-C170_GRN_0805
21
D61PRES@HSMG-C170_GRN_0805
21
D92
PAV@HSMB-C172 BLUE_0805
21
C831
@.1UF_0402
12
D60
PAV@HSMB-C172 BLUE_0805
21
SW7 TC010-PS11CET_5P
2
3
1
4
5
D64
PAV@HSMB-C172 BLUE_0805
21
R113691_0402_5%
12
R1138
10K_0402_5%
12
SW5 PAV@TC010-PS11CET_5P
2
3
1
45
C809
@.1UF_0402
12
R888
27_0402_5%1 2
Q66
PDTA114EK_SC59
C1
E3
B2
Q71
PDTA114EK_SC59
C1
E3
B2
Q70
PAV@MMBT3904_SOT232
31
SW6 PAV@TC010-PS11CET_5P
2
3
1
4
5
Q69
PDTA114EK_SC59
C1
E3
B2
D59
PAV@HSMB-C172 BLUE_0805
21
D62PAV@HSMB-C172 BLUE_0805
21
R1058
PAV@10K_0402_5%
12
Q116
MMBT3904_SOT232
31
R890
91_0402_5%1 2
R1137
1K_0402_5%
R885
91_0402_5%1 2
Q117
PRES@PDTA114EK_SC59
C1
E3
B2
R1146 PRES@300_0402_5%1 2
SW3 PAV@TC010-PS11CET_5P
2
3
1
4
5
D57
PRES_1520@12-21SYGC/S530-E1/TR8_GRN
21
3
D54
PAV@HSMB-C172 BLUE_0805
21
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
MDM_PME#
PCI_AD18
PCI_AD18
CLK_PCI_MINI
MINIPCI_AD22
PCI_AD22
CLK_PCI_MINI
PCI_PIRQC#
WL_ON
MINIPCI_PME#
PCI_AD14<26,31,34,35,36>
PCI_GNT#3 <26,36>
PCI_CLKRUN#<26,31,34,35,36>
PCI_AD18 <26,31,34,35,36>
PCI_PERR#<26,31,34,35,36>
PCI_AD16 <26,31,34,35,36>
PCI_AD3<26,31,34,35,36>
PCI_AD29<26,31,34,35,36>
PCI_AD21<26,31,34,35,36>
PCI_PAR <26,31,34,35,36>PCI_AD20 <26,31,34,35,36>
PCI_PIRQC#<26,36>
PCI_AD15 <26,31,34,35,36>
PCI_AD17<26,31,34,35,36>
PCI_AD5<26,31,34,35,36>
PCI_CBE#2<26,31,34,35,36>
PCI_SERR#<26,31,34,35,36>
PCI_AD11 <26,31,34,35,36>
PCI_AD23<26,31,34,35,36>
PCI_AD8<26,31,34,35,36>
MDM_PME# <31,34,36,46,47>
PCI_AD28 <26,31,34,35,36>
PCI_STOP# <26,31,34,35,36>
PCI_AD2 <26,31,34,35,36>
PCI_AD12<26,31,34,35,36>
PCI_AD26 <26,29,31,34,35,36>
PCI_AD9 <26,31,34,35,36>
PCI_AD31<26,31,34,35,36>
PCI_RST# <11,26,30,31,34,35,36,46>
PCI_AD30 <26,31,34,35,36>
PCI_AD7<26,31,34,35,36>
PCI_AD25<26,31,34,35,36>
PCI_AD10<26,31,34,35,36>
PCI_REQ#3<26,36>
PCI_IRDY#<26,31,34,35,36>
PCI_AD6 <26,31,34,35,36>
PCI_AD24 <26,31,34,35,36>
PCI_CBE#0 <26,31,34,35,36>
PCI_AD0 <26,31,34,35,36>
PCI_DEVSEL# <26,31,34,35,36>
PCI_FRAME# <26,31,34,35,36>
PCI_CBE#3<26,31,34,35,36>
PCI_GNT#4 <26,36>PCI_REQ#4<26,36>
PCI_TRDY# <26,31,34,35,36>
PCI_AD27<26,31,34,35,36>
PCI_AD13 <26,31,34,35,36>
PCI_AD22 <26,31,34,35,36>PCI_AD19<26,31,34,35,36>
PCI_AD4 <26,31,34,35,36>
PCI_AD1<26,31,34,35,36>
CLK_PCI_MINI<26>
PCI_CBE#1<26,31,34,35,36>
WL_ON<44,46>
WIRELESS_LED#<38,42,44>
MINIPCI_AD22<44>
MINIPCI_PME# <44>
+5VS
+3VS
+3VALW
+5VS
+5VS
+3VALW
+3VALW
+5VS
+3VS
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
Mini PCI Slot
43 66, 07, 2003星期四 八月
Compal Electronics, Inc.
W=40mils
W=40mils
LAN RESERVED LAN RESERVEDTIP
W=40mils
W=40mils
IDSEL : AD18
RING
W=30mils
W=30mils
W=30mils
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R302
@10_0402_5%
12
C275
@15P_0402_50V8J
1
2
D88 1N4148_SOT231 2
C286
1000P_0402_50V7K1
2
KEY KEY
JP12
AMP_1318644-1
11 2 2
33 4 455 6 677 8 899 10 101111 12 121313 14 141515 16 161717 18 181919 20 202121 22 222323 24 242525 26 262727 28 282929 30 303131 32 323333 34 343535 36 363737 38 383939 40 404141 42 424343 44 444545 46 464747 48 484949 50 505151 52 525353 54 545555 56 565757 58 585959 60 606161 62 626363 64 646565 66 666767 68 686969 70 707171 72 727373 74 747575 76 767777 78 787979 80 808181 82 828383 84 848585 86 868787 88 888989 90 909191 92 929393 94 949595 96 969797 98 989999 100 100101101 102 102103103 104 104105105 106 106107107 108 108109109 110 110111111 112 112113113 114 114115115 116 116117117 118 118119119 120 120121121 122 122123123 124 124
C284
4.7U_0805_10V4Z
1
2
C272
0.1U_0402_10V6K
1
2
C285
0.1U_0402_10V6K
1
2
D89 RB751V_SOD32321
C278
1000P_0402_50V7K1
2
C281
4.7U_0805_10V4Z
1
2
R304 @10K_0402_5%1 2
C269
0.1U_0402_10V6K
1
2
C277
0.1U_0402_10V6K
1
2
C274
0.1U_0402_10V6K
1
2
C276
4.7U_0805_10V4Z
1
2
C280
4.7U_0805_10V4Z
1
2
C270
1000P_0402_50V7K
1
2
C282
@1000P_0402_50V7K1
2
C271
0.1U_0402_10V6K
1
2 C273
1000P_0402_50V7K
1
2
R301 100_0402_5%1 2
+5VMDC
ACT_LED
MRING
USB2-
USB0-USB0+
BT_VCC
USB20_NEC_P0+USB20_NEC_P0-
USB20P0-USB20P0+
USB20P2+USB20P2-
USB20_NEC_P2+USB20_NEC_P2-
USB2+
USB20P1+USB1-USB20P1-USB1+
USB20_NEC_P1-USB20_NEC_P1+
BT_VCC
USB3-
USB5+USB5-
USB3+
USB5-
USB5+
TIP
MD_MIC<37>
MDC_DET# <39>
AC97_SYNC <27,29,37>AC97_SDIN1 <27>
AC97_RST#<27,37>
MD_SPK <37>
AC97_BITCLK <27,37>
AC97_SDOUT<27,29,37>
TP_DATA<46>TP_CLK<46>
BATLED_0<45>
PMLED_1<45>
WL_ON<43,46>
WIRELESS_LED#<38,42,43>
USB20_NEC_P0-<36>USB20_NEC_P0+<36>
USB20P0+<27>USB20P0-<27>
USB20P1+<27>
USB20P2+<27>USB20P2-<27>
USB20_NEC_P2-<36>USB20_NEC_P2+<36>
USB20_NEC_P1-<36>USB20_NEC_P1+<36>
USB20P1-<27>
OVCUR_USB20#1 <36>
OVCUR#0 <27>
OVCUR#1 <27>
OVCUR_USB20#0 <36>
MINIPCI_AD22<43>MINIPCI_PME#<43>
USB20P3+<27>USB20P3-<27>
USB20P5-<27>USB20P5+<27>
VOLBTN+#<38,41,46>
VOLBTN-#<38,41,46>
ACT_LED<45>
MUTE_LED<37,38>
PAV_LEDVCC<42>
USB20_NEC_P3-<36>
USB20_NEC_P3+<36>
PRES_LEDVCC<42,46>
PMLED_1#<45,46>
BATLED_0#<45,46>
+3VS+5VS
+3V
+3VS
+3V
+3VS
+5V
+5V
+5V USB_VCCB
USB_VCCA+5V
USB_VCCA
USB_VCCB
USB_VCCB
+3VS
+3V
+3VS
+3VS
+5VS
+5VS
+5VALW
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
MDC , Bluetooth & USB CONN.
44 66, 07, 2003星期四 八月
Compal Electronics, Inc.
MDC Conn.
RJ11 CONN.
Note: PLACE CLOSE TO EACH USB PORT
USB KEY
TP CONNECTOR
Front Board CONNECTORPavilion only
PRESARIO only
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
BT CONNECTOR
W=40mils
RIGHT USB CONNECTOR 0
W=40mils
LEFT USB CONNECTOR 1
W=40mils
LEFT USB CONNECTOR 2
L
L Note: PLACE CLOSE TO EACH USB PORT (JP18)
L Note: PLACE CLOSE TO EACH USB PORT (JP19)
L Note: PLACE CLOSE TO EACH USB PORT (JP20)
L Note: Place close to JP43.1
L Note: Place close to JP43
L Note: Place close to JP46
Front Board CONNECTOR
PIR BOM & LAYOUT 92.07.30
JP44
ACES_87152-080712345678
C299
@0.1U_0402_10V6K1
2
C313
0.1U_0402_10V6K
1
2
R1080 0_0402_5%1 2
R1073 NEC@0_0402_5%1 2
C309
1000P_0402_50V7K
1
2
R895
330K_0402_5%
12
R809
4.7K_0603_1%
12
R1077 NEC@0_0402_5%1 2
L80PAV@CHB1608B121_06031 2
L88PAV@CHB1608B121_06031 2
JP46
ACES_85201-0405
1234
L90 PRES@CHB1608B121_06031 2
L86PAV@CHB1608B121_06031 2
R1084 100_0402_5%1 2
R1074 NEC@0_0402_5%1 2
R976 ATI@0_0402_5%1 2
R323 10K_0402_5%1 2
JP18
suyin_020167mr004s511zu_4p
1234
JP16
FOXCONN_JM34613-L002-TR
3344 6 65 5
11
22
R1070 NEC@0_0402_5%1 2
R320
100K_0402_5%
12
R319 @0_0805_5%1 2
C977
@220PF_3KV_1808
12
+C312
100U_D2_6.3VM
1
2
L81PAV@CHB1608B121_06031 2
C308
0.1U_0402_10V6K
1
2
C958
0.1U_0402_10V6K
1
2
R325 22_0402_5%12
L91 PRES@CHB1608B121_06031 2
L95 CHB1608B121_06031 2
R1075 ATI@0_0402_5%1 2
L87PAV@CHB1608B121_06031 2
D87 1N4148_SOT231 2
R1055 10K_0402_5%1 2
R896
560K_0402_5%
12
C832
1000P_0402_50V7K
1
2
JP47
MOLEX_53398_0290
1122
L84PAV@CHB1608B121_06031 2
C978
@220PF_3KV_1808
12
R979 ATI@0_0402_5%1 2
C304
0.1U_0402_10V6K1
2
R981 ATI@0_0402_5%1 2
+C315
100U_D2_6.3VM
1
2
JP43
ACES_85201-0805
12345678
C955
0.1U_0402_10V6K
1
2
C311
0.1U_0402_10V6K
12
R894
560K_0402_5%
12
R1072 NEC@0_0402_5%1 2
R326 22_0402_5%12
C310
0.1U_0402_10V6K
12
L92 PRES@CHB1608B121_06031 2
L89PAV@CHB1608B121_06031 2
+C307
100U_D2_6.3VM
1
2
C298
@1000P_0402_50V7K
1
2
C314
1000P_0402_50V7K
1
2
L96CHB1608B121_06031 2
C954
1000P_0402_50V7K
1
2
C813
0.47U_0603_10V7K
1
2
C812
0.47U_0603_10V7K
1
2
G
D
SQ1002N7002_SOT23
2
13
C302@1000P_0402_50V7K
12
R1071 ATI@0_0402_5%1 2
R977 ATI@0_0402_5%1 2
L83PAV@CHB1608B121_06031 2
C30522P_0402_25V8K
1
2
JP19
suyin_020167mr004s511zu_4p
1234
C301
0.1U_0402_10V6K
1
2
Q99
SI2301DS_SOT23
D1
S3
G2
L93 PRES@CHB1608B121_06031 2
L97 CHB1608B121_06031 2
R1076 NEC@0_0402_5%1 2
R980 ATI@0_0402_5%1 2
R1083 100_0402_5%1 2
R982 ATI@0_0402_5%1 2
R1069 NEC@0_0402_5%1 2
U14
AATI4610GV-T1_SOT23_5
VIN5
ON#4SET 3
VOUT 1
GND2
C316
0.1U_0402_10V6K
1
2
U13
AATI4610GV-T1_SOT23_5
VIN5
ON#4SET 3
VOUT 1
GND2
L79PAV@CHB1608B121_06031 2
R810
4.7K_0603_1%
12
R978 ATI@0_0402_5%1 2
L85PAV@CHB1608B121_06031 2
R1082 NEC@0_0402_5%1 2
C300
1000P_0402_50V7K
1
2
C957
10U_0805_10V3M
1
2
C303
4.7U_0805_10V4Z
1
2
JP42
PAV@ACES_85201-1405
11223344556677889910101111121213131414
L94 PRES@CHB1608B121_06031 2C833
1000P_0402_50V7K
1
2
R983 ATI@0_0402_5%1 2
R32710_0402_5%
12
R1079 0_0402_5%1 2
JP20
suyin_020167mr004s511zu_4p
1234
C317
1000P_0402_50V7K
1
2
R893
330K_0402_5%
12
R1081 NEC@0_0402_5%1 2
R1078 NEC@0_0402_5%1 2
JP45
PRES@ACES_85201-0805
12345678
JP17
ACES_88021-3000
MONO_OUT/PC_BEEP1GND3AUXA_RIGHT5AUXA_LEFT7CD_GND9CD_RIGHT11CD_LEFT13GND15
AC97_SDATA_OUT23 3.3Vmain21
3.3Vaux17GND19
AC97_RESET#25GND27AC97_MSTRCLK29
AUDIO_PWDN 2MONO_PHONE 4
Bluetooth Enable 6GND 8+5V 10
USB Data+ 12USB Data- 14
PRIMARY DN 165Vd 18
GND 20AC97_SYNC 22
AC97_SDATA_IN1 24AC97_SDATA_IN0 26
GND 28AC97_BITCLK 30
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
IRRX
IRTXOUTIRMODE
ON/OFFBTN#
+5V
S_F
IR
EC_ON
ON/OFF#
KSI[0..7]
KSO[0..15]
ON/OFFBTN#
KSO1
KSI1
KSO7
KSO13
KSO3
KSO2
KSO10
KSO8
KSI2
KSI7
KSO0
KSO12
KSO15
KSI0
KSO4
KSI6
KSO5
KSO11
KSO9
KSI3
KSO14
KSO6
KSI5KSI4
KSO10KSO15
KSO11KSO14
KSO6KSO3KSO12KSO13
KSO7
KSO2
KSO8
KSO4
KSO1KSI0
KSI3KSO5
KSI4
KSO0KSI2
KSI5
KSI7KSI1
KSI6KSO9
IRTXOUT <39>IRMODE <39>
IRRX <39>
EC_PWR_ON# <51>
ON/OFF# <46>
LID_SW# <46>
EC_ON<46>
KSO[0..15] <46>
KSI[0..7] <42,46>
BATLED_0#<44,46>
ACT_LED#<30>
PMLED_1#<44,46>
ACT_LED <44>
PMLED_1 <44> BATLED_0 <44>
+5VS
+3VS
+3VALW
+3VALW
+5VS
+3VALW
+3VALW
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
KBD,ON/OFF,T/P,LED & FIR
45 66, 07, 2003星期四 八月
Compal Electronics, Inc.
FIR Module
T = 12mil
T = 12milT = 12mil
T = 40mil
T = 20mil
Power BTN
WHEN R=33K,Vbe=0.8VWHEN R=0,Vbe=1.35V
INT_KBD CONN.
Touch Pad & Status LED Conn.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PIR BOM 92.07.30
PIR BOM 92.07.30 PIR BOM 92.07.30
PIR BOM 92.07.30
22K
22K
Q21DTC124EK_SOT23
2
13
D29
RLZ20A_LL34
12
R306
470_0402_5%
12
R308
FIR@10_1206_5%
12
SW8PRES@TC010-PS11CET_5P
2
3
1
4
5
R923 220_0402_5%1 2
R307 0_0402_5%1 2
D27 @PSOT03C
3
2
CP4
100P_1206_8P4C_50V8
234 5
6781
SW9
ESE11MV9_4P
2
4
1
3
D28
DAN202U_SC70
2
31
R305 100K_0402_5%1 2
C291
FIR@22U_1206_16V4Z
1
2
D30 @PSOT03C
32
SW1PAV@TC010-PS11CET_5P
2
3
1
4
5
R924 220_0402_5%1 2
C294
FIR@0.1U_0402_10V6K
1
2
CP1
100P_1206_8P4C_50V8
234 5
6781
+ C292
FIR@10U_0805_6.3VM1
2JP13
ACES_85201-2405
123456789101112131415161718192021222324
10K
10KC
BE
Q93DTA114EK
31
2
R925 470_0402_5%1 2
CP2
100P_1206_8P4C_50V8
234 5
6781
10K
10KC
BE
Q94DTA114EK
31
2
C290
FIR@0.1U_0402_10V6K
1
2
CP5
100P_1206_8P4C_50V8
234 5
6781
10K
10KC
BE
Q92DTA114EK
31
2
C293
FIR@0.1U_0402_10V6K
1
2U12
FIR@IR_VISHAY_TFDU6101E-TR4_8P
IRED_C2
GND8 MODE 7SD/MODE 5
IRED_A 1
RXD4VCC6
TXD 3
C289
1000P_0402_50V7K
1
2
G
D
S
Q112@2N7002_SOT23
2
13
CP3
100P_1206_8P4C_50V8
234 5
6781
R309
FIR@10_1206_5%
12
CP6
100P_1206_8P4C_50V8
234 5
6781
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
KBA18
KBA13
KBA8
KBA5
EC_TCK
EC_SMD_2 ADB3
ADB0
EC_SMC_1
ADB1
ADB[0..7]
KBA16
LID_SW#
SELIO#
KBA10
FRD#
C RY1
KBA3
EC_TINIT#
KBA[0..19]FSEL#KBD_CLK
SELIO#
KBA15
KBA4
KBA5
EC_SMI#
KBA1
KBA3
EC_TMS
FRD#
LID_SW#
KBA12
KBA2
ECAGND
FWR#
KBA1
KBA7
EC_TDI
ADB7
ECAGND
KBA11
C RY2
KBA0
ECAGND
ADB6
KBA17
EC_SMD_1
KBA14
EC_SMC_2
KBA6
EC_TDO
ADB4
ADB2
CLK_PCI_EC
KBA9
ADB5
EC_RST#
ADP_IR
KBA2
KBA19
CLK_PCI_EC
KSI[0..7]
KSI2
KSI6
KSI1
KSI5
KSI0
KSI7
KSI3KSI4
TP_CLKTP_DATA
PS2_CLKPS2_DATA
EC_SMI#
FSEL#
KSO8
KSO11
KSO0
KSO2
KSO5
KSO[0..15]
KSO12
KSO9
KSO3
KSO13
KSO15
KSO1
KSO4
KSO7KSO6
KSO14
KSO10
EC_SMC_1
AC_IN
EC_SMC_2EC_SMD_2
EC_SMD_1
TP_OFF_LED#
M_SEN#
KSO16KSO17
PMLED_1#
KSO16
EC_TDO
EC_TMS
EC_TCK
EC_TDI
EC_TINIT#
KSO17
AC_IN
GA20KBRST#
KBD_DATA
FANSPEED1 BID
VOLBTN+#
VOLBTN-#
SCI#
VOLBTN-#
M_SEN#
BID
SCI#
VOLBTN+#
PMLED_1#
PWR_ACTIVE_PAV#
MMO_ON
PWR_ACTIVE_PRES#
PRES_DETECT
PRES_DETECT
PS2_DATAPS2_CLK
KBD_DATAKBD_CLK
TP_DATATP_CLK
LPC_FRAME#<26,39>
FRD# <47>
ADB[0..7] <47>
LPC_AD1<26,39>LPC_AD2<26,39>
LPC_AD0<26,39>
KBA[0..19] <47>
SLP_S5# <27>ON/OFF# <45>
SELIO# <47>
SIRQ<26,31,39>
BATT_TEMPA <51>
LPC_AD3<26,39>
ADP_I <51,52>
FWR# <47>
CAPSLED# <42>
CLK_PCI_EC<26>
KSO[0..15]<45>KSI[0..7]<42,45>
TP_DATA<44>TP_CLK<44>
LID_SW#<45>
FSEL#<47>
SUSP#<47,49>
EC_SWI#<27>
ENAVDD<10,17,25>
EC_SMI#<27>
VR_ON<55>
BKOFF#<25>
SYSON<49>
INVT_PWM <25>
LID_OUT# <27>
EN_FAN1 <7>DAC_BRIG <25>
EC_SMD_1 <47,51>EC_SMC_1 <47,51>
PWRBTN_OUT# <27>
EC_ON <45>
ACOFF <52>
SLP_S3# <27>
FANSPEED2 <7>
EC_SMC_2 <7>EC_SMD_2 <7>
FSTCHG <52>
TP_OFF_LED# <42>
PM_BATLOW# <27>
KSO16 <42>
BEEP# <37>
EC_THERM# <27>
ACIN <27,50,53>
KBRST#<27>GA20<27>
EC_RSMRST#<27>PCM_SUSP#<31>
BATT_OVP <52>
EN_FAN2 <7>IREF <52>
G_RST#<31,32,36>
FANSPEED1 <7>
JACK_DET# <41>
SCI#<27>
NUMLED# <42>
WIRELESS_BTN <38,42>VOLBTN-# <38,41,44>
WL_ON <43,44>
PCI_RST# <11,26,30,31,34,35,36,43>
M_SEN# <25>
VOLBTN+# <38,41,44>
PME_EC# <31,34,36,43,47>
EC_MUTE#<38>
PMLED_1# <44,45>
BATLED_0#<44,45>
PWR_BACK#<42>
CONA# <37,41>
PWR_ACTIVE_PAV#<42>
VTT_PWRGD <24,27,48>
PWR_ACTIVE_PRES#<42>
PRES_LEDVCC <42,44>
+3VALW
EC_AVCC
+5VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
EC_AVCC+3VALW
+3VS
+3VS
+5VALW
+3VALW
+3VS
+3VALW
+5VS +5VS
+5V
BATT1.1
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
KBD EC CTRL-NS PC87591L
46 66, 07, 2003星期四 八月
Compal Electronics, Inc.
(BADDR1)
1 1
0
ENV0
(BADDR0)
1 0
PROG
0 1
0
DEV
0 0
0
OBD
(ENV1)
TRIS
BADDR1-0
1
IRE
I/O Address
1
TRIS=1: While in IRE and OBD, float all the signals for clip-on ISE use
(SHBM)
1
Reserved
EC DEBUG port
(HCFGBAH, HCFGBAL)+1
SHBM=1: Enable shared memory with host BIOS
1
(HCFGBAH, HCFGBAL)
0
4F2F
0
4E
Data
*
0
2E
*
0
Index
0
ENV1
EEPROM/BATTERY
THERMAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PIR BOM & LAYOUT 92.07.30
PIR BOM & LAYOUT 92.07.30
PIR LAYOUT 92.07.30
PIR BOM & LAYOUT 92.07.30
C3221U_0603_10V6K1
2
R337
@10_0402_5%
12
R345 10K_0402_5%1 2
C9111U_0603_10V6K1
2
R929@1K_0402_5%
12
R33310K_0402_5%
1 2
R331
10K_0402_5%1 2
Host interface
Key matrix scan
JTAG debug port
PS2 interface
AD Input
DA output
PWMor PORTA
PORTB
PORTC
PORTE
PORTH
PORTI
PORTJ-1
PORTD-1
PORTD-2 PORTJ-2
PORTK
PORTL
PORTM
U15
PC87591L-VPCN01 A2_LQFP176
GA20/IOPB55KBRST/IOPB66
LAD015LAD114LAD213LAD310
RESET1#19
LFRAME#9
SERIRQ7
LCLK18
IOPD3/ECSCI#31
SMI#22PWUREQ#23
LDRQ#8
VDD
16
VCC
134
VCC
245
VCC
312
3VC
C4
136
AVC
C95
VBAT
161
KBSIN071KBSIN172KBSIN273KBSIN374KBSIN477KBSIN578KBSIN679KBSIN780
KBSOUT049KBSOUT150KBSOUT251KBSOUT352KBSOUT453KBSOUT556KBSOUT657KBSOUT758KBSOUT859KBSOUT960KBSOUT1061KBSOUT1164KBSOUT1265KBSOUT1366KBSOUT1467KBSOUT1568
TCK106
TDI108 TDO107
TINT#105
TMS109
PSCLK1/IOPF0110PSDAT1/IOPF1111PSCLK2/IOPF2114PSDAT2/IOPF3115PSCLK3/IOPF4116PSDAT3/IOPF5117PSCLK4/IOPF6118PSDAT4/IOPF7119
32KX1/32KCLKIN158
32KX2160
AD0 81AD1 82AD2 83AD3 84
IOPE0AD4 87IOPE1/AD5 88IOPE2/AD6 89IOPE3/AD7 90
DP/AD8 93DN/AD9 94
DA0 99DA1 100DA2 101DA3 102
IOPA0/PWM0 32IOPA1/PWM1 33IOPA2/PWM2 36IOPA3/PWM3 37IOPA4/PWM4 38IOPA5/PWM5 39IOPA6/PWM6 40IOPA7/PWM7 43
IOPB0/URXD 153IOPB1/UTXD 154
IOPB2/USCLK 162IOPB3/SCL1 163IOPB4/SDA1 164
IOPB7/RING/PFAIL/RESET2 165
IOPC0 168IOPC1/SCL2 169IOPC2/SDA2 170
IOPC3/TA1 171IOPC4/TB1/EXWINT22 172
IOPC5/TA2 175IOPC6/TB2/EXWINT23 176
IOPC7/CLKOUT 1
IOPE4/SWIN 2IOPE5/EXWINT40 44
IOPE6/LPCPD/EXWIN45 24IOPE7/CLKRUN/EXWINT46 25
IOPH0/A0/ENV0 124IOPH1/A1/ENV1 125
IOPH2/A2/BADDR0 126IOPH3/A3/BADDR1 127
IOPH4/A4/TRIS 128IOPH5/A5/SHBM 131
IOPH6/A6 132IOPH7/A7 133
IOPI0/D0 138IOPI1/D1 139IOPI2/D2 140IOPI3/D3 141IOPI4/D4 144IOPI5/D5 145IOPI6/D6 146IOPI7/D7 147
IOPJ0/RD 150IOPJ1/WR0 151
SELIO# 152
AGN
D96
GN
D1
17G
ND
235
GN
D3
46G
ND
412
2G
ND
515
9
IOPD0/RI1/EXWINT20 26IOPD1/RI2/EXWINT21 29
IOPD2/EXWINT24/RESET2 30
VCC
515
7VC
C6
166
GN
D6
167
GN
D7
137
IOPD4 41IOPD5 42IOPD6 54IOPD7 55
IOPJ2/BST062IOPJ3/BST163IOPJ4/BST269IOPJ5/PFS70IOPJ6/PLI75IOPJ7/BRKL_RSTO76 IOPK0/A8 143
IOPK1/A9 142IOPK2/A10 135IOPK3/A11 134IOPK4/A12 130
IOPK5/A13_BE0 129IOPK6/A14_BE1 121
IOPK7/A15_CBRD 120
IOPL0/A16 113IOPL1/A17 112IOPL2/A18 104IOPL3/A19 103
IOPM0/D8148IOPM1/D9149IOPM2/D10155IOPM3/D11156IOPM4/D123IOPM5/D134IOPM6/D1427IOPM7/D1528
IOPL4/WR1# 48
SEL0#173SEL1#174CLK47
NC
212
NC
320
NC
421
NC
585
NC
686
NC
791
NC
892
NC
997
NC
1098
NC
111
C326
0.1U_0402_10V6K1
2
RP24
10K_0804_8P4R_5%
1 82 73 64 5
L32
MURATA BLM11A20PT_06031 2
R114810K_0402_5%
12
R1175
1K_0402_5%
R340 20M_0603_5%1 2
R986
@0_0402_5%12
R926 @0_0603_5%1 2
J1 JOPEN12
C320
0.1U_0402_10V6K
1
2
JP21
@96212-1011S
1 12 23 34 45 56 67 78 89 9
10 10
R332
10K_0402_5%
1 2
R985 @0_0402_5%1 2
R335
10K_0402_5%1 2
R1169 10K_0402_5%1 2
R336 10K_0402_5%1 2
R342 20K_0402_5%1 2
C318
4.7U_0805_6.3V6K
1
2
R96010K_0402_5%
12
C327
1000P_0402_50V7K
1
2
C33110P_0402_50V8K
1
2
C321
0.01U_0402_16V7K
1
2
R1170 10K_0402_5%
1 2
D36 RB751V_SOD3232 1
L33MURATA BLM11A20PT_0603
1 2
C325 0.01U_0402_16V7K1 2
C319
0.1U_0402_10V6K1
2
R1171 10K_0402_5%1 2
R1162 10K_0402_5%1 2
R95910K_0402_5%
12
R9311K_0402_5%
12
RP23
10K_0804_8P4R_5%SD309100200
1 82 73 64 5
R984 0_0402_5%1 2
R1172 10K_0402_5%
1 2
C329
@15P_0402_50V8J
1
2
C3280.22U_0603_10V7K
1
2
C33010P_0402_50V8K
1
2
C323
4.7U_0805_6.3V6K
1
2
R1147
6.2K_0402_5%1 2
R338 10K_0402_5%1 2
R344
10K_0402_5%
12
R1135 33_0402_5%1 2
Y3
32.768KHZ_12.5P_MC-306
12
43
R341120K_0402_5%
12
R927 0_0603_5%1 2
R334
@10K_0402_5%1 2
R1163 10K_0402_5%
1 2
R1123@10K_0402_5%
@
12
C324
0.1U_0402_10V6K
1
2
KBA5
FWE#
KBA12
KBA[0..19]
ADB2
FWE#
KBA3
KBA8
KBA0
KBA17
ADB5
KBA1
ADB0
KBA11
KBA6KBA13
ADB1
KBA15
ADB6
KBA10
ADB7
KBA4
FSEL#
KBA7
ADB[0..7]
ADB3
KBA16
KBA2
KBA9
KBA14
KBA18
ADB4
FRD#
ADB5
ADB1
ADB4
ADB2ADB3
KBA2
ADB0
ADB7
SELIO#
ADB6
LARST#
ADB3ADB2
KBA19
RESET#
KBA13
KBA9
ADB4
KBA0
ADB6
KBA15
FSEL#KBA2
KBA6
ADB7
ADB5
FRD#KBA4
KBA10KBA11
KBA5
KBA7
KBA1
KBA12
ADB1
KBA18
KBA16
KBA8FWE#
KBA3
KBA17
KBA14
ADB0
KBA17
ADB7
KBA2
KBA18
ADB4
ADB0
KBA12
KBA10
RESET#
KBA7
ADB6
KBA16
FSEL#
ADB3
KBA15
FWE#
KBA14
ADB1
KBA19
KBA3KBA4
KBA9
KBA6
ADB5
KBA5
KBA0
KBA13
KBA8
ADB2
KBA1
KBA11
FRD#
EC_SMC_1<46,51>
ADB[0..7]<46>
EC_FLASH# <27>
FWR# <46>
EC_SMD_1<46,51>
KBA[0..19]<46>
MDM_PME#<31,34,36,43,46>ONBD_LAN_PME#<31,34,36,43,46>
PME_EC# <31,34,36,43,46>WLAN_PME#<31,34,36,43,46>
PCM_PME#<31,34,36,43,46>
FSEL#<46>FRD#<46>
SELIO#<46>
USB20_PME#<31,34,36,43,46>
SUSP# <46,49>
+3VALW
+3VALW+3VALW
+3VALW +3VALW +3VALW
+3VALW
+5VALW
+3VALW
+3VALW
+3VALW
+3VALW
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
BIOS & EC I/O Port
47 66, 07, 2003星期四 八月
Compal Electronics, Inc.
OUTPUT
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
U18ASN74LVC32APWLE_TSSOP14
A1
B2 O 3
P14
G7
R360@100K_0402_5%
1 2
C333 @0.1U_0402_16V7K1 2
R3564.7K_0402_5%
12
R354
10K_0402_5%
12
JP22
@SUYIN-80065A-040G2T
1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40
U20
@SST39VF080-70_TSOP40
A021A120A219A318A417A516A615A714A88A97A1036A116A125A134A143A152A161
A1813
CE#22OE#24
D0 25D1 26D2 27D3 28D4 32D5 33D6 34D7 35
GND1 39
A1740
WE#9
VCC1 30VCC0 31
GND0 23
A1937
NC0 29NC1 38
NC 11RP# 10
READY/BUSY# 12
U19
512K8-90_PLCC32
A181A162A153A124A75A66A57A48A39A210A111A012DQ013DQ114DQ215
DQ3 17DQ4 18DQ5 19DQ6 20DQ7 21CE# 22A10 23OE# 24A11 25A9 26A8 27A13 28A14 29
WE# 31VDD 32
VSS16
A17 30
U18CSN74LVC32APWLE_TSSOP14
A 9
B 10O8
P14
G7
G
D S
Q29 2N7002 1N_SOT23
2
1 3
R359100K_0402_5%
12
C338
0.1U_0402_10V6K
1
2
R357100K_0402_5%
12
R358100K_0402_5%
12
C334
@1U_0603_10V6K
1 2
U21
AT24C164-10SC_SO8
A0 1A1 2
SDA5 SCL6
VCC8
A2 3GND 4
WC7
R352
@20K_0402_5%
1 2
U17
@SN74HCT273PW_TSSOP20
Q0 2D14 Q1 5D27 Q2 6D38 Q3 9D413 Q4 12D514 Q5 15D617 Q6 16D718 Q7 19
D03
CP11
VCC
20
MR1 GN
D10
C336
0.1U_0402_10V6K1
2
C337
0.1U_0402_10V6K
1
2
TV_COMPS
TV_LUMAL
TV_CRMATV_COMPSLTV_CRMAL
TV_LUMA
SUSP
NB_PWRGD <8>
SB_PWRGD <27>
TV_COMPS<11,17,41>TV_CRMA<11,17,41>
TV_GND<41>
TV_LUMA<11,17,41>
VCORE_PWRGD<56>
SUSP<49,55>
VTT_PWRGD <24,27,46>
+3VALW
+2.5VS
+3VALW +3VALW+3VALW
+3VS
+3VALW
+3VS
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
POWER GOOD & P/S2 CKT
48 66, 07, 2003星期四 八月
Compal Electronics, Inc.
TV_OUT CONNECTOR
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R188
75_0402_5%
12
D20
DAN217_SOT23
2 31
U32E
SN74LVC14APWLE_TSSOP14
O 10I11
P14
G7
R603
330K_0603_5%1 2
C111
68P_0402_50V8K
1
2
R1106
330K_0402_5%1 2
L7 CHB1608B121_06031 2
R610
47K_0402_5%
12
R1107
1K_0402_5%
12
R608
1K_0402_5%
12
U18D
SN74LVC32APWLE_TSSOP14
A12
B13 O 11
P14
G7
L8 CHB1608B121_06031 2
R190
75_0402_5%
12
R961
0_0603_5%
12
U32D
SN74LVC14APWLE_TSSOP14
O 8I9
P14
G7
R189
75_0402_5%
12
G
D
S
Q110
@2N7002_SOT23
2
13
G
D
S
Q52
2N7002_SOT23
2
13
C110
68P_0402_50V8K
1
2
R605
1M_0402_5%1
2
U32B
SN74LVC14APWLE_TSSOP14
O 4I3
P14
G7
U32C
SN74LVC14APWLE_TSSOP14
O 6I5
P14
G7C606
0.1U_0402_16V7K
1
2
C115
68P_0402_50V8K
1
2
R601
10K_0402_5%
12
R606
10K_0402_5%
12
R604 47_0603_5%1 2
D19
DAN217_SOT23
2 31
C607
0.47U_0603_10V7K
1
2
L4 CHB1608B121_06031 2
G
D
S
Q111
@2N7002_SOT23
2
13
C114
68P_0402_50V8K
1
2
C112
68P_0402_50V8K
1
2
C113
68P_0402_50V8K
1
2
JP7
SUYIN_35138S-07T1-DF
1234567
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SYSON
SUSP SUSP
SUSP
SUSP
SYSON#
SUSPSUSP
SUSP
SYSON#
SYSON# SUSP
SUSP SUSP
SUSP
SYSON#
SUSP SYSON# SYSON#SYSON#
SUSP#<46,47>
SUSP<48,55>
SYSON<46>
+2.5VALW
+3VALW
+1.8VS
+2.5V
+5VALW
+2.5VS
+5VS
+12VALW
+5VALW
+3VS
+2.5VS
+5VALW
+3VS +5VS+1.25VS
+12VALW
+2.5VALW
+3V+3VALW
+5V+5VALW
+12VALW
+12VALW +12VALW
+12VALW
+1.5VSP +1.5VS+12VALW
+1.2VS_VGA+2.5V+5V+1.5VS +3V
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
DC/DC Circuits
49 66, 07, 2003星期四 八月
Compal Electronics, Inc.
+3VALW to +3VS Transfer
+2.5VALW to +2.5V Transfer
Discharge circuit
+5VALW to +5VS Transfer
+2.5V to +2.5VS Transfer
+3VALW to +3V Transfer
+5VALW to +5V Transfer
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
(6A,240mils ,Via NO.= 12)
+1.5VSP to +1.5VS Transfer
Place close to PJP4L(0.5A(VGA)+0.83A(VGA_RAM)+0.14A(SB)=1.5A,60mils,)
PIR BOM 92.07.30
G
D
S
Q39
2N7002 1N_SOT23
2
13
C350
10U_0805_6.3V6M
1
2
U23
SI4800DY_SO8
S 1S 2S 3G 4
D8D7D6D5
C959
10U_0805_6.3V6M
1
2R362
100K_0402_5%1
2
R1101
56K_0402_5%
12
G
D
S
Q43
2N7002 1N_SOT23
2
13
C346
10U_0805_6.3V6M
1
2
R1102
470_0402_5%
12
R1094
470_0402_5%
12
G
D
S
Q41
2N7002 1N_SOT23
2
13
G
D
S
Q382N7002 1N_SOT23
2
13
G
D
S
Q40
2N7002 1N_SOT23
2
13
R376
470_0402_5%
12
R369
10K_0402_5%
12
U56
SI4800DY_SO8
S 1S 2S 3G 4
D8D7D6D5
G
D
S
Q322N7002 1N_SOT23
2
13
C355
10U_0805_6.3V6M
1
2
C347
0.1U_0402_10V6K
1
2
G
D
S
Q102
2N7002 1N_SOT23
21
3
C627
0.1U_0402_10V6K
1
2
U24
SI4800DY_SO8
S 1S 2S 3G 4
D8D7D6D5
G
D
S
Q109
2N7002 1N_SOT23
2
13
C357
10U_0805_6.3V6M
1
2
C342
10U_0805_6.3V6M
1
2
R373
10K_0402_5%
12
C344
10U_0805_6.3V6M
1
2
R363
95.3K_0603_1%
12
G
D
S
Q42
2N7002 1N_SOT23
2
13
G
D
S
Q732N7002 1N_SOT23
2
13
R902
95.3K_0603_1%
12
G
D
S
Q742N7002 1N_SOT23
2
13
C844
0.1U_0402_10V6K
1
2
C358
0.1U_0402_10V6K
1
2
U25
SI4800DY_SO8
S 1S 2S 3G 4
D8D7D6D5
U22
SI4800DY_SO8
S 1S 2S 3G 4
D8D7D6D5
C352
0.1U_0402_10V6K
1
2
R372
470_0402_5%
12
R1095
470_0402_5%
12
C359
10U_0805_6.3V6M
1
2
C625
0.1U_0402_10V6K
1
2
R904
47K_0402_5%
12
C356
0.1U_0402_10V6K
1
2
C354
0.1U_0402_10V6K
1
2
C360
0.1U_0402_10V6K
1
2
C341
10U_0805_6.3V6M
1
2
R375
470_0402_5%
12
C960
0.1U_0402_10V6K
1
2
C353
10U_0805_6.3V6M
1
2
U26
SI4800DY_SO8
S 1S 2S 3G 4
D8D7D6D5
C343
0.1U_0402_10V6K
1
2
G
D
S
Q115
2N7002 1N_SOT23
2
13
G
D
S
Q36
2N7002 1N_SOT23
2
13
G
D
S
Q103
2N7002 1N_SOT23
2
13
C351
10U_0805_6.3V6M
1
2
R374
470_0402_5%
12
G
D
S
Q762N7002 1N_SOT23
2
13
R901
6.8K_0402_5%1
2
C626
10U_0805_6.3V6M
1
2
C961
10U_0805_6.3V6M
1
2
U36
SI4800DY_SO8
S 1S 2S 3G 4
D8D7D6D5
C962
0.1U_0402_10V6K
1
2
R378
470_0402_5%
12
G
D
S
Q752N7002 1N_SOT23
2
13
C348
0.1U_0402_10V6K
1
2
R377
470_0402_5%
12
R1116
470_0402_5%
12
R903
100K_0402_5%
12
C345
0.1U_0402_10V6K
1
2
G
D
S
Q312N7002 1N_SOT23
2
13
G
D
S
Q108
2N7002 1N_SOT232
13
C624
10U_0805_6.3V6M
1
2
G
D
S
Q342N7002 1N_SOT23
2
13
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
ADPIN
PACIN PACIN
ACIN <27,46,53>
PACIN <52>
MAINPWON<7,51,53>
DCSRD<52>
DC_IN
VL B+
DC_IN DC_IN
VS
VL
VS
ADPIN
+5VALW
VL
Title
Size Document Number Rev
Date: Sheet o f
0.7
Detector
50 66, 07, 2003星期四 八月
Compal Electronics, Inc.
Detector
Vin Detector
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ACIN
Precharge detector16.421 15.817 15.22914.108 13.657 13.002
BATT
detector15.029 14.095 13.18712.636 11.850 10.860
17.522 17.044 16.57517.026 16.544 16.090
PIR POWER 92.08.04
5V
PR
549
9K_0
603_
1%
12PC
810
00P_
0603
_16V
7K
12P
C7
0.1U
_060
3_25
V7K
12
PC
210
00P_
0402
_50V
8J
12
PR41M_0603_1%
1 2
PR110K_0603_5%
1 2
PC
1010
00P_
0603
_16V
7K
12
PR21M_0402_5%
12
PR91K_0603_1%
1 2
PC
910
00P_
0603
_16V
7k
12
PR6150K_0603_0.1%
12
PC
410
00P_
0402
_50V
8J
12
PR3432K_0603_1%
12
PC
610
00P_
0402
_50V
8J
12
PU1BLM393M_SO8
+5
-6 O 7
P8
G4
PC
310
0P_0
603_
50V8
G
12
PU1ALM393M_SO8
+ 3
- 2O1
P8
G4
PR78.2K_0805_5%
12
PC50.01U_0603_50V7K
12
PR81K_0603_5%
1 2
PR1010K_0603_1%
12
PR1410K_0603_5%
12
G
D
S
PQ46
2N7002_SOT23
2
13
PJP17PAD-OPEN 4x4m1 2
PZD1
RLZ4.3B_LL34
12
PR
191
499K
_060
3_1%
12
PR192
47K_0603_5%
1 2
PJP18
PAD-OPEN 4x4m
1 2
PR
1166
.5K_
0603
_1%
12
100K
100K
PQ47
DTC115EKA_SOT23
2
13
PCN1
FOX_JDP1021
1
2
3
4
PR1210K_0603_5%
12
PL1FBM-L18-453215-900LMA90T_1812
1 2PD43
SBM1040-13_POWERMITE3
12
3
PD22
RB751V_SOD323
12
PD1
RB751V_SOD323
12
PC
110
0P_0
603_
50V8
G
12
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
EC_SMCAEC_SMDATS_A
N1CHGRTCP
N3
N2
EC_SMC_1 <46,47>
BATT_TEMPA <46>
EC_SMD_1 <46,47>
EC_PWR_ON#<45>
MAINPWON <7,50,53>
H_PROCHOT# <5,26>ADP_I<46,52>
BATT+
VMB
+3VALWP
+5VALWP
RTCVREF
DC_IN
CHGRTC
BATT+
B+
VSVS
VL
VL
VREF
VREF
VS
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
BATTERY CONN / OTP
51 66,星期四 07, 2003八月
Compal Electronics, Inc.
PH2 near main Battery CONN :
Recovery at 45 degree CBAT. thermal protection at 84 degree C
3.3V
PD3@BAS40-04_SOT23
@
1
3
2
PC151000P_0603_50V7K
12
PR41
200_0603_5%
12
PR42100K_0402_1%
12
PR31
47_1206_5%
12
PR17
1M_0603_1%
1 2
PQ2TP0610T_SOT23
13
2
PR27
1.5K_1206_5%
1 2
PC22
1U_0805_50V4Z
12
PR38
100K_0603_5%
12
PL2CHT_C8BBPH853025_13A
1 2
PR3616.9K_0603_1%1 2
PU2A
LM393M_SO8
+3
-2 O 1
P8
G4
PC111000P_0603_50V7K
12
PR193
73.2K_0603_1%
1 2
G
D
S
PQ12N7002_SOT23
2
13
PR39
22K_0603_5%
1 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY O
PC180.1U_0805_25V7M
12
PD10
RLZ16B_LL34 2
1
PR40
150K_0402_1%
12
PC17
0.22U_1206_25V7M
12
PR261K_0603_5%
12
PD9
RLZ4.3B_LL34
12
PC
200.
22U
_080
5_16
V7K
_V2
12
PD4@BAS40-04_SOT23
@
1
3 2
PR25
100K_0603_1%
12
PR230
200_0603_5%
1 2
PR29
1.5K_1206_5%
1 2
PR43
200_0603_5%
1 2
PR2147K_0603_1%
12
PC130.1U_0603_50V4Z
12
PCN2
SUYIN_200275MR009G130ZL
BATT+ 1
TS 3SMD 4
GND 7
BATT+ 2
SMC 5GND 6
PR302.15K_0603_1%
12
PR28
1.5K_1206_5%
1 2
PD8
RB751V_SOD323
12
PC970.01U_0603_50V4Z
12
PD6
1N4148_SOD80
12
PU2B
LM393M_SO8
+5
-6 O 7
P8
G4
PR24
25.5K_0603_1%
1 2
PR3247K_0402_1%1 2
PH
110
K_T
H11
-3H
103F
T_06
03_1
%
12
PR19
100_0603_5%
12
PR23200K_0603_1%
1 2
PC2310U_1206_10V4Z
12
PR18100_0603_5%
12
PD7
1N4148_SOD80 1
2
PU3S-81233SGUP-T1_SOT89
2 2
11
33
PC120.01U_0603_50V4Z
12
PC141000P_0603_50V7K
12
PD5@BAS40-04_SOT23
@
1
32
PC
2110
00P
_040
2_50
V7K
1
2
PR22
11.5K_0603_1%
1 2
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
CHGSS
N18
LXCHRG
DCSRD
ACOFF#
PACIN
ACOFF#
CHGSS
ACOFF <46>
IREF<46>
BATT_OVP<46>
FSTCHG<46>
ADP_I<46,51>
PACIN<50>
DCSRD
<50>
DC_IN
BATT+
P3B+ B++
VMB +3VALWP
VL
VREF
DC_INP2
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
CHARGER
52 66,星期四 07, 2003八月
Compal Electronics, Inc.
Iadp=0~6A
CC=0.5~3ACV=16.8V(12 CELLS LI-ION)
IREF=0.73~3.3VIREF=1.1*Icharge
4.2V
OVP voltage : LI
(BAT_OVP=0.1111 *VMB)
4S3P : 18V--> BATT_OVP= 2.0V
3S4P/3S3P : 13.5V--> BATT_OVP= 1.5V
PIR POWER 92.08.04
PL4
15U_SPC-1204P-150_4A_20%
1 2
PR70499K_0603_1%
12
PR44
0.01_2512_1%
12
PR59
1K_0603_1%
1 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY O
PU5A
LM358A_SO8
+ 3
- 201
P8
G4
PR67
143K_0603_0.1%
12
PR57
1K_0603_1%
1 2
PC24
4.7U_1210_25V6K
12
PR69340K_0603_1%
12
PR48
47K_0603_5%
1 2
PC36
1500P_0603_50V7K
1 2
PQ5
AOS4407_SO8
S1S2S3G4
D 8D 7D 6D 5
PR72
105K_0603_0.5%
12
PR56
10K_0603_1%
12
PC37
0.1U_0805_25V7M
1 2
PR
195
47K
_040
2_5%
12
10K
47KPQ48
DTA144YKA_SC70
2
13
PD14
SKS30-04AT_TSMA 21
PC34
0.1U_0603_50V4Z
1 2
PC42
0.1U_0603_16V4Z
12
PQ49DTC115EUA_SC70
2
13
PC30 2200P_0603_50V7K
1 2
PR64
174K_0603_1%
1 2
PC25
4.7U_1210_25V6K
12
PC28
2200
P_0
402_
50V
7K
12
PD30
1SS355_SOD323
12
PC38
1500P_0603_50V7K
1 2
G
D
S
PQ10
2N7002_SOT23
2
13
PR51
10K_0603_5%
12
PC26
@4.7U_1210_25V6K@
12
G
D
S
PQ50
2N7002_SOT23
2
13
PR240
1K_0
603_
1%
12
PC40
4.7U
_121
0_25
V6K
12
PC39
4.7U
_121
0_25
V6K
12
PD13
1SS355_SOD323
1 2
PC31
0.1U_0805_25V7M
1 2
PR47
200K
_060
3_5%
12
PR65
100K_0603_1%
12
PR61
0.02_2512_1%
1 2
PC33
4700P_0603_50V7K
1 2
PU4
MB3887_SSOP24
-INC21
OUTC22
+INE23
-INE24
+INC2 24
GND 23
CS 22
VCC(o) 21
FB25
VREF6
FB17
-INE18
+INE19
OUTC110
OUTD11
-INC112
OUT 20
VH 19
VCC 18
RT 17
-INE3 16
FB3 15
CTL 14
+INC1 13
PC41
4.7U
_121
0_25
V6K
12
PR58
3K_0603_5%
1 2
PR53
150K_0603_5%
12
100K
100K PQ8
DTC115EKA_SOT23
2
13
PR63
47K_0603_1%
1 2
PC450.01U_0603_50V4Z
12
PR60
68K_0603_5%
1 2
PQ3
AOS4407_SO8
S 1S 2S 3G 4
D8D7D6D5
100K
100K
PQ11
DTC115EKA_SOT23
2
13
PR68
47K_0603_5%
12
PR66
47.5K_0603_0.1%
12
PC
98
0.1U
_060
3_25
V4K
12
PQ4
AOS4407_SO8
S1S2S3G4
D 8D 7D 6D 5
G
D
S
PQ9
2N7002_SOT23
2
13
PC32
0.1U
_060
3_16
V4Z
12
PR62
10K_0603_1%
12
PR54
31.6K_0603_1%
12
PQ6
SI4835DY_SO8
365 7 8
2
4
1
PC430.1U_0603_50V4Z
12
PC350.1U_0603_16V4Z
12
PR50
0_0603_5%
12PR52
47K_0603_1%
12
PC29
0.47
U_0
805_
25V
4Z
12
PL3
HCB4532K-800T90_1812
1 2
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
DH
3
BST51
LX3
FLYBACKSNB
DH31
DH51DH5
DL3
BST31
LX5
DL5
ACIN
ACIN<27,46,50>
MAINPWON <7,50,51>
VS
VL
B++++
B++++
VL
+12VALWP
B+
+3VALWP
VS
2.5VREF
VL
+5VALWP
Title
Size Document Number Rev
Date: Sheet o f
0.7
5V/3.3V/12V
Compal Electronics, Inc.
53 66,星期四 07, 2003八月
+3.3V Ipeak = 6.66A ~ 10A
+5V Ipeak = 6.66A ~ 10A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTYOF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT ASAUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NORTHE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
INC.
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
PIR POWER 92.08.04
PIR POWER 92.08.04
+ PC76
150U
_D_6
.3V
M
1
2
PR770_0402_5%
12
PR8910K_0402_1%
1 2
PQ13SI4800DY
365 7 8
2
4
1
PD19
1SS355_SOD323 12
PL5HCB4532K-800T90_1812
12
PC48
0.1U_0805_25V7K_V2
1 2
PC71
100P_0402_50V8K
12
PL6
10UH_SPC-1204P-100_4.5A_20%
12
PR850_0402_5%
1 2
PR94@0_0402_5%
1 2
PC801U_0603_16V6K
12
PC56
2200P_0402_25V
7K
12
PD17
EP10QY03 2
1
PR242620_0402_5%
1 2
PR950_0402_5%
1 2
G
D
S
PQ51
2N7002_SOT23
2
13
EC11FS2
PD15
12
PR78
1.54k_0603_1%
12
PR790_0402_5%
12
PC50
2200P_0402_25V
7K
12
PR2411.27k_0603_1%
12
PQ15SI4810DY_SO8
S1
S2
S3
G4
D8
D7
D6
D5
PC53
0.1U_0805_25V7K_V1
1 2PC
51
4.7U
_121
0_25
V6K
12
PR101
100K_0603_1%
12
PC75100P_0402_25V8K
12
PC63
47P
_040
2_25
V8K
12
PR800_0402_5%
1 2
PC600.1U_0805_25V7K_V2
12
PR91
3.32K_0603_1%
12
PC
52
@4.
7U_1
210_
25V
6K
12 PR74
0_0402_5%
1 2
PQ14SI4810DY_SO8
S1
S2
S3
G4
D8
D7
D6
D5
PC464.7U_1210_25V6K
1 2
PR750_0402_5%
12
+PC70
150U
_D_6
.3V
M
1
2
PC67
0.47U_0603_10V6K
12
PC
58
4.7U
_121
0_25
V6K
12
PR243698_0402_1%
12
PR811.27k_0603_1%
1 2
PC61
4.7U
_121
0_25
V6K
12
PR9947K_0402_1%
12
PC79@0.047U_0603_16V7K
12
PR92300K_0402_5%
12
PD18
EP10QY03 2
1
PR9710K_0402_1%
12
PC68
0.47U_0603_10V6K
12
PC724.7U_1206_25V6K
12
+
PC74
@15
0U_D
_6.3
VM
1
2
PC47470P_0805_100V7K
12
PQ12SI4800DY
36 578
2
4
1
PC54
4.7U
_120
6_10
V6K
12
PR96
10.2K_0402_1%
12
PT1
9U_SDT-1204P-100-132A_5A_30%
14
32
PR831M_0402_5%
12
PC
57
4.7U
_121
0_25
V6K
12
PR100
10K_0402_1%
12
PC73680P_0402_50V7K
12
PU6
MAX1632_SSOP28
LX326DL324
BST325
DH327
CSH31CSL32FB33SKIP#10
GN
D8
12OUT 4VDD 5
BST5 18DH5 16LX5 17DL5 19
PGND 20CSH5 14CSL5 13
FB5 12SEQ 15REF 9
SYNC 6RST# 11SHDN#23
TIME/ON57
RUN/ON328
VL
21
V+
22
PR822M_0402_1%
12
PC6547P_0402_25V8K
12
PR7322_1206_5%
12
PD16DAP202U_SOT323 1
2 3
PR
239
2.7K
_120
6_5%
12
+
PC69
@15
0U_D
_6.3
VM
@
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCC_MAX1845
B+
+5VALWP
+1.5VSP +2.5VALWP
+3VALW
+2.5VALW
+VCCVID
+2.5VALWP
+12VALW
+5VALW
+1.25VS
+5VALWP
+VCCVIDP
+12VALWP
+1.25VSP
+3VALWP
+1.8VS+1.8VSP
+5VALWP
+5VALWP
Title
Size Document Number Rev
Date: Sheet o f
0.7
DDR POWER 2.5V & 1.5V
Compal Electronics, Inc.
54 66, 07, 2003星期四 八月
BMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
(150mA,40mils ,Via NO.= 2)
(120mA,20mils ,Via NO.= 1)
(2A,80mils ,Via NO.= 4)(6A,240mils ,Via NO.= 12)
(6A,240mils ,Via NO.= 12)
(8A,480mils ,Via NO.=24)
(1.5A,120mils ,Via NO.= 6)
L The related parts will be placed close to power PU7.11
PIR POWER 92.04.16
PIR POWER 92.04.16
+
PC93220U_D2_6.3VM
1
2
PC
8522
00P_
0402
_50V
7K
12
PR
117
100K
_060
3_1%
12
PJP6
PAD-OPEN 2x2m
2 1
PR116100K_0603_1%
12
PL9
4.7U_SPC-1204P-4R7
1 2
PR11416.9K_0603_0.1%
12
PL7
FBM-L11-322513-151LMAT_1210
12
PC812200P_0402_50V7K
12
PQ19SI4810DY_SO8
S1
S2
S3
G4
D8
D7
D6
D5PR108
0_0603_5%
1 2
PC844.7U_1210_25V6K
12
PU7
MAX1845EEI_QSOP28
OUT2 15
BST2 19
FB2 14
CS2 16
VDD 21
UVP
9
SKIP
6
V+4
GN
D23
ON111
DH126
LX127
ILIM2 13
DL124
VCC
22
PGOOD 7
FB12 ON2 12
ILIM1 3
OVP
8
REF
10
LX2 17DL2 20
TON 5
CS128
BST125
DH2 18
OUT11
PC
944.
7U_0
805_
6.3V
6K
12
PC920.1U_0805_50V7M
12
PC834.7U_1210_25V6K
12
PR1030_0603_5%
12
PC
91
1U_0
805_
16V7
K
12
PD
21E
P10
QY
03
21
PJP4
PAD-OPEN 3x3m
1 2
PR104
20_0603_1%
12
PR1070_0603_5%
1 2
PD
23E
P10
QY
03
21
PQ17SI4800DY_SO8
365 7 8
2
4
1
PR1060_0603_5%
1 2
PQ16
SI4800DY_SO8
36 578
2
4
1
PR1020_0603_5%
12
PJP3
PAD-OPEN 4x4m
1 2
PC
99
0.22
U_0
603_
16V7
K
12
PJP16PAD-OPEN 4x4m1 2
PR236
0_0603_5%12
PJP2PAD-OPEN 4x4m1 2
PJP10
PAD-OPEN 3x3m
1 2
PC
900.
1U_0
805_
50V7
M
12
PJP8
PAD-OPEN 2x2m
2 1
PC
964.
7U_0
805_
6.3V
6K
12
PR1050_0603_5%
1 2PC89
0.1U_0805_50V7M
12
PQ18SI4810DY_SO8
S1
S2
S3
G4
D8
D7
D6
D5
PD20DAP202U_SOT323
1
23
+PC
9522
0U_D
2_6.
3VM
1
2
PR115127K_0603_1%
12
PJP1PAD-OPEN 4x4m1 2
PC884.7U_0805_10V4Z
12
PL8
4.7U_SPC-1204P-4R7
12
PJP5
PAD-OPEN 4x4m
1 2
PC
874.
7U_1
210_
25V6
K
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SUSP <48,49>
VR_ON<46>
VID_PWRGD<5,56>
+1.2VS_VGA
+5VS_1.2V
+2.5VS +1.8VSP
2.5VREF
+VCCVIDP+3VALWP
+1.25VREF
+2.5VS
+2.5VS
+1.25VSP
VL
+5VS_1.2V+5VS
Title
Size Document Number Rev
Date: Sheet o f0.7
1.2V/1.8V/VCCVID/1.25VCompal Electronics, Inc.
55 66, 07, 2003星期四 八月BDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(1.25V)
PIR POWER 92.04.16
PR124//PR202 = 5.11K_0603_1%M9+
M10
VGA_CORE
1.5V
PR124 = 9.09K_0603_1%1.2V
PR1293.9K_0603_1%
1 2
PR
125
5.1K_0402_5%
12
PR121
180K_0603_5%
12
PR127
5.1K_0402_5%
1 2
PU8
MAX1954
COMP/SHDN#2 PGND 7
HSD
1
BST 10
LX 9
DH 8
FB 3
GN
D4
IN5
DL 6
PC111560P_0402_50V7K
12
PU27
MIC5258_SOT23-5
PG4
OUT 5
EN3
VIN1
GND 2
PC110
68P_0402_50V8J1 2
PC1781U_0603_10V6K
12C
BE
PQ242SC4672_SOT89
2
1
3
+ PC
104
@22
0U_D
_2VM
1
2
PU5BLM358A_SO8
+ 5
- 607
PR20211.5K_0603_1%
12
PL10
2.2UH_1205P_2R2B_13A
1 2
PR130
10K_0603_0.1%
12
PC1770.1U_0402_10V6K
12
PC1724.7U_0805_10V4Z
12
PD24
1SS355_SOD323
12
PC102
10U_0805_6.3V4Z
12
PC106
470P_0402_50V7K_A34
12
PR218100K_0402_1%
12
+ PC
103
220U
_D_2
VM
1
2
PU16
NE57814
VD4
RefOut8 VttSense 2
VTT 3VSS1
ExtRefIn 6
VDD 5STANDBY/7
PQ21
SI4800DY_SO8
365 7 8
2
4
1
PR1224.53K_0603_1%
12
PC1714.7U_0805_10V4Z
12
PR123
0_0603_5%
12
PC179
0.1U_0402_16V4Z
12
PR1190_0603_5%
1 2
PC107
33P_0402_50V8J
12
G
D
S
PQ25
2N7002_SOT23
2
13
PC1010.1U_0603_10V6K
12
+
PC
173
150U
_D2_
6.3V
M 1
2
PR126100_0603_5%
12
PJP15
PAD-OPEN 4x4m
1 2
PR
124
9.09
K_06
03_1
%
12
PR2350_0603_5%
12
PQ23 SI4810D
Y_S
O8
365 7 8
2
4
1
PC1740.1U_0402_10V6K
12
PC17610U_1206_10V4Z
12
PR128
15_0603_5%
12
PC
112
0.01U_0402_25V7K
12
PC10022U_1210_6.3V6M
12
PC1750.1U_0402_10V6K
12
+PC184
22U_1210_10v
1
2
PR2170_0603_5%
12
CM-
CM+
BSTM
CORE_REF
BSTM
OAIN-
OAIN+
OAIN+
FB
OAIN-
FB
OAIN+
OAIN+
OAIN+
OAIN-
FB
SKIP#
CORE_REF
VID5<5>
VID4<5>
VID3<5>
VID1<5>
VID2<5>
VID0<5>
VCCSENSE<5>
CORE_REF<57>
VID_PWRGD<5,55>
DLM<57>
CM+ <57>CM- <57>
DLS<57>
VSSSENSE<5>
VCORE_PWRGD<48>
CPUCLK_STP# <5,11,26>
CORE_REF <57>
H_BOOTSELECT<4>
CS- <4,5,6,7,8,26,57>
CS+ <57>
DPRSLPVR<26>
SKIP# <57>
VCCSENSE <5>
+CPU_B+
B+
+CPU_B+
+VCC_CORE
+VCC_CORE
+5VS_CORE
+VCCVID
+5VS_CORE
+5VS +5VS_CORE
+5VS_CORE
+VCC_CORE
+5VS_CORE
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 0.7
CPU_CORE(1)
A3
56 66,星期四 07, 2003八月
(120mA,20mils ,Via NO.= 1)
PIR POWER 92.04.16
PIR POWER 92.04.16
PIR POWER 92.04.18
H_BOOTSELECT=1
H_BOOTSELECT=0
PRESCOTT
NORTHWOOD
1. When mode control signal ishigh/ low, the VR will operate toNorthwood/ Prescott load line. 2. VID5(12.5) should be pulledhigh, when the VR operates toNothwood load line.
PIR POWER 92.08.04
EC31QS04
PD27
12
PR150_0402_5%
12
PR1621K_0603_1%
12
PC1821000P_0402_50V7K
12
PQ26
MM
BT39
04_S
OT2
3
C1
E3
B2
PR1450.0015_2512_1%
1 2
PC
134
2200
P_0
402_
50V
7K
12
PR140100K_0402_1%
12
PC
135
0.1U
_080
5_25
V7K
12
PR135100K_0402_5%
12
PR2250_0402_5%
1 2
PL11FBM-L18-453215-900LMA90T_1812
12
G
D
S
PQ202N7002_SOT23
2
13
PC139
0.022U_0603_50V
4Z
12
PR164499_0402_1%
12
PC1294700P_0402_25V7K
12
PC1150.1U_0402_10V6K
1 2
PC
132
10U
_121
0_25
V6K
12
PL120.7U_ETQP2H0R7BFL_31A_20%
12
PR2210_0402_5%
1 2
PR244
0_0402_5%
1 2
G
D S
PQ43
2N7002_SOT23
2
1 3
PR159100K_0402_1%
1 2
PR144
47K _0402_1%
12
PQ45
2N70
02_S
OT2
3
D1
S3
G2
+PC130
100U_25V_M
1
2
PR136100K_0402_5%
12
PC138
100P_0603_50V
8G
12
PD28
CH
P202U
_SC
70
1
32
PR1700_0402_5%
12 PQ31IR
F7832_SO
8
365 7 8
2
4
1
PR143
0_0603_5%
1 2
EC31QS04
PD29
12
PR173
1k_0603_1%
1 2
G
D
S
PQ402N7002_SOT23
2
13
PJP14
PAD-OPEN 2x2m
2 1
PR141
0_0402_5%
1 2
PR110
5.1_0402_1%
12
PR153499_0402_1%
12
PQ29
IRF7832_SO8
365 7 8
2
4
1
PR1660_0402_5%
1 2
PR171
1k_0603_1%
1 2
PC142100P_0603_50V8G
12
PR2230_0402_5%
1 2
PC1280.1U_0402_10V6K
12
PC136470P_0402_50V8J
12
PC
116
10U
_121
0_25
V6K
12
PQ30SI7392DP_SO8
3 2
4
1
5
PR160
20K_0402_5%
1 2
PR2240_0402_5%
1 2
PR11133_0402_1%
1 2
PC140
100P_0603_50V
8G
12
PR167
100K_0402_5%
12
PR154100K_0402_1%
1 2
PR1560_0402_5%
1 2
PC180
100P_0402_50V8K
12
PC
120
0.1U
_080
5_25
V7K
12
PQ44
2N70
02_S
OT2
3
D1
S3
G2
PR
180
2.7K_0603_1%
12
PC
117
10U
_121
0_25
V6K
12 P
C11
922
00P
_040
2_50
V7K
12
PQ32IRF7832_S
O8
365 7 8
2
4
1
PC124
0.47U_1206_16V7K
1 2
PQ28
IRF7832_S
O8
365 7 8
2
4
1
PR1570_0402_5%
1 2
PR1630_0402_5%
1 2
PC
131
10U
_121
0_25
V6K
12
PR132
0_0402_5%
1 2
EC31QS04
PD26
12
G
D
SPQ33
2N7002_SOT23
2
13
PR246
0_0402_5%
1 2
PC141
0.47U_1206_16V7K
1 2
PR165100K_0402_1%
12
PR
148
0_0402_5%
12
PR13730.1K_0603_1%
1 2
PC
133
10U
_121
0_25
V6K
12
PR1490_0402_5%
12
PR139
0_0402_5%
1 2
PR2220_0402_5%
1 2
PR155
0_0603_5%
1 2
PQ27SI7392DP_SO8
3 2
4
1
5
PU9
MAX1546
TIME1
FB15
VCC10
ILIM9
REF8
SHDN#6
TON2
CCV12
SKIP 18
DHS 33
BSTM 26
DLM 29
SUS 3
LXS 34
LXM 27
BSTS 35
D420
CMP 37
D321
PGND 31
OAIN+17
CSP 40
OAIN-16
CMN 38
OFS7 VROK25
GND11
S1 5
CSN 39
D519
V+ 36
DLS 32
DHM 28
VDD 30
CCI14
D222
D024
D123
S0 4
GNDS13
PC1140.22U_0603_10V7K
12
PR
133
100k
_040
2_5%
12
PR1689.31K_0603_1%
1 2
PC181470P_0402_50V7K_A34
12
PR1461K_0603_1%
12
PC122
270P_0402_50V
7K
12
PL130.7U_ETQP2H0R7BFL_31A_20%
1 2
PR152@1.74K_0402_1%
@
1 2
PC
125
2.2U_0805_10V
6M
12
PR1582.7K_0603_1%
12
PR138
@0_0402_5%1 2
PR227
0_0402_5%
1 2
PR2450_0402_5%
1 2
PR2200_0402_5%
1 2
PC1231U_0603_10V6K
12
PR14710_0603_1%
1 2
PR161
150K_0402_1%
1 2
PR109@100K_0402_1%
1 2
PC
126
1000
P_0
402_
50V
7K
12
PC
118
10U
_121
0_25
V6K
12
SKIP#
CS- <4,5,6,7,8,26,56>
CS+ <56>
CORE_REF6>
CM- <56>
CM+ <56>
DLM<56>
SKIP# <56>
DLS<56>
+VCC_CORE
+CPU_B+
+CPU_B+
+VCC_CORE
+VCC_CORE
+VCC_CORE
+5VS_CORE
+5VS_CORE
Title
Size Document Number Rev
Date: Sheet o f
0.7
+CPU_CORE(2)
Compal Electronics, Inc.
57 66,星期四 07, 2003八月
PQ
35
IRF7
832_
SO
8
S1
S3
G4
D8
D7
D6
D5
S2
PC
145
10U
_121
0_25
V6K
12
PC1532200P_0402_50V7K
1 2PR18320K_0603_1%
1 2
PC
160
10U
_121
0_25
V6K
12
PC168
1000P_0603_16V7K
12
PC
158
2.2U
_080
5_10
V4Z
12
PC
148
2200
P_0
402_
25V
7K
12
PR196
0_0603_5%
1 2
PR1880_0603_5%
12
PQ
39
IRF7
832_
SO
8
S1
S3
G4
D8
D7
D6
D5
S2
PU11
MAX1980
VDD11
LIMIT18
VCC12
POL7
TON3
COMP6
DD
/13
ILIM19
GND8
V+ 17
BST 16
DH 14
LX 15
DL 10
PGND 9
CS+ 5
CS- 4
CM+ 1
CM- 2
TRIG
20
PR19810_0603_1%
12
PR1780_0603_5%
1 2
PC162
2200
P_0
402_
25V
7K
12
PC1672200P_0402_50V7K
1 2
PR
204
1K_0
603_
1%
12
PC
161
10U
_121
0_25
V6K
12
PR17610_0603_1%
12
PC166
0.47U_1206_16V7K
1 2
PD41
@1SS355_SOD3231 2
PC1500.22U_0603_16V7K
12
PR184
200K_0603_1%
12 PC155
1000P_0603_16V7K
12
PU10
MAX1980
VDD11
LIMIT18
VCC12
POL7
TON3
COMP6
DD
/13
ILIM19
GND8
V+ 17
BST 16
DH 14
LX 15
DL 10
PGND 9
CS+ 5
CS- 4
CM+ 1
CM- 2
TRIG
20
PC169
1000P_0603_16V7K
12
PR2010_0603_5%
1 2
PD33
1SS355_SOD323
12
PC170
100P_0603_50V8J
12
PC
149
2.2U
_080
5_10
V4Z
12
PR21049.9K_0603_1%
12
PC
147
10U
_121
0_25
V6K
12
PR174
0_0603_5%
1 2
PQ34SI7392DP_SO8
3 2
4
1
5
PR
181
1K_0
603_
1%
12
PR1770_0603_5%
1 2
PC
144
0.1U
_080
5_25
V7K
12
PC
159
10U
_121
0_25
V6K
12
PC165
0.22
U_0
603_
16V
7K
12
PL14
0.7U_ETQP2H0R7BFL_31A_20%
1 2
PR200
0_0603_5%
1 2
PR20620K_0603_1%
1 2
PR1870_0603_5%
12
PQ
38
IRF7
832_
SO
8
S1
S3
G4
D8
D7
D6
D5
S2
PC154
1000P_0603_16V7K
12
PQ
36
IRF7
832_
SO
8
S1
S3
G4
D8
D7
D6
D5
S2
PC152
0.47U_1206_16V7K
1 2
PD39
1SS355_SOD323
12
PC164
0.22U_0603_16V7K
12
PC
146
10U
_121
0_25
V6K
12
PC1630.1U_0805_25V7K_V2
12
PC1510.22U_0603_16V7K
12
PL15
0.7U_ETQP2H0R7BFL_31A_20%
12
PR18949.9K _0402_1%
12
PR1990_0603_5%
1 2
PC
156
100P
_060
3_50
V8J
12
PD35
@1SS355_SOD3231 2
PQ37SI7392DP_SO8
3 2
4
1
5
EC31QS04PD36
12
PR172
0_0603_5%
1 2
PR207
200K_0603_1%
12
EC31QS04PD42
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet o fLA-1811 0.7
58 66, 07, 2003星期四 八月
Compal Electronics, Inc.
Changed-List History-1
Version Change List ( P. I. R. List ) for Power Circuit
Item Issue DescriptionDateRequestOwner Solution Description Rev.Page#
1 0.2
0.2
Title
2
3
change to correct layout pad on PU7, PU8, PU9, PU10, PU11, PU16 and PQ24
54,55, 56,57 03/25/2003 Compal
DPRSLPVR56 03/25/2003Reserve two resistors for voltage of Deep-sleeper mode Reserver PR231, PR232, PR233, PR234
for deeper-sleeper mode voltage setting
03/25/2003 Reserve a jumper for power consumption measurement56 CPU VR-Cont.
4
Add PJP14
57 Compal Change Netname of +5VS_CORE
5 51 RTC charger Add PR230
wrong layout pad
wrong layout pad
Compal
Compal
CPU VR-Cont. 03/25/2003 Change the netname +5VS_CORE for powerconsumption measurement
03/25/2003 Compal use two resistors for RTC charger protection
0.2
0.2
0.2
6 re-located both PL10 and PQ21, PQ23 as well as 1.2VS_VGA related power circitry
55 1.2VS_VGA 03/25/2003 Compal re-layout 1.2V_VGA requested by ME
7 55 1.2VS_VGA 03/26/2003 Compal Reserve a jumper for power consumption measurement Add PJP15
0.2
0.2
8 55 +1.25VSP 03/26/2003 Compal Change power time-sequence of 1.25VSP input power Change VD, and VDD of PU16 from +2.5VALWPto +2.5VS; Connect PR235.2 to +2.5VSadd a resistor PR235 for Stand/By pin for test
0.2
9 03/27/2003 Compal Add PR237, PR238 for force PWM function control, and add PR236 for SUSP# signal
54 +1.5VALWP Reserve Force PWM function of 1.5V/2.5V and add a PR236 for SUSP# signal 0.2
1
1
2
2
3
3
4
4
5
5
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet o fLA-1811 0.7
H/W2 EE Dept. PIR SHEET(1)
59 66, 07, 2003星期四 八月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
----PLEASE SEE NEXT PAGE
BHR60 from DB-1 to DB-2 STEP LA-1811 REV:0.1 -> 0.2 Modify <92.03.17.~92.03.24. >
-Add U53(SI9185),C913,R1023,C912,C914 and related net . (Modify CKT,BOM&Layout)1.Add an independent power source for VGA chip because of ATI request . <Page 12> 92.03.17.
-Add U54(NEC_uPD720101F1-EA8),R1024~R1047,R1049,R1051,R1053,R1054,C915~C929,U55(AT24C02),RP147,RP148,R102,R1059,R1062;Del RP127 . (Modify CKT,BOM&Layout)
3.Change the USB2.0 Controller chip from ATI to NEC and modify the net for Customer request . <Page 26,27,36,44> 92.03.18.
-Add R1063(39K_0603_1%);Del R768(0_1206_5%) . (Modify CKT,BOM&Layout)4.Modify the Audio related schematic for Customer request . <Page 37,38> 92.03.20.
-Change C894,C896 from 1U_0603_10V6K to 0.1U_0603_16V7K . (Modify CKT&BOM)-Change R974 from @100K_0402_5% to 100K_0402_5% . (Modify CKT&BOM)
-Add R1048,R1050,R1052 . (Modify CKT&Layout)
2.Modify the Audio related schematic for Customer request . <Page 37> 92.03.17.-Add Q101(2N7002);Del R948(2.2K_0402_5%);Modify R746(2.2K_0402_5%) . (Modify CKT,BOM&Layout)
-Change JP41.3 from GNDA to +5VAMP. (Modify CKT&Layout)
15.Modify the schematic after rev0.1 debug by Brian . <Page 12,17,26,29> 92.03.24.
-Add R1071,R1075,R1090,R1091(ATI@0_0402_5%) . (Modify CKT&Layout)
-Add RP149(@0_0404_4P2R_5%) . (Modify CKT&Layout)9. Add the power source +5V and +1.5VS discharge circuit for ATI request . <Page 49> 92.03.23.
-Add C937~C946,C862,C863,C865~C871(0.1U_0402_10V6K) . (Modify CKT,BOM&Layout)
-Add R1094,R1095(470_0402_5%),Q102,Q103(2N7002 1N_SOT23) . (Modify CKT,BOM&Layout)
6.Modify the USB2.0 related for Compal ATI/NEC Dual Layout request . <Page 27,44> 92.03.21.
5.Modify the MiniPCI and BlueTooth conn related schematic for Customer request . <Page 43,44> 92.03.21.-Add R1083,R1084,R1085(@0_0402_5%) . (Modify CKT&Layout)-Change R300 from 100_0402_5% to @100_0402_5% . (Modify CKT&BOM)
-Change R976,R977,R978,R979,R982,R983 from 0_0402_5% to ATI@0_0402_5% and the net . (Modify CKT,BOM&Layout)
-Change R1083,R1084 from @0_0402_5% to 100_0402_5% . (Modify CKT&BOM)-Add C957(10U_0805_10V3M),C958(0.1U_0402_10V6K) . (Modify CKT,BOM&Layout)
12. Del Via Hole on schematic for ME modify . <Page 41> 92.03.24.-Del H15(H_C374D295),H29(H_C197D91) . (Modify CKT,BOM&Layout)
7.Add De-coupling capacitor for AGP power pins on RC300M and VGA chip because of ATI request . <Page 10> 92.03.21.
10. Modify the ON1 related to speed up the power sequence for ATI request . <Page 48,54> 92.03.23.
8. Reserve the SMBus1/2 swap Resistors for ATI request . <Page 27> 92.03.23.-Add RP150(0_0404_4P2R_5%) . (Modify CKT,BOM&Layout)
-Add R1069,R1070,R1072,R1073,R1074,R1076,R1077,R1078,R1092,R1093(NEC@0_0402_5%) . (Modify CKT,BOM&Layout)
-Change C347,C360 from 0.1U_0402_10V6K to 3900P_0402_50V7K;C356,C348 from 0.01U_0402_16V7K to 2200P_0402_25V7K . (Modify CKT&BOM)
14.Swap the USB20*P3* and USB20*P5* for Customer request . <Page 44> 92.03.24.-Modify R1079~R1082,JP43,R980,R981's connection . (Modify CKT&Layout)
13.Modify the MiniPCI and BlueTooth conn related for Customer request . <Page 43,44> 92.03.24.
-Add C956(180P_0603_50V8J) . (Modify CKT,BOM&Layout)
A-TEST SMT BUILT
-Change R1010 from @0_0603_5% to 0_0603_5%;R1011 from 0_0603_5% to @0_0603_5%;Q15 from 2SC2411K_SOT23 to @2SC2411K_SOT23;R145 from 4.7K_0402_5% to @4.7K_0402_5%;R146 from @4.7K_0402_5% to 4.7K_0402_5%;R967 from @10K_0402_5% to 10K_0402_5%;R833 from @0_0402_5% to 0_0402_5% . (Modify CKT&BOM)
-Add R1096,R1097(10K_0402_5%),Q1043(2N7002 1N_SOT23),Q105(DTC124EK_SC59);Del PR113(47K),PC183(0.1U) . (Modify CKT,BOM&Layout)
11. Modify power source CAP.'s value by Brian . <Page 26,49> 92.03.24.
-Change R972 from 100K_0402_5% to @100K_0402_5% . (Modify CKT&BOM)
16.Modify the schematic H_BOOTSELECT related by Power Team . <Page 04> 92.03.25.-Add Q106(2SC2411K_SC59),Q107(MMBT3904_SOT23),R1099,R1100(47K_0402_5%) . (Modify CKT,BOM&Layout)-Change R899 from 0_0402_5% to 22K_0402_5%,R900 from @0_0402_5% to 100K_0402_5% . (Modify CKT&BOM)
17.Add a power transfer circuit to fix +1.5VS leakage issue . <Page 49> 92.03.25.-Add U56(SI4800DY_SO8),Q108(2N7002 1N_SOT23),R1101(100K_0402_5%),C960(0.1U_0402_10V6K),C961(10U_1206_6.3V6M),C962(3900P_0402_50V7K) . (Modify CKT,BOM&Layout)
-Change C347,C360,C962 from 3900P_0402_50V7K to 0.1U_0402_10V6K;C356,C348 from 2200P_0402_25V7K to 0.1U_0402_10V6K;C627,C844 from 1000P_0402_50V7K to 0.1U_0402_10V6K . (Modify CKT&BOM)
18. Modify power source Resistor and CAP.'s value for power sequence . <Page 49> 92.03.26.
-Change R903,R362 from 100K_0402_5% to 91K_0402_5% . (Modify CKT&BOM)-Change R902,R363 from 100K_0402_5% to 95.3K_0603_1% . (Modify CKT,BOM&Layout)
19. Modify the ON1 related to speed up the power sequence for ATI request by Brian/James/CT . <Page 48,54> 92.03.26.-Del R1096,R1097(10K_0402_5%),Q1043(2N7002 1N_SOT23),Q105(DTC124EK_SC59) . (Modify CKT,BOM&Layout)
20. Add the power source +3VS discharge circuit by Brian . <Page 49> 92.03.26.-Change Q42 from @2N7002 1N_SOT23 to 2N7002 1N_SOT23 . (Modify CKT&BOM)
21. Change the Resistor's value for ATI recommend . <Page 17 > 92.03.26.-Change R264 from 169_0603_1% to 2N7002 1N_SOT23 . (Modify CKT&BOM)
23. Add the power source +3V discharge circuit for ATI request . <Page 49> 92.03.27.-Add R1102(470_0402_5%),Q109(2N7002 1N_SOT23) . (Modify CKT,BOM&Layout)
22. Correct material layout footprint and pin define . <Page 26,34 > 92.03.26.-Change Y1,Y3 PCB Footprint and JP32 pin define . (Modify CKT&Layout)
24. Change the power sequence related part's power source by Brian . <Page 5,37,48> 92.03.27.-Change U32's power source from +3VS to +3VALW . (Modify CKT&Layout)
25. Modify the power sequence related schematic for timing by Brian . <Page 48> 92.03.27.-Change R605 from 1M_0402_5% to @1M_0402_5%;C606 from 1U_0603_10V6K to @1U_0603_10V6K . (Modify CKT&BOM)-Add Q110(2N7002_SOT23) . (Modify CKT,BOM&Layout)
26. Modify the SPDIF related schematic for Customer request . <Page 37,41> 92.03.28.-Add R1103(0_0402_5%),C963(0.01U_0402_50V7K) . (Modify CKT,BOM&Layout)
27. Modify the NEC USB2.0 Controller Chip related schematic for Customer request . <Page 36> 92.03.28.-Add Y7(30MHZ_30PPM),R1105(100_0402_5%),C964(12P_0402_50V8J),C965(10P_0402_50V8K) . (Modify CKT,BOM&Layout)-Add R1104(@0_0402_5%) . (Modify CKT&Layout)-Change R1024 from 0_0402_5% to @0_0402_5% . (Modify CKT&BOM)
28. Update the material's Layout Footprint for error correction . <Page 36> 92.03.28.-Update JP29,JP14,SW1,SW3~SW8,JP40,Q65 . (Modify CKT&Layout)
29. Modify the related schematic after Brian Review <Page 7,24,26,29,30,39,43,45> 92.03.31.-Del R288(56_0402_5%) . (Modify CKT,BOM&Layout)
30. Modify the related schematic after Layout check <Page 44> 92.03.31.-Modify JP16(RJ11 Conn.).5 and JP16.6 from GND to NC . (Modify CKT&Layout)
31. Update the material's Layout Footprint for error correction . <Page 41> 92.04.02.-Update JP40 . (Modify CKT&Layout)
32. Modify the schematic for cost down . <Page 10,12,26,37,> 92.04.04.-Change to @(R1005,D79~D82,U53,C912,C913,R1023,Q98,R769,R771,) . (Modify CKT&BOM)
1
1
2
2
3
3
4
4
5
5
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet o fLA-1811 0.7
H/W2 EE Dept. PIR SHEET(2)
60 66, 07, 2003星期四 八月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
----PLEASE SEE NEXT PAGE
BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 EE Modify <92.04.08.~92.04.18. >
-Change JP33 sequence JP33.4->JP33.1, JP33.3->JP33.2, JP33.2->JP33.3, JP33.1->JP33.4. (Modify EECircuit)
1.1394 Connector JP33 Pin define sequence error. <Page 35> 92.04.08. 1.FDD Connector JP38 PCB Footprint error. <Page 40> 92.04.09.-Check JP38 ACES_85201-2605_26P. (Modify Layout)
2.Power Switch U53 PCB Footprint error. <Page 12> 92.04.09.-Change U53 SI9185_MLP33-8->MSOP8. (Modify Layout)
3.Crystal Y4 PCB Footprint error. <Page 11> 92.04.09.-Change Y4 Y_TXC_6X1430004201_20P->KDS_DSX840GA. (Modify Layout)
4.USB Key Connector JP46 Part error. <Page 44> 92.04.09.-Change JP46 S W-CONN ACES 85205-0400 4P P1.25(ACES_85205-0400_4P)->S H-CONN ACES85201-0405 4P P1.0(ACES_85201-0405_4P). (Modify Layout)
2.LED Circuit to Power Button(PRES)modify . <Page 42, Page 46> 92.04.09.-Move Q66.1-R883-D56 -> Q62.1-R883-D56(PRES). (Modify EE Circuit)-Rename Q62.2 net PWR_BACK# change to PWR_ACTIVE# connect to EC U15.119. (Modify EE Circuit)
3.Add +1.2VS_VGA Discharge Circuit. <Page 49> 92.04.09.-Add +1.2VS_VGA Discharge Circuit(R1116 , Q115 to SUSP). (Modify EE Circuit)
BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 Layout Modify <92.04.08.~92.04.18. >
4.Add 3VDDCDA & 3VDDCCL pull hing CRT_VCC circuit. <Page 25> 92.04.09.-Add Q13.1-R1117 to +CRT_VCC & Q14.1-R1118 to CRT_VCC. (Modify EE Circuit)
5.PCMCIA U37 NET S1_CE2# & S1_CE1# Sweep. <Page 31> 92.04.09.
6. MDC(JP17) Net AC97_SData_In1/AC97_SData_In2 to AC97_Data_In. <Page 44> 92.04.10.-Update BOM add R326. (Modify EE Circuit)
7. Change NB DDR Bus Net for basic on ATI NB DDR Bus Layout rule. <Page 9, 14, 15, 16> 92.04.11.-Add R1122(DDRA_CKE_R3), R1121(DDRA_CKE_R2). (Modify EE Circuit)-Del R399(DDRA_CS#0), R400(DDRA_CS#2). (Modify EE Circuit)
8. Check BOM USB OUVUR R893&R895 470K change to 330K. <Page 44> 92.04.12.
9. Add SUSP# pull Down. <Page 46> 92.04.14.-Add EC U15.115 to SUSP# pull Down @R1123 to GND. (Modify EE Circuit)
10. Add CPUCLK_STP# pull High Circuit. <Page 26, 5> 92.04.14.-BOM Q113 -> @ , Add R1124 to Q113.1 & Q113.3. (Modify EE Circuit)-Add CPUCLK_STP# pull High @R1126 to +3VS . (Modify EE Circuit)
12. SIO Circuit All Power Plan +3V -> +3VS. <Page 39> 92.04.15.
-Add CPUCLK_STP# serial resistor R1125 to Q96.2. (Modify EE Circuit)
11. Change BOM R585 75 -> 0 & R996 33 -> 68(REFCLK1_NB). <Page 11, 24> 92.04.15.
5. Change BOM & Layout LED D57 Footprint . <Page 42> 92.04.15.-Change D57 HSMG-C170 to LED_12-21SYGC_S530-E1_TR8. (Modify Layout)
13. Add NEC USB Corstralor U54.P19(SRMOD) pull Low. <Page 36> 92.04.16.-Add USB Constralor U54.P19(SRMOD) pull Low R1127 to GND. (Modify EE Circuit)-Update BOM R1046 -> @. (Modify EE Circuit)
6. Change Layout Keyboard Connector JP13 Footprint. <Page 45> 92.04.15.-Change JP13 ACES_85201-2402_24P -> ACES_85201_2405_24P. (Modify Layout)
7. Change Layout FrontSideboard Connector JP42 Footprint. <Page 44> 92.04.15.-Change JP42 ACES_85201-1402_14P -> ACES_85201_1405_14P. (Modify Layout)
16. Change BOM R380 430 -> 412(U27.A9/CPU_RSET#). <Page 8> 92.04.17.
15. Change BOM C364, C23, C24, C40, C798 47U -> 22U. <Page 8,28,41> 92.04.17.
18. Change BOM C191 4.7U -> 2.2U. <Page 17> 92.04.17.
19. Change BOM C202,C931 10U -> 2.2U. <Page 20> 92.04.17.
20. Change BOM R636 100K-> @10K, R637 100K-> @10K, R665 -> @. <Page 33> 92.04.17.
21. Change MC_CD# - D44.3(SA_A25) -> D45.2, D44.2(SA_A22). <Page 33> 92.04.17.
14. Add @R1132 pull High +3V(RTS1#) & @RP153 pull High +3V(CTS1#/DSR1#/DCD1#/RI1#). <Page 39> 92.04.16.
17. Change BOM D57 HSMG-C170 -> 12-21SYGC/S530-E1, R1014 @ -> Del @. <Page 42> 92.04.17.
24. Change BOM Q67 -> @, R884 -> @(CARD_LED#). <Page 42> 92.04.18.
23. Add R1136, Q116, R1137, R1138 for pull High +3VS(CARD_LED#). <Page 42> 92.04.18.
22. Add R1135 -> VTT_PWRGD(U15.165). <Page 46> 92.04.18.
25. Change BOM C966 22U -> 0.1U. <Page 18> 92.04.18.
26. Change BOM C916 -> @, C917 -> @. <Page 36> 92.04.18.
27. Change BOM R1019 -> @(U47.17 JS1) pull High. <Page 37> 92.04.18.
28. Change BOM R264 47 -> 137(U6.PM27 AGPTEST). <Page 17> 92.04.18.
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Title
Size Document Number Rev
Date: Sheet o fLA-1811 0.7
H/W2 EE Dept. PIR SHEET(2)
61 66, 07, 2003星期四 八月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
----PLEASE SEE NEXT PAGE
BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 EE Modify <92.04.08.~92.04.18. >
BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 Layout Modify <92.04.08.~92.04.18. >
35. Add @R1142 pull High(DOCK_LOUT_R). <Page 38> 92.04.21.
32. Change SPR JP40 33,34 DOCKVIN -> GND , JP35,36 GND -> DOCKVIN, . <Page 41> 92.04.21.
36. Add C971 & R1140 for VOLBTN+#, R1141 & C972 for VOLBTN-#, R1131 pull High +5VS, @R1139 pullHigh +3V. <Page 41> 92.04.21.
33. Change BOM Q65 DTC124EK_SC59 -> MMBT3904_SOT23. <Page 41> 92.04.21.
29. Change U13.P1 <-> U13.P5, U14.P1 <-> U14.P5. <Page 43> 92.04.21.
30. Change R994.1 - AGP_DEVSEL# -> AGP_SBA1(DDC_DAT), R995.1 AGP_IRDY# ->AGP_SBA0(DDC_CLK). <Page 10> 92.04.21.
31. Add CLK_14M_APIC Terminte R,C @R1143 10/@C973 15P. <Page 26> 92.04.21.
34. Del @R1104, @R1089, @C953(CLK_SB_48M). <Page 36> 92.04.21.
37. Add R520 @ -> Del @(JP8.AE26 COMPAT#). <Page 5> 92.04.23.
38. Change BOM R539, R540 61.9 -> 51.1 (JP8.L24/P1 COMP0/COMP1). <Page 5> 92.04.23.
39. Change BOM R553 100 -> 49.9, R558 169 -> 100. <Page 5> 92.04.23.
40. Change BOM R383 100 -> 49.9, R384 169 -> 100. <Page 8> 92.04.23.
41. Add R1001 @4.7K -> Del @, 100K pull Low(DPRSLPVR). <Page 26> 92.04.23.
42. Change BOM R40 @ -> Del @, R53 -> @. <Page 29> 92.04.23.
43. Change BOM R792 -> @, R795 @ -> Del @. <Page 39> 92.04.23.
44. Change BOM R230 -> @. <Page 4> 92.04.23.
45. EMI add R1144 for SSOUT. <Page 10> 92.04.24.
46. EMI change D73, D74, D75, D76 part. <Page 38> 92.04.24.
47. Add C974 pull Low for +NB_AGP. <Page 17> 92.04.24.
48. Change BOM R623 10K -> 0. <Page 25> 92.04.28.
49. Change BOM R622, R619 10K ->@. <Page 25> 92.04.28.
BHR60 SI STEP LA-1811 REV:0.4 EE MEN <92.04.28. >
1. Change C781 SE077106M00 -> SE054106Z10. <Page 39> 92.04.28.2. Change C963 -> @. <Page 41> 92.04.28.3. Change C974 -> @. <Page 17> 92.04.28.4. Change C742 -> (SD028000000) 0 Ohm. <Page 37> 92.04.28.5. Add R771 -> (SD028470100) 4.7K Ohm. <Page 37> 92.04.28.6. Add C747 -> (SE070104Z00) 0.1U. <Page 37> 92.04.28.7. DEL R761,R762 <Page 37> 92.04.28.
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Title
Size Document Number Rev
Date: Sheet o fLA-1811 0.7
H/W2 EE Dept. PIR SHEET(2)
62 66, 07, 2003星期四 八月
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
BHR60 from SI-1 to DB(15.4") LA-1811 REV:0.4 -> 0.5 HW PIR <92.05.07.~92.05.30. >
0 .5Add Nets: NMCSA1# and NMCSB1#18, 19,22, 236 Add CS1# for Hynix 8Mx32 VGA DRAM
1 Prevent CPUCLK_STP# abnormal state happened 5 Change R1125 from 4.7K to 12K
26 Delete R1126
29 Change R40 from 10K to 1K
7 Change the power of U8 from +3VS to +3VALW
M.B. Ver.
0 .5
0 .5Prevent power leakage
Power saving 7 Change the power of Fans from +5VALW to +5VS 0 .5
2
3
Reason for change PAGE Modify ListFixed IssueItem
ATI recommendation 8 Add C974 0 .54
Add VGA DRAM size detect function5 1 7 Add R1149 for 128MB VGA DRAM (un-populate for 64MB) 0 .5
7 Change M9+X VGA_CORE from +1.5VS to individual power source 2 1 Delete JOPEN3 0 .5
8 Delete useless components
2 5 Delete C96
0 .5
25 Change R619.1 and R622.1 net from +5VS to CRT_VCC 0 .5Solve power leakage from CRT9
2610 Prevent DPRSLPVR abnormal state happened Change R1001 from 100K to 47K, R1002 from 0 to 47K 0 .5
11 Using rechargeable RTC battery for HP's request Delete D66, D71 and D72; Add D91 (BAS40-04, the same as LA-1761 D30); ChangeBATT1 from CR1220 to ML1220 (the same as LA-1761 BATT1)
0 .52 6
12 Prevent +5V drop while plug SPR for HP's request 4 1 Change JP40.3, C798.1, C800.1 and C801.1 net from +5V to USB_VCCA; Change C798from 22u to @10u; Change C801 from 1000p to @1000p
0 .5
5 Delete R538
13 Enhance brightness of blue LEDs 0 .5Delete Q67, R883, R884, R942 and R943; Add Q117 and R1146; Change R881, R882,R885, R888, R889, R890, R925 and R1136 to 220
42, 45
Change JP42.2 from BATLED_0 to BATLED_0#; Change JP42.7 from N.C. to +5VALW;Change JP42.12 from PAV_GND to PAV_LEDVCC; Change JP42.13 from PMLED_1 toPMLED_1#; Change JP42.14 from PAV_GND to +5VS; Change JP45.7 from PRES_GND toPRES_LEDVCC; Change JP45.8 from PRES_GND to +5VS
44
14 Solve PWR_ACTIVE LED function fail issue 4 2 Change power from +3VS to +5V for PWR_ACTIVE LED (D52 and D56) 0 .5
4 6 Add R1147 and R1148; Change U15.76 net from N.C. to PWR_ACTIVE_PRES#; ChangeU15.87 net from N.C. to PRES_DETECT; Change U15.119 net from PWR_ACTIVE# toPWR_ACTIVE_PAV#
15 Solve M10 can't power up issue 4 9 Change R1101 from 100K to 56K; Change R901 from 91K to 27K 0 .5
16 Add discharge components 4 9 Add R372, R1095, R1102, Q36, Q103 and Q109 0 .5
17 Material change for ME's request 4 4 Change JP47 from ACES_88231_0200 to MOLEX_53398_0290 (the same as LA-1761 JP2) 0 .5
1 8 Using NEC USB2.0 to support BT for HP's request 4 4 Change R1082.2 net from USB3+ to USB5+; Change R1081.2 net from USB3- to USB5- 0 .5
27 Delete Q114, Add R1145
19 Increase MONO_IN voltage level 3 7 Change R738 from 2.4K to 10K 0 .5
20 Decrease Audio AMP Gain 3 8 Change R971 from 100K to @100K; Change R973 from @100K to 100K 0 .5
Update with Item23
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Title
Size Document Number Rev
Date: Sheet o fLA-1811 0.7
H/W2 EE Dept. PIR SHEET(2)
63 66, 07, 2003星期四 八月
Compal Electronics, Inc.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
BHR60 from SI-1 to DB(15.4") LA-1811 REV:0.4 -> 0.5HW PIR <92.05.07.~92.05.30. >
21 RTL8101L no need transistor for 3.3V to 2.5V anymore 3 4 Delete Q55, R944 and C668
44Change PCB Footprint from SUYIN_020167MR004SX01ZR_4P tosuyin_020167mr004s511zu_4p for JP18, JP19 and JP20
M.B. Ver.
0 .5
0 .5Connector Spec. change for ME's request
Solve Tr and Tf of H-sync/V-sync over Spec issue for high resolution CRT 25 Delete Q68, Q64, R619, R620, R621 and R612; Add U57, U58 and R1150 0 .5
22
23
Reason for change PAGE Modify ListFixed IssueItem
Change R704 from 5.6K_0402_5% to 5.6K_0402_1%REALTEK recommendation
Delete useless components with BOM 10 Delete R574, R1086 and C952 0 .524
24 Delete R210 for UMA only
Add SB to control H_PROCHOT# for HP's request 2 6 Add Q118 and R1151 0 .525
Add components for EMI 37 Add R1152 0 .526
40 Add L65 ~ L78
Solve DOS cold-boot shunt down issue 7 Delete C256 0 .527
40 Add L79 ~ L97
Decrease overshoot & undershoot 2 5 Add R1153 and R1154 0 .628
Change SB GPIO0 and GPIO2 pull-down to GND 26 Delete RP126; Add R1155~ R1157 0 .629
Only 0603 size in SAP for 5.6K_1% 34 Change component size of R704 from 0402 to 0603 0 .630
40The pin-definition of FDD conn. was error on rev0.5 M/B31 0 .6Correct the pin-definition for JP38
4032 0 .6Change RP119 from 1K to 330; Delete RP121; Add R? and R?VIA recommendation
4 133 0 .6Change R880 from 10K to 470Enhance brightness of Docking LEDs
0 .634 44To support wake-up function with TP Change TP power from +5VS to +5V
0 .635 5Delete useless components Delete R535, R536, R991 and R992
12 Delete U53, C912~C914, D79~D82, R954, R1010~R1012 and R1023
17 Delete Q15 and R251
20 Delete R1022
24 Delete R211 and R216
25 Delete C93~C95 and C930
26 Delete Q113, R1124 and D91; Add D93
0 .6
27 Delete RP149, RP150, R1145 and Q114
29 Delete R53
37 Delete L45, R1019, Y6, R756, C740 and C741
Add components for EMI38 37 Add L98 and L99 0 .6
38 Delete R1142
40 Add C975, C976, CP15~CP17
0 .636 To improve RTC accuracy 2 6 Change Y1 from +/-20ppm to +/-10ppm
37 Solve Cardbus controller can't reset well issue 3 1 Delete R905, R941 and C906; Connect U37.C11 to G_RST#
39 Improve Audio quality3 8 Add R1158 and R1164; Exchange the nets of JP41.2 and JP41.3
0 .6
39 Delete RP153 and R1132
41 Add R1161
40 42 Add D92Add components for ID & ME
41 Change R904 from 91K to 47K49Modify +5V power-up timing to lead +3V
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BHR60 from DB to SI LA-1811 REV:0.5 -> 0.6HW PIR <92.06.20.~92.07.03. >
Delete C753~C756; Add R1165~R1168 and C97937
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Title
Size Document Number Rev
Date: Sheet o fLA-1811 0.7
H/W2 EE Dept. PIR SHEET(2)
64 66, 08, 2003星期五 八月
Compal Electronics, Inc.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
BHR60 from SI-1 to PV LA-1811 REV:0.6 -> 0.7HW PIR <92.07.03.~92.08.08. >
42 Correct Y1 and Y3 pin-out 2 6 Using pin-1 and pin-2 of these crystals
4 4Delete R65, R66, R67, R70, R72, R75, R79, R82, R86. R89, R94 and R95
M.B. Ver.
0 .7
0 .7ATI Product Advisory, refer to PA_218IXP0T1
Solve CD-ROM audio noise issue 3 0 Delete C11 0 .7
43
44
Reason for change PAGE Modify ListFixed IssueItem
Solve audio noise issue 3 7 Change R733.1 from +5VS to +5VAMP_CODEC 0 .745
For EMI 38 Add L100, L101, L102 and L103 0 .746
For FIR detect 3 9 Add R1173(no fir) and R1174(with FIR) 0 .74 7
ATI recommendation 2 7 Change RP12 from 10K to 2.2K 0 .748
Delete useless components 4 6 Delete D69 and D70 0 .749
To support wake-up function with TP 4 6 Delete RP154; Add R1169, R1170, R1171 and R1172 0 .750
Solve M10 can't power up issue 4 9 Delete C844 0 .751
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
46
46 Add R1175
Improve Tr and Tf of H-sync/V-sync for high resolution CRT 25 Decrease the R,L,C value 0 .75 2
Modify brightness of LEDs 42 Change Transistors from BJT to PMOS and Resisters value for Pav; Change Resisters value for Pre. 0 .75 3
45
Fast power on for battery only 4 5 Change R306 from 100K to 470; Delete Q112 0 .754
Change R901 from 27K to 6.8K
Improve contact Move JP2(CD-ROM conn.) right 0.65mm 0 .755
Correct Caps. LED and Numl. LED placement Exchange the placement of these LEDs 0 .756
Solve audio noise issue Cut the bridge between AGND and DGND in GND1 layer 0 .75 7
Reserve for EMI Add JOPEN6, JOPEN7 and JOPEN8 0 .758 37
Improve USB2.0 signal quality Change R1027, R1029, R1030, R1031, R1032, R1033, R1034 and R1035 0 .759 36
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Title
Size Document Number Rev
Date: Sheet o fLA-1811 0.7
65 66, 07, 2003星期四 八月
Compal Electronics, Inc.
Changed-List History-1
Version Change List ( P. I. R. List ) for Power Circuit
Item Issue DescriptionDateRequestOwner Solution Description Rev.Page#
1 0.2
0.3
Title
2
3
change to correct layout pad on PU7, PU8, PU9, PU10, PU11, PU16 and PQ24
54,55, 56,57 03/25/2003 Compal
DPRSLPVR56 03/25/2003Reserve two resistors for voltage of Deep-sleeper mode Reserver PR231, PR232, PR233, PR234
for deeper-sleeper mode voltage setting
03/25/2003 Reserve a jumper for power consumption measurement56 CPU VR-Cont.
4
Add PJP14
57 Compal Change Netname of +5VS_CORE
5 51 RTC charger Add PR230
wrong layout pad
wrong layout pad
Compal
Compal
CPU VR-Cont. 03/25/2003 Change the netname +5VS_CORE for powerconsumption measurement
03/25/2003 Compal use two resistors for RTC charger protection
6 re-located both PL10 and PQ21, PQ23 as well as 1.2VS_VGA related power circitry
55 1.2VS_VGA 03/25/2003 Compal re-layout 1.2V_VGA requested by ME
7 55 1.2VS_VGA 03/26/2003 Compal Reserve a jumper for power consumption measurement Add PJP15
8 55 +1.25VSP 03/26/2003 Compal Change power time-sequence of 1.25VSP input power Change VD, and VDD of PU16 from +2.5VALWPto +2.5VS; Connect PR235.2 to +2.5VSadd a resistor PR235 for Stand/By pin for test
9 03/27/2003 Compal Add PR237, PR238 for force PWM function control, and add PR236 for SUSP# signal
54 +1.5VALWP Reserve Force PWM function of 1.5V/2.5V and add a PR236 for SUSP# signal
10 54 +1.5VALWP04/16/2003 Compal
11 04/16/2003 Compal
Compal
Change power time-sequence of 1.5VSP input power
Add two transistor PQ44,PQ45 for voltage of Deep-sleeper mode
12 Change power JUMP SIZE to follow new jump role
56 CPU DPRSLPVR
565554
PWR JUMP
13 CPU DPRSLPVR56
04/16/2003
04/18/2003 Compal Reserve DPRSLPVR function and add a PR136 for +5VS_CORE signal
14
15
50 Vin DETECTOR 04/30/2003 CompalChange PR8 form 10k_0603 to 0K_0603
50 Precharge 04/30/2003 Compal Change PR1 from 10k_0603 to 100k_0603
16 04/30/2003 CompalChange PC20 from .22u to 1u ;PR40&PR42 from 100k to150k; PC80 from 1u to .47uBattery OTP
to make ACIN to enable to pull low
BOM error
To change feekbeck time
17
51
51 04/30/2003 Compal change component Change PU3 from S-81233SGUP-T1 to S-812C33AUA-C2N
18 52 Battery_OVP 04/30/2003 Compal To avoide the BATT_OVP output to oscillate Delet PC44&PR71
19 53 5V/3.3V/12V 04/30/2003 Compal BOM error Change PD16 from EC31Q04 to EC11FS2
04/30/2003 Compal To improve the 3V output ripple Voltage Delet PC7720 53 5V/3.3V/12V
change 1.5V time sequence
Change DPRSLPVR design
For DFX issuse
Change DPRSLPVR design
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.3
0.3
0.3
0.3
0.3
0.3
0.3
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4
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Title
Size Document Number Rev
Date: Sheet o fLA-1811 0.7
66 66, 07, 2003星期四 八月
Compal Electronics, Inc.
Changed-List History-1
Version Change List ( P. I. R. List ) for Power Circuit
Item Issue DescriptionDateRequestOwner Solution Description Rev.Page#
210.4
Title
Change PR121 from 511k to 180k;PR122 form 9.09k to 4.64k55 04/30/2003 Compal1.2VS_VGA BOM errors
22 50Prechargedetector 05/16/2003 Compal System can't power on by battery
AddPR191(909K_0603),PR192(47k_0603),PRPQ46(2N7002)&PQ47(DTC115EUA_SC70)
Change PR5 from 150k to 180k0.5
23 51Colok THROTTLING
05/16/2003 CompalTo modify the circuit Add PR193(73.2k) ,PC97(0.01U_0603); change PR22 form
84.5K to 11.5K
24 56,57 CPU_CORE(1&2) 05/16/2003 Compal Change the freqeuce 300k to 200k delet PR138 ; add PR187(0_0603)&PR188(0_0603)
0.5
0.5
25 52 Charger 05/16/2003 Compal To modify the charger circuit 0.5Add PR194(1K),PC98(0.1U_0603),PR195(47K),PQ48(DTA144EUA),PQ49(DTC115EUA),PQ50(2N7002),PD30(1SS355)
26 55 1.2VS_VGA 05/16/2003 Compal To modify the circuit for 1.2VS_VGA &1.5VS_VGA add PR124(11.5k_0603) 0.5
27
56 CPU_CORE
07/4/2003 CompalTo modify the DCR sense Add PR81(3.4k) ,PR78(3.4K),PR79(0_0402)
,PR85(0_0402),PC67(0.1U_0603) ,PC68(0.1U_0603);deletPR86,PR88,PR90,PR93
0.6
28
53 3V/5V/12V
07/4/2003 Compal To modify THE CPU Load line form -1.5mV/A to -2.2mV/AChange PR158,PR180 from 2k to 3.4k 0.6
29 56,57CPU_CORE(1&2) 07/4/2003
CompalTo improve the CPU_CORE effecient
Change PL12,PL13,PL14,PL15 from TOHO to PANASONIC 0.6
30
31
32
0.7
0.7
50 DC_in 08/4/2003 Compal For Gibson issue ,add two schottky diodes add PD43(SBM1040-13_powermite3) ,PD44(SBM1040-13_powermite3)
Charger 08/4/2003 Compal
53 3V/5V/12V 08/4/2003 Compal To solve the DCR sense for 5V OCP issuechange PR81(1.27k) ,PR78(1.54K),PR79(0_0402),PR85(0_0402),PC67(0.47U_0603) ,PC68(0.47U_0603);addPR241(1.24k),PR242(620 ohm),PR243(698 ohm)
33 56 CPU_CORE 08/4/2003 Compal To modify THE CPU Load line form -2.2mV/A to-1.5mV/A, and senes CPU VCC and VSS
Change PR158,PR180 from 3.4k to 2.2k and add PR244 (0 ohm)and PR245(0 ohm)
0.7
0.7
52Add PD30(1SS355_SOD323) ,PC98 (0.1U_0603),PR195(47K_0402),PQ49(DTC115EUA_S
34 52 Charger 08/4/2003 Compal
To modify the Precharge circuit
To improve the charger feedback loop for charger noise issueChange PR52 (47k_0603),PR57(1K_0603),PC36(1500P_0603) 0.7
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