elct201: digital logic design...โข an encoder is a digital circuit that performs the inverse...
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ELCT201: DIGITAL LOGIC DESIGN Prof. Dr. Eng. Tallal El-Shabrawy, tallal.el-shabrawy@guc.edu.eg
Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg
Lecture 6
ููู 1441ู ุญุฑู
Spring 2020
Following the slides of Dr. Ahmed H. Madian
COURSE OUTLINE
1. Introduction
2. Gate-Level Minimization
3. Combinational Logic
4. Synchronous Sequential Logic
5. Registers and Counters
6. Memories and Programmable Logic
2
LECTURE OUTLINE
โข Combinational Logic Circuits
โข Decoders
โข Encoders
โข Multiplexers
โข Tri-state Buffers
3
DECODERS
4
โข Consider a vending machine that takes 3 bits as input and releases a single product, out of the available 8 product sorts
โข A Decoder is a combinational circuit that converts binary information from ๐ input lines to a maximum of 2๐ unique output lines
โข If the ๐ โbit coded information has unused combinations, the decoder may have fewer than 2๐ outputs
Vending
Machine Input pad
Output
select
line
DECODERS
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โข It is required to design a combinational circuit with two inputs (๐, ๐) and four outputs (๐ท0, ๐ท1, ๐ท2, ๐ท3), such that:
โข ๐ท0 = 1 when ๐ = 0 and ๐ = 0
โข ๐ท1 = 1 when ๐ = 0 and ๐ = 1
โข ๐ท2 = 1 when ๐ = 1 and ๐ = 0
โข ๐ท3 = 1 when ๐ = 1 and ๐ = 1
DECODERS
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Solution
1. From the specifications of the circuit, determine the required number of inputs and outputs and assign a letter (symbol) to each
2 ร 4
Decoder
๐
๐ ๐ท3
๐ท1
๐ท2
๐ท0
DECODERS
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2. Derive the truth table that defines the required relationship between the inputs and outputs
Inputs Outputs
๐ ๐ ๐ท0 ๐ท1 ๐ท2 ๐ท3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
DECODERS
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3. Obtain the simplified Boolean functions for each output as a function of the input variables
๐ท0 = ๐โฒ๐โฒ
๐ท1 = ๐โฒ๐
๐ท2 = ๐๐โฒ
๐ท3 = ๐๐
4. Sketch the logic diagram
๐ท0
๐ท1
๐ท2
๐ท3
๐
๐
3ร8 DECODER
โข A 3 ร 8 line decoder decodes 3 input bits into one of 8 possible outputs
โข Each output represents one of the minterms of the 3 input variables
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๐ฆ
๐ฅ
๐ง
๐ท0 = ๐ฅโฒ๐ฆโฒ๐งโฒ
๐ท1 = ๐ฅโฒ๐ฆโฒ๐ง
๐ท2 = ๐ฅโฒ๐ฆ๐งโฒ
๐ท3 = ๐ฅโฒ๐ฆ๐ง
๐ท4 = ๐ฅ๐ฆโฒ๐งโฒ
๐ท5 = ๐ฅ๐ฆโฒ๐ง
๐ท6 = ๐ฅ๐ฆ๐งโฒ
๐ท7 = ๐ฅ๐ฆ๐ง
2ร4 DECODER
โข A decoder could include an Enable input to control the circuit operation
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๐ต
๐ธ
๐ด
๐ท0
๐ท1
๐ท2
๐ท3
โข A decoder could be implemented with NAND gates and thus produces the minterms in their complemented form
IMPLEMENTING FUNCTIONS USING DECODERS
โข Any combinational circuit can be constructed using decoders and OR gates (the decoder generates the minterms and the OR gate performs the summation)
โข Example: Implement a full adder circuit with a decoder and two OR gates
โข Full adder equations:
๐ ๐ฅ, ๐ฆ, ๐ง = ฮฃ๐(1,2,4,7) and ๐ถ ๐ฅ, ๐ฆ, ๐ง = ฮฃ๐(3,5,6,7)
โข Since there are 3 inputs, we need a 3 ร 8 decoder
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IMPLEMENTING FUNCTIONS USING DECODERS
โข ๐ ๐ฅ, ๐ฆ, ๐ง = ฮฃ๐(1,2,4,7) and
โข ๐ถ ๐ฅ, ๐ฆ, ๐ง = ฮฃ๐(3,5,6,7)
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Inputs Outputs
๐ฅ ๐ฆ ๐ง ๐ถ ๐
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
๐ฆ
๐ง
๐ฅ
๐ถ
๐
DECODER EXPANSIONS
โข Larger decoders can be constructed using a number of smaller ones
โข For example, a 3 ร 8 decoder can be built using a couple of 2 ร 4 decoders and a 4 ร 16 decoder can be built using a couple of 3 ร 8 decoders
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๐ฆ
๐ง
๐ฅ
๐ค
๐ท0 to ๐ท7
๐ท8 to ๐ท15
4 ร 16 Decoder
EXERCISE
โข Can you sketch a 4 ร 16 decoder using a number of 2 ร 4 decoders?
โข I am now giving you 5 minutes to attempt it
โข After these 5 minutes, the lecture will continue
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DEDEC
15
4 ร 16 DECODER USING 2 ร 4 DECODERS
ENCODERS
โข An encoder is a digital circuit that performs the inverse operation of a decoder
โข An encoder has 2๐ input lines and ๐ output lines
โข The output lines generate the binary equivalent of the input line whose value is 1
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8ร3 OCTAL-TO-BINARY ENCODER
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๐ฅ = ๐ท4 + ๐ท5 + ๐ท6 + ๐ท7 ๐ฆ = ๐ท2 + ๐ท3 + ๐ท6 + ๐ท7 ๐ง = ๐ท1 + ๐ท3 + ๐ท5 + ๐ท7
What happens if more than one input is
active (set to HIGH) at the same time?
For example, ๐ท3 and ๐ท6?
What happens if all inputs are equal to 0?
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What happens if more than one input is active (set to HIGH) at the same time? For example, ๐ท3 and ๐ท6?
โข If ๐ท3 and ๐ท6 are active simultaneously, the output would be (111)2= (7)10, because all three outputs would be equal to 1
โข But this does not reflect the actual input which should have resulted in an output of (011)2= (3)10 for ๐ท3 or (110)2= (6)10 for ๐ท6
โข To overcome this problem, we use priority encoders
โข If we establish a higher priority for inputs with higher subscript numbers, and if both ๐ท3 and ๐ท6 are active at the same time, the output would be (110)2 because ๐ท6 has higher priority than ๐ท3
๐ฅ = ๐ท4 + ๐ท5 + ๐ท6 + ๐ท7 ๐ฆ = ๐ท2 + ๐ท3 + ๐ท6 + ๐ท7 ๐ง = ๐ท1+๐ท3 + ๐ท5 + ๐ท7
8ร3 OCTAL-TO-BINARY ENCODER
19
What happens if all inputs are equal to 0?
โข The encoder output would be (000)2, but in fact this is the output when ๐ท0 is equal to 1
โข This problem can be solved by providing an extra output to indicate whether at least one input is equal to 1
โข ๐ฃ is the valid output
๐ท7๐ท6๐ท5๐ท4๐ท3๐ท2๐ท1๐ท0
๐ง
๐ฆ
๐ฅ
๐ฃ
8ร3 OCTAL-TO-BINARY ENCODER
20
โข The input ๐ท3 has the highest priority,
regardless of the values of the other inputs
โข Thus, if ๐ท3 is 1, the output will indicate
that ๐ด1๐ด0 = 11, i.e. the code
๐ด1๐ด0 = 11 means that any data
appearing on line ๐ท3 will have the
highest priority and will pass through the system irrespective of other inputs
โข If ๐ท2 = 1 and ๐ท3 = 0, the output
code will be ๐ด1๐ด0 = 10 and this
means that ๐ท2 has the highest priority in this case
4ร2 PRIORITY ENCODER
Inputs Outputs
๐ซ๐ ๐ซ๐ ๐ซ๐ ๐ซ๐ ๐จ๐ ๐จ๐ ๐
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 X 0 1 1
0 1 X X 1 0 1
1 X X X 1 1 1
21
MAKING CONNECTIONS
Control Control
Multiplexer Demultiplexer
โข Direct point-to-point connections between gates are made up of wires
โข Routing one of many inputs to a single output is carried out using a multiplexer
โข Routing a single input to one of many outputs is carried out using a demultiplexer
22
MULTIPLEXERS
โข A multiplexer is used to connect 2๐ points
to a single point
โข The control signal pattern forms the binary
index of the input to be connected to the
output
๐ฐ๐ ๐ฐ๐ ๐จ ๐
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
๐จ ๐
0 ๐ผ๐
1 ๐ผ๐
Functional
form
Logical
form
2ร1 MUX ๐ผ๐
๐ผ๐
๐ด
๐
๐ = ๐ดโฒ๐ผ0 + ๐ด๐ผ1
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MULTIPLEXERS
8ร1 MUX
4ร1 MUX
2ร1 MUX ๐ผ๐
๐ผ๐
๐ด
๐
๐ผ๐
๐ผ๐
๐ผ๐
๐ผ๐
๐ ๐
๐ผ๐
๐ผ๐
๐ผ๐
๐ผ๐
๐ผ๐
๐ผ๐
๐ผ๐
๐ผ๐
๐ด ๐ต
๐ด ๐ต ๐ถ
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2ร1 LINE MULTIPLEXER
๐ ๐
๐ ๐
๐ผ๐
๐ผ๐
๐ผ๐
๐ผ๐
4ร1 LINE MULTIPLEXER
๐
๐ผ๐
๐ผ๐
๐ผ๐
๐ผ๐
๐0
๐1
๐บ๐ ๐บ๐ ๐
0 0 ๐ผ๐
0 1 ๐ผ๐
1 0 ๐ผ๐
1 1 ๐ผ๐
25
Functional
form
Can you sketch the logic
diagram of an 8ร1
multiplexer?
8ร1 LINE MULTIPLEXER
โข I am now giving you 5 minutes to attempt sketching the logic diagram of an 8ร1 line multiplexer
โข After these 5 minutes, the lecture will continue
26
8ร1 LINE MULTIPLEXER
27
28
MULTIPLEXERS AS GENERAL-PURPOSE LOGIC
โข A 2๐โ1: 1 multiplexer can implement any function of
๐ variables
โข Steps:
1. The Boolean function is listed in a truth table
2. The first ๐ โ 1 variables in the table are applied
to the selection inputs of the MUX
3. For each combination of the selection variables,
evaluate the output as a function of the last
variable
4. The values are then applied to the data inputs in
the proper order
29
MULTIPLEXERS AS GENERAL-PURPOSE LOGIC: EXAMPLE I
๐น ๐ฅ, ๐ฆ, ๐ง = ฮฃ(1,2,6,7)
๐น
๐ฆ
๐ฅ
๐ง
๐งโฒ
0
1
๐น
๐ถ
๐ด
๐ท
0
1
๐ต
30
MULTIPLEXERS AS GENERAL-PURPOSE LOGIC: EXAMPLE II
๐น ๐ด, ๐ต, ๐ถ, ๐ท = ฮฃ(1,3,4,11,12,13,14,15)
31
THREE-STATE BUFFERS (TRI-STATE BUFFERS)
โข These are digital circuits that exhibit three states
โข Two of these states are logic 0 and logic 1
โข The third state is a high-impedance state in which:
1. The logic behaves like an open circuit
2. The circuit has no logic significance
3. The circuit connected to the output of the three-
state gate is not affected by the inputs to the gate
32
MULTIPLEXERS USING THREE-STATE BUFFERS
๐ด
๐ต
๐๐๐๐๐๐ก
๐๐๐๐๐๐ก
๐ธ๐๐๐๐๐
๐ผ๐
๐ผ๐
๐ผ๐
๐ผ๐
๐
๐
2 ร 1 line MUX 4 ร 1 line MUX
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