情報デバイス工学特論 5回 · qualitative circuit analysis 1. break all feedback loops and...

平成１７年度　前期　大学院

情報デバイス工学特論第5回

中里　和郎

基本CMOSロジック回路(2)

今回の講義内容は

William J. Dally and John W. PoultonDigital Systems EngineeringCambridge University Press, 1998

4.3.4~4.4.2 (pp. 191-215)の内容に従っ

ている

Basic FET Amplifiers Forms

inout

Load

Load

inout

in outLoad

VGG

Common Source Source Follower Cascode or Common Gate

voltage gain

current gain

X

X

○

○ ○

○

Source Follower

inout

1/ 22 S

out in TnIV V Vβ

⎛ ⎞= − − ⎜ ⎟

⎝ ⎠

Ld

S

VCtI

Δ=

inout

CL

CG

IS

基板バイアス効果により

1out

in

VV

Δ<

Δ

出力への駆動力が大きい入力への負荷が小さいCG の影響小

Vin

Vout

0VTn

Source Follower Logic

A

B C( )D A B C= ∧ ∨

not composable 繋げて回路を組むには、出力をレベル・シフトし増幅してやる必要がある

他の回路との組み合わせとして使う

Cascode

ID

in

outVGG

ID

in

out

ref

ID

replica-bias circuit

Vin = Vref

Vout = VGG

VGG

VX

Vin

Vout

0

2 DX GG Tn

IV V Vβ

= − −

VDD

GG TnV V−

VX = Vref

Cascode Logic

A

B

IDVGG

C A B= ∧

not composable

Cascoded Common-source Amplifier

ID

out

VGG

in

AA GG TnV V V≈ −

m1

m2

DCゲインの増加Miller 効果を消す

Current Mirrors

I1 I2

VGG

VO1/ 2

12GG Tn

IV Vβ

⎛ ⎞− = ⎜ ⎟

⎝ ⎠

( ) ( ) ( )22 11 1GG Tn O OI V V V I Vβ λ λ= − + = +

2 1

1OO

VrI Iλ

∂= =

∂

I1 I2

I1

I2 I3 I4

low-pass filter

Cascode Current Mirror

I1 I2

VG2

VO

VG1

( )22 2 1

2OO

G Tn

VrI V V Iλ

∂= =

∂ −

VO

I2

m1

m2

m1

m2

線形

線形 飽和

飽和

動作領域が狭くなる (headroom)

Source-Coupled Pair

I1 I2

V1 V2

VS

IS

ΔV = V１- V2

I1 , I2

0

IS

0

I1I2

1 2V V VΔ = − 1 2I I IΔ = −

1 2

2CV VV +

= 1 2

2 2S

CII II +

= =

mI g VΔ = Δcommon-mode

differential

( )m C S Tng V V Vβ= − −

Differential Load

Differential Voltage Differential CurrentSource-coupled pair

Differential Load

+ ΔV −I1 I2

V1 V2

VrIΔ

∂Δ=

∂ΔC

CC

VrI

∂=

∂

CC

VrIΔ

∂Δ=

∂C

CVr

IΔ

∂=

∂Δ

cross-impedance

C CC C

C

r rV Ir rV I

Δ

Δ Δ

⎛ ⎞⎛ ⎞ ⎛ ⎞= ⎜ ⎟⎜ ⎟ ⎜ ⎟Δ Δ⎝ ⎠ ⎝ ⎠⎝ ⎠

R R

Several Differential Loads

I1 I2V1 V2

I1 I2V1 V2

I1 I2V1 V2

I1 I2V1 V2

Resistor Current Mirror Cross-Coupled Infinite Impedance

rC R

rΔ R

1/gm

1/λI1

1/gm

−1/gm

1/2gm

∞

FET Resistor

I

V+

−

Triode

I

V+

−

Two-elements

V

I

Pass Gate FET Resistor

r0 r1 r2 r3

r0 , r1 , r2 , r3 = H or L

Digital Trimming

Simple Differential Amplifier

I1 I2out+out−

in+ in−

Vbias

Vbias

Vlow+−

Replica-bias Circuit

Gain

gm

rΔ

AΔ=gmrΔ

ΔVin=Vin+−Vin−0

Vout−Vout

Vout+

Vhigh

Source Coupled FET Logic

XOR

Vbias

B-

A+ A-

B+

out+out−

Bandwidth of Differential Amplifier

dr Cτ Δ=out+

in+

Vbias

in−

mA g rΔ Δ=

cutoff frequency

1 12 2 d

fr Cπτ πΔ

Δ

= =

gain bandwidth product(unity-gain frequency)

1 2m

d

gf A fCπΔ Δ= =

AΔ

fΔ f1

1ff

1 f

Gain

Regenerative Circuits and Clocked Amplifier

I

+ ΔV −

I1 I2

Cd Cd

V1 V2小さな信号 ΔV を高速でfull-swing に増幅

t = 0 Ι = 0 , ΔV =ΔV(0)

m

d d

gd V I Vdt C CΔ Δ

= = Δt > 0

( )0 expr

tV Vτ

⎛ ⎞Δ = Δ ⎜ ⎟

⎝ ⎠

dr

m

Cg

τ =

in+clk

clk

clk

clk

V1 V2in−

Complementary Clocked S/A

clk = low

in+ → V1in− → V2

clk = high

in+, in− → VDD , 0

pass gate

in+

clkclk

in−

V1 V2

Gate-Isolated S/A

clk

S1 S2

clk = low

S1, S2, V1, V2 : precharged

Static Latch

inclk

outS

clk

clk

Qualitative Circuit Analysis

1. Break all feedback loops and assign a direction to any

bidirectional circuit elements.

2. Identify basic circuit forms in the circuit and partition the

circuit into these components.

3. Identify region(s) of operation for each device.

4. Describe the open-loop behavior of the circuit.

5. Describe the closed-loop behavior of the circuit.

Qualitative Analysis of a Differential Amplifier

in+ in−

out+out−

Differential Load

Source-Coupled Pair

Current mirror

Voltage Divider

Qualitative Analysis of a Voltage-Controlled Oscillator

in

Current mirror

Current source

Inverters

Feedback

Power Dissipation of a Static CMOS Gate定常状態 どちらかのトランジスタがOFF

消費電力小 （サブスレッショルド電流x電源電圧）

ON ⇔ OFF の切り替え時に電力を消費

C

出力 OFF → ON のエネルギー消費量

( ) ( )2

0 2

DDVDD

SW DD C DD C CCVE V V Idt V V CdV= − = − =∫ ∫

= 出力 ON → OFF のエネルギー消費量

1サイクルのエネルギー消費量= CVDD2

消費電力 = C VDD2 KD fck

KD : duty factor ~ 0.15fck : clock frequency

Energy-Delay Product

( )22DD DD

DSS DD T

V C VCI V V

τβ

= =−

2cy DDE CV= ( )

32

22 DD

cyDD T

VCEV V

τβ

=−

VT

VDD

cyE τ

レポート（５）

１．右の Chappell Amplifier の動作を説明せよ

Vout+−

Vin

２．下の３つの回路を抵抗として用いた場合について I-V 特性を示せ。次の範囲でVが変化するとき、どの

回路を用いるのが良いか？(1) GND に近い小電圧(2) GNDからVctrl までの電圧(3) GNDからVDDまでの電圧

V VI I

VI

VctrlVctrl Vctrl

(a) (b) (c)