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Introduction to VLSI Circuits and Systems, NCUT 2007
Chapter 08Designing High-Speed CMOS Logic
Networks
Introduction to VLSI Circuits and Systems積體電路概論
賴秉樑Dept. of Electronic Engineering
National Chin-Yi University of Technology
Fall 2007
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
Gate Delays Driving Large Capacitive Loads Logical Effort BiCMOS Drivers
Introduction to VLSI Circuits and Systems, NCUT 2007
Gate Delay
In VLSI, the ability to meet system timing targets is intimately related to the switching speed of the logic circuits
» The output switching times of the CMOS logic gate
Lprr Ctt 0
Lnff Ctt 0
(8.1)
Figure 8.1 Output switching times
Introduction to VLSI Circuits and Systems, NCUT 2007
Minimum-size MOSFET
Figure 8.2 Unit transistor reference
The drawn aspect ratio (W/L) and the active dimension X are determined by the design rules
» We can define the parasitical R and C for the device by design rules
» While
» To create a design methodology, we will specify that all transistor size are integer multiples of the minimum width Wmin = Wu
TDDu
u
VVL
WR
'
1
(8.2)
uoxGu WLCC
uDBGDDu CCC
uSBGSSu CCC
(8.3)
um L
Wm
L
W
(b) 3X scaled FET (m=3)
(a) Minimum-size
(8.4)
with m=1,2, 3, …as the size specifier
(u: unit FET parameters)
(u: unit FET parameters)
Introduction to VLSI Circuits and Systems, NCUT 2007
mX Scaled FET The resistance and gate capacitance of the m-
size FET are written in terms of the unit transistor as
m
RR u
m
GuGm mCC
DuDm mCC SuSm mCC
(8.5)
(8.6)
uumm CRCR constant (8.7)
Figure 8.2 Unit transistor reference
(b) 3X scaled FET (m=3)
(a) Minimum-size
This is true by the Scaling Theorem in chapter 07
Introduction to VLSI Circuits and Systems, NCUT 2007
Inverter Using Scaled Transistors (1/2)
Rise and Fall time with scaled technology (Figure 8.3(a), unit gate)
» Since Rp > Rn, tr0 > tf0, and , for a given load CL, tru > tf
u. The midpoint voltage is
» The input capacitance is a minimum value for a complementary pair
» However, this does not change the midpoint voltage, but does alter the switching times
The response time of the new circuit next slide
Figure 8.3 Inverter designs using scaled
transistors
(a) Unit Inverter (b) m = 3
Lpurru Ctt 0
Lnuffu Ctt 0
(8.8)(8.9)
(rise time is controlled by pFET)
(fall time is controlled by nFET)
nupu
r
VrVVV
TnTpDD
M
1(8.10)
where is the mobility ratio
p
nr
min2 CCC uin (8.11)
(Mid. Voltage of an inverter)
Introduction to VLSI Circuits and Systems, NCUT 2007
Inverter Using Scaled Transistors (2/2)
The response of the new circuit (Figure 8.3(b), m = 3)» The zero-load times tr0 and tf0 are (approximately) constants
and the slope parameter decrease as (1/m) because of the decrease in resistance by the same factor. Thus,
» The input capacitance for this gate is
Lpu
rr Ctt303
Lnu
ff Ctt303
min3CCin
(8.12)
(8.13)
Figure 8.3 Inverter designs using scaled
transistors
(a) Unit Inverter (b) m = 3
(under s = 3)
(under s = 3)
Introduction to VLSI Circuits and Systems, NCUT 2007
NAND Using Scaled Transistors
Minimum-size NAND2
» Since an nFET/pFET pair consists of minimum-size devices, the input capacitance is
NAND2 with m = 3
» The input capacitance is
Lpurr Ctt
02
3
Lnuff Ctt 23 0 (Unit NAND2)(8.14)
minCCin (8.15)
Lpu
rr Ctt32
30
Lnu
ff Ctt3
23 0
(8.16)
(8.17)
min3CCin
Lpu
rr Cm
tN
t
02
1
Lnu
ff Cm
NtNt
01
minmCCin
(8.18)
If N is the fan-in (number of inputs), then we may extrapolate the analysis to write
(NAND-N)
For an N-input NAND gate that use m-sized FETs
Figure 8.4 NAND2 gate scaling
(a) Unit transistors (b) m = 3
Introduction to VLSI Circuits and Systems, NCUT 2007
NOR Using Scaled Transistors
Minimum-size NOR2
» For M = 3
» For N inputs and general scaling factor m
» These equations clearly demonstrate the dependence of the switching times and input capacitance on
Number of inputs N (fan-in) Transistor scaling factor m
Lpurr Ctt 23 0 Lnuff Ctt
02
3
Lpu
rr Ctt3
23 0
L
nuff Ctt
32
30
Lpu
rr Cm
NtNt
01
Lnu
ff Cm
tN
t
02
1
minmCCin
(8.21)
(8.22)
(8.23)
(8.24)
Figure 8.5 NOR2 gate scaling
(b) m=3 circuit(a) Unit transistors
(Unit NOR2)
(Unit NOR-N)
Introduction to VLSI Circuits and Systems, NCUT 2007
Delay Time Estimation (1/2)
For a logic chain with M stages, the total delay through the chain by summing the individual delays:
Figure 8.6 Delay time example
M
iid tt
1
32221 ||| mNORmNANDmNOTd tttt
min01 2| Ctt nufmNOT
min022 322
3| Ctt pu
rmNAND
min032 432
3| Ctt nu
fmNOR
min00
min0min0
2
3
3
10)35(
2
1
2
3
2
3
3
10
2
5
Ctt
CtCtt
punurf
purnufd
Ls Ctt 0
inv
uin
C
rCC
1
Ls Cm
tt
0
(8.25)
(8.26)
(8.27)
(8.28)
(8.29)
(8.30)
(8.31)
(tf) (tf)(tr)
(βn ≠ βp) (βn=βp, Wn=Wmin and Wp=rWmin)(minimum-size inverter)
Introduction to VLSI Circuits and Systems, NCUT 2007
Delay Time Estimation (2/2)
Using the minimum-size inverter (βn=βp) as a basic, and then build up NAND and NOR gates for increasing numbers of inputs N
Figure 8.7 Delay times as a function of
fan-in N
minBnAtd
minminmin CR
minC
Cn L
min)1(
1, )()( BnAxt NNd
min)1(
, )()17.1( BnAt NNd
min)1(
1, )(
n
m
BAxt Nm
Nd
min)1(
12, )(
n
m
BAxxt Nm
Nd
(8.32)
(8.33)
(8.34)
(8.38)
(8.35)
(8.36)
(8.37)
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
Gate Delays Driving Large Capacitive Loads Logical Effort BiCMOS Drivers
Introduction to VLSI Circuits and Systems, NCUT 2007
Driving Large Capacitive Loads
High speed design can be obtain from studying the characteristic delay through inverter
Figure 8.8 CMOS inverter circuit
np L
Wr
L
W
1'
'
p
n
p
n
k
kr
)(
1
TDDpn VV
RRR
]1[)( /tDDout eVtV
/)( tDDout eVtV
)( LFETout CCRRC
Ls Ctt 0
)(
1
TDD VVR
)( GpGnox
GpGnin
AAC
CCC
Gn
nox
pnoxin
Cr
LWCr
WWLCC
)1(
))(1(
)(
)2/( DDM VV
(8.42)
(8.43)
(8.44)
(8.50)(8.45)
(8.48)
(8.49)
(8.46)
(8.47)
(8.51)
(p-network pre-charge function)
(n-network dis-charge function)
(assume ts = tr = tf)
Introduction to VLSI Circuits and Systems, NCUT 2007
Unit Load
Figure 8.9, since the load capacitance is the same as the gate’s own input capacitance , we call this a unit load value
Figure 8.9 Concept of a unit load
Figure 8.10 Driving a large input capacitance gate
inL CC 1
ins Ctt 01
S'
S
RR '
S
'
Ls CS
tt
0
nn SWW '
inin SCC '
CL1
(unit load) (8.52)
(switching time)
(When CL >> Cin, using S > 1)
(new switching time)
(8.53)
(8.54)
(8.55)
(8.52)
(8.53)
(8.54)
(8.55)
(When CL=S Cin, using S > 1)
Introduction to VLSI Circuits and Systems, NCUT 2007
Delay Minimization of Inverter Cascade, ideal case (1/3)
In figure 8.11. To drive the large load capacitance, let the 1-th be the unit gate
Figure 8.11 Inverter chain analysis
NN 1321 ...
12 S
23 S
jj S 1
12 S
12
23 SS
13
34 S
1)1( j
j S
1)1( CSC j
j
)1( jj S
RR
1 jjj CR
Figure 8.12 Characteristics of a typical stage in the
chain
(8.60)
(8.61)
(8.62)
(8.63)
(8.64)
(8.65)
(8.66)
(8.67)
cetanctranscondudevice
cetanresisFETR
etanccapaciinputC
1
1
1
(1-th stage parameters)
(assume Cj+1 >> CFET,j)
Introduction to VLSI Circuits and Systems, NCUT 2007
Delay Minimization of Inverter Cascade, ideal case (2/3)
LNNN
NNd
CRRRCRCRCR
1433221
1321
...
...
1
1
CS
CCN
NL
111
11
21
13
21
121
11 ... CSS
RCS
S
RCS
S
RCS
S
RSCR N
NN
Nd
)(
...
11
1111111111
CSRN
CSRCSRCSRCSRCSRd
rd NS
1CSC NL
)ln(ln)ln(1
SNC
CS LN
)ln(
ln1
S
C
C
N
L
)ln(ln
1 S
S
C
CLrd
0)ln(
S
S
SSd
1)ln( Sor
eS
1
1 ln)ln(
ln
C
C
S
C
C
N L
L
rL
d C
Ce
1
ln
Figure 8.13 Time constants in the cascade
(8.68)
(8.69)
(8.70)
(8.71)
(8.72)
(8.73)
(8.74)
(8.75)
(8.77)
(8.78)
(8.79)
(8.80)
(8.81)
(8.76)
(8.82)
(N stages)
11, CRwhere r
0)][ln()ln(
12
SS
S
S
(e = 2.71…)
Introduction to VLSI Circuits and Systems, NCUT 2007
Delay Minimization of Inverter Cascade, in physical (3/3)
Figure 8.14 shows the j-th stage circuit with the parasitic FET capacitance CFj included at the output S > e (in physical design)
Figure 8.14 Driver chain with internal FET
capacitance
)( 1, jjFjj CCR
1,)1(
, Fj
jF CSC
)(...)()( ,32,221,1 LNFNFFd CCRCCRCCR
)( 111,1 CSRNCNR Fd
1
ln)ln()ln( C
C
S
S
SL
rx
d
1,1 Fx CRwhere
r
xSS
1)ln(
(8.68)
(8.69)
(8.70)
(8.71)
(8.72)
(8.73)
(8.74)
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
Gate Delays Driving Large Capacitive Loads Logical Effort BiCMOS Drivers
Introduction to VLSI Circuits and Systems, NCUT 2007
Logical Effort
Logical effort characterizes gates and how they interact in logic cascades, and provides techniques to minimize the delay
» Basic definition starts with an inverter, and uses a symmetric NOT gate, where
» The logical effort g of a gate is defined by the ratio of capacitance to that of the reference gate:
» For the 1X inverter, , where AGn = WnL and AGp = WpL
pn
np L
Wr
L
W
(8.98)
Figure 8.15 Reference inverter for logic effort
ref
in
C
Cg (8.99)
)( GpGnoxin AACCSince
(8.103)
ref
Gn
noxin
np
C
rC
rLWCC
rWWSince
1
1 1ref
refNOT C
Cg(8.102)
Introduction to VLSI Circuits and Systems, NCUT 2007
Electrical Effort
Electrical effort h is defined by the capacitance ratio
» It is the ratio of electrical drive strength that is required to drive Cout relative to that needed to drive its own input capacitance Cin
» The absolute delay time dabs through the inverter is written in the form
in
out
C
Ch (8.104)
Figure 8.16 Delay circuit for a 1X inverter
sec)( , outrefprefabs CCRd
S
RR ref
refpP SCC ,
)(
)(
, outrefpref
outpabs
CSCS
R
CCRd
refin SCC
in
outrefrefrefpref
refref
outrefrefpref
outref
refpref
abs
C
CCRCR
CC
C
S
RCR
CS
RSC
S
Rd
,
,
,
refref CR
)( phd abs
refref
refprefpar
CR
CRp ,
phd
d abs
(8.105)
(8.106)
(8.107)
(8.110)
(8.111)
(8.112)
(8.113)
(8.114)
(8.108)
(8.109)
(In chapter 07, k=ln(9)≒2.2)
Introduction to VLSI Circuits and Systems, NCUT 2007
Logical Effort Examples
2-Stage inverter chain
Figure 8.17 2-Stage inverter chain
)()( 2211
21
phph
ddD
2
32
1
21 ,
C
Ch
C
Chwhere
first
last
C
CH
21hhH
1
3
2
3
1
2
C
C
C
C
C
CH
12 h
Hh
2
111 )( p
h
HphD
21
1111
)( ph
Hph
hh
D
012
11
h
H
h
D
21 hh
(8.115)
(8.116)
(8.117)
(8.118)
(8.119)
(8.120)
(8.121)
(8.122)
(8.123)
(8.124)
(path electrical effort)
(since H=h1h2)
Introduction to VLSI Circuits and Systems, NCUT 2007
Logical Effort Generalization (1/2)
The real power of the Logical Effort tech. is that it can be generalized to include arbitrary CMOS logic gates
All calculations are reference to the 1X reference inverter with an input capacitance Cref and transistor resistance Rref
In figure 8.18(a)
In figure 8.18(b)
Figure 8.18 Symmetric NAND and NOR gates
(a) NAND2
(b) NOR2
)2( rCC Gnin
)21( rCC Gncin
r
r
C
rCg
ref
GnNOR
1
21)21(2
(8.125)
(8.126)
(8.127)
(8.128)
(Cin of NAND2)
r
r
C
rCg
ref
GnNAND
1
2)2(2 (logical effort of NAND2)
(Cin of NOR2)
(logical effort of NOR2)
Introduction to VLSI Circuits and Systems, NCUT 2007
Logical Effort Generalization (2/2)
)( rnCC Gnin
r
rng NAND
1
pghd
iiii phgd
N
i
N
iiiii phgdD
1 1
)(
N
iNi ggggG
121 ...
h
iNi hhhhH
121 ...
Λ
ii ftstanconhg
N
fF
NFfgh /1
ii g
fh
PNFD N
/1
N
iipP
1
refnpp
N
NN
ffff
hghghghg
GHF
...
))...()()((
321
332211
Generalize to larger fan-in gates, an n-input NAND and NOR gate
(8.129)
(8.130)
(8.131)
(8.132)
(8.133)
(8.134)
(8.135)
(8.137)
(8.138)
(8.139)
(8.140)
(8.141)
(8.142)
(8.143)
(8.144)
r
nrg NOR
1
1
(8.136)
(NAND2)
(logical effort of NAND2)
(logical effort of NOR2)
(total path delay)
(path logical effort)
(path electrical effort)
(path effort)
(min. delay)
(min. path delay)
(design reference)
(min. path delay)
(n-stage parasitic)
Introduction to VLSI Circuits and Systems, NCUT 2007
Optimizing the Number of Stages
A well-known characteristic of CMOS logic cascades is that the fact that one can often insert inverters into a logic chain and decrease the total delay time
Logic Effort shows this feature using the path delay D
Therefore, it may be possible to obtain a smaller path delay by inserting the inverters (buffer inversion)
» A large memory cell array and it’s peripheral circuit, e.g. address decoder» Placement and routing of FPGA application
NgggG ...21
GHF
NN GHFf /1/1 )(
PNFD N
/1
(8.162)
(8.163)
(8.164)
(8.165)
(Note: logic effort of an inverter is gnot = 1)(multiplying by additional factors of gnot does not change the numerical value of the path effort)
(Delay time minimization)
(the total path dealy)
Introduction to VLSI Circuits and Systems, NCUT 2007
Logical Area
With scaling theorem, an estimate of the circuit requirements can be obtained using Logical Effort quantities by simply summing the gate areas of each FET by calculating the logical area (LA) for the j-th gate using
LWLA ii
rLANOT 1
)1( rSLANOT
)21(2 rSLANOR
)2(2 rSLANAND
M
iiLALA
1
(8.174)
(8.175)
(8.176)
(8.177)
(8.178)
(8.179)
(LA for the j-th gate)
(LA of 1X NOT gate)
(including scaling factor s > 1 with NOT gate)
(including scaling factor s > 1 with NOR2 gate)
(including scaling factor s > 1 with NAND2 gate)
(the total LA for a network with M gates)
Introduction to VLSI Circuits and Systems, NCUT 2007
Branching
The tech. of Logical Effort applied to a well-defined path. However, when a logic gate drives two or more gates, a branching concept must be considered
In Figure 8.20, two branching points between the primary In/Out Figure 8.20
Branching
path
T
C
Cb
offpathT CCC
i
ibB
(8.180)
(8.181)
(8.182)
pathmaintheoffarethatonscontrubutiecapacitancallincludesCwhere off
pathlogicmaintheinecapacitanctheisCwhere path
(branching effort b at every branch point)
(total capacitance seen at every branch node)
(path branching effort when b > 1)
GHBF (8.183)(new path effort including branching effort)
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
Gate Delays Driving Large Capacitive Loads Logical Effort BiCMOS Drivers
Introduction to VLSI Circuits and Systems, NCUT 2007
BiCMOS Drivers BiCMOS is a modified CMOS technology that includes bipolar junction tran
sistors as circuit elements
Used to drive high-capacitance line in digital design
More expensive, and have an intrinsic voltage drop that cannot be avoided making them undesirable for low-voltage application
Introduction to VLSI Circuits and Systems, NCUT 2007
BJT Characteristics
A Bipolar Junction Transistor (BJT)» 3-terminal element, pnp and npn» npn is faster than pnp because electrons are faster th
an holes» Forward-active bias
For amplification and controlled current flow, and is used for analog circuits
» Reverse-active bias In this case, large current can flow through the device but
the transistor does not control the values
» Saturation (can be used in digital as closed switch)
» Cutoff Can be modeled as an open switch
Figure 8.21 npn BJT
Figure 8.22 Operating regions
of the BJT
00 BCBE VandV
00 BCBE VandV
00 BCBE VandV
(a) Symbol (b) Structure
(a) Symbol and parameters
(b) Operating
regions
00 BCBE VandV
Introduction to VLSI Circuits and Systems, NCUT 2007
Forward-active Bias of BJT
Bipolar are faster than MOSFETs but are more complicated to build into an integrated circuit
» Why a BJT can provide faster switching?» In forward-active bias
» In Figure 8.24
1, FEFC whereII
th
BE
V
V
SC eII
where Is is the saturation current and Vth is the thermal voltage
th
BE
V
V
Sout
outC eIdt
dVCI
outC
out
CI
Vt
The values of IC can reach 10 mA to hundreds of mA!
Figure 8.24 Discharge of a capacitor using a
BJT
Figure8.23 Forward-active bias in a BJT
(8.188)
(8.189)
(8.190)
(8.191)
Introduction to VLSI Circuits and Systems, NCUT 2007
Diffuse Mechanism
A BJT accomplishes the task faster than a FET that occupies the same area, making BiCMOS attractive
» Since current flow through a BJT is due to the mechanism of particle diffusion, not electric field aided motion as in a FET
aBB
inES Nx
nDqAI
2
Electrons diffuse through the base
Where AE [cm2] is the emitter area, Dn [cm2/sec] is the electron diffusion coefficient in the base and is a measure of the diffusive motion, q is the electron charge, and NaB [cm-3] is the acceptor doping in the base
(8.192)
Figure 8.25 Forward-bias operation
Figure 8.26 An integrated bipolar junction transistorFigure 8.27 Cutoff and saturation in a
BJT
(a) Cutoff
(b) Saturation
Introduction to VLSI Circuits and Systems, NCUT 2007
Driver Circuits
BiCMOS circuits employ CMOS logic circuits that are connected to a bipolar output driver stage
» CMOS network provides logic operation and drive the output bipolar transistors Q1 and Q2
» Only one BJT is active at a time» An inverter BiCMOS
Figure 8.28 General form of a BiCMOS circuit
Figure 8.29 An inverter BiCMOS driver circuit Figure 8.30 DC analysis of the output
voltages
(a) VOH circuit (b) VOL circuit
)(satBEDDOH VVV )(satBEOL VV (8.193) (8.194)
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