waveguide high-speed circuits and systems laboratory b.m.yu high-speed circuits and systems...
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High-Speed Circuits and Systems Laboratory
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Waveguide
High-Speed Circuits and Systems Laboratory
B.M.Yu
High-Speed Circuits and Systems Laboratory
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Content
1. Overview
2. Introduction
3. Design and fabrication
I. Simulation
II. measurement
4. Waveguide loss measurement
5. Coupling between shallow-ridge and narrow strip
6. Conclusion
High-Speed Circuits and Systems Laboratory
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Overview
Optics Express (2010), Low Loss Shallow-Ridge Silicon Waveguide, Po Dong
Buried Oxide: 3 um, Cross section of waveguide: 0.25 um x 2 um
Target : Chip to Chip interconnect (a few tens of centimeter)
Average propagation loss: 0.2740.008 dB/cm in C-band (1530~1565 nm)
Double-level taper: to adiabatically couple from shallow ridge to strip waveguide
Cross section of WG
3 um
2 um
0.25 um
High-Speed Circuits and Systems Laboratory
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Introduction
Silicon photonics: interest area for broad spectrum applications (opti-cal interconnect, sensing, RF photonics)
Submicron wide deeply etched waveguide structures- Efficient and high speed active photonic devices- SOI substrates (Top silicon thickness: 0.25 um)- Lowest propagation loss (in previous reports): 1~2 dB/cm @ 1550
nm - Chip to Chip interconnect & Narrow bandwidth filters in RF photon-
ics
Shallow ridge or thin silicon waveguide- Propagation loss: 0.3~1 dB/cm (selective oxidation fabrication
technique) - Difficult to control (device density, hard mask thickness, cross
section of WG)
In this paper- Low loss silicon ridge WG: 0.25 um silicon, average propagation
loss: 0.274 dB/cm
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Design and Fabrication
- Main reason of waveguide propagation loss: light scattering from etch
sidewalls
Minimizing optical field overlap with etched interface (increasing width
of WG,
decreasing etch depth)
- Cross section of wave guide: 2 um x 0.25 um (etch depth: 0.05 um)
- Power confinement: 84 %
Etch sidewall of WG Shallow-ridge WG
Simulation
High-Speed Circuits and Systems Laboratory
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Design and Fabrication
Group index: ~3.7, effective index: ~2.9
- Etch depth tolerance 0.01 um
- Group index variation: 0.0033 5ps delay time difference (50cm waveguide)
40Gbps with a reasonable fabrication tolerance
Simulation
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Design and Fabrication
Bending loss
- 90 bending with various radii (50~120 um)
- @ 100um radii 10-4dB
Simulation
bending loss with various bending radii
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Design and Fabrication
SEM image of WG cross section Top-view of 64 cm waveguide
- Soitec 6” wafers
- 0.25 um thick silicon 3um buried oxide
- Spiral waveguide (rmin= 300 um)
- 6 mm x 3 mm waveguide (length of waveguide: 64cm)
6 mm
3 mm
Fabrication
High-Speed Circuits and Systems Laboratory
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Waveguide loss measurement
Test setup
ASE ( =1550 nm)
Optical spectrum analyzer
Optical fiber (TE mode Polarization)
Waveguide(horizontal taper)
Optical fiber
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Waveguide loss measurement
Insertion loss measured for different WG length as a function of wavelength
Waveguide propagation loss using linear fitting @ =1550 nm
- Insertion loss is normalized to power measured from direct
to direct fiber coupling
- Insertion loss = waveguide propagation loss + coupling loss
- Waveguide loss: 0.281dB/cm (@ =1550 nm)
Loss measurement
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Waveguide loss measurement
Loss measurement
Waveguide propagation loss as a function of wavelength in C-band
Waveguide loss with 9 chip on the same 6” SOI wafer
- Average loss ( variation): 0.274 dB/cm 0.008 dB/cm
- Same wafer but different average loss etch depth variation
- Average loss (same wafer): 0.299 dB/cm
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Coupling between shallow-ridge and narrow strip WG
Double level taper
- Narrow strip WG (450 nm x 250 nm): 1.5 um bending radius
- In Ring modulator, narrow strip WG is more efficient.
- Coupling would be need
Coupling between shallow-ridge and narrow strip waveguide
3-D simulation result
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Coupling between shallow-ridge and narrow strip WG
Simulation result
Coupling loss as a function of taper length
- 10um long taper is sufficient in order to achieve <0.25 dB coupling loss
- Highly index contrast between silicon and oxide