lecture digital integrated circuits chapter5 [호환 모드]

Digital Integrated Digital Integrated Digital Integrated Digital Integrated CircuitsCircuits

The InverterThe Inverter

The CMOS InverterThe CMOS InverterThe CMOS InverterThe CMOS InverterAnalysisVDD Analysis

Inverter complex gate

Costcomplexity & AreaVin Vout

Integrity and robustnessStatic behavior

PerformanceDynamic response

E ffi iEnergy efficiencyEnergy & power consumption

CMOS InverterCMOS InverterCMOS InverterCMOS InverterVDD

N Well

PMOS 2λVDD

PMOSContacts

Polysilicon

In OutMetal 1

GNDNMOS

Two InvertersTwo InvertersShare power and groundShare power and ground

Abut cells

Connect in MetalVDD

CMOS InverterCMOS InverterFirstFirst--Order DC AnalysisOrder DC Analysis

VDD VDD

VOL = 0VOH = VDD

VOH VDDVM = f(Rn, Rp)Vout

Vi = VDD Vi = 0

Vin = VDD Vin = 0

CMOS Inverter: Transient ResponseCMOS Inverter: Transient Responsepp

V DDV DD

tpHL = f(Ron.CL)R p

V DDDD

pHL on L= 0.69 RonCL

V outVout

R n Ex)Rp or Rn ~ 수 KΩCL ~ 수십 fF

V in = V DDV in = 0

(a) Low-to-high (b) High-to-low

L 수tpHL=0.69RC ~ 수십ps

( ) g ( ) g

Voltage TransferVoltage TransferCh t i tiCh t i tiCharacteristicCharacteristic

PMOS Load LinesPMOS Load LinesPMOS Load LinesPMOS Load Lines

IDp IDnVin=0

IDnVin=0

VDSp VDSp

Vin=1.5

VGSp=-2.5

VGSp=-1p

Vin = VDD+VGSpIDn = - IDp

Vout = VDD+VDSp

Mirror around x-axis Shift over VDD

CMOS Inverter Load CharacteristicsCMOS Inverter Load CharacteristicsCMOS Inverter Load CharacteristicsCMOS Inverter Load Characteristics

IDnVin = 2.5Vin = 0

Vin = 2Vin = 0.5 NMOSPMOS

Vin = 1.5Vin = 1

V = 0 5

Vin = 1Vin = 1.5

V = 2Vin = 1Vin = 1.5

Vin = 0

Vin = 0.5Vin 2

Vin = 2.5

CMOS Inverter VTCCMOS Inverter VTCCMOS Inverter VTCCMOS Inverter VTC

NMOS offPMOS res

22 NMOS sat

PMOS res1.

5 NMOS satPMOS sat

NMOS resPMOS t

0.5 NMOS res

PMOS offPMOS sat

Vin0.5 1 1.5 2 2.5

Switching Threshold as a function of Switching Threshold as a function of Transistor RatioTransistor Ratio

100 1010.8

W /WWp/Wn

Switching ThresholdSwitching ThresholdSwitching ThresholdSwitching Threshold

Determining VDetermining V and Vand VDetermining VDetermining VIHIH and Vand VILILVout

g = inverter gain

V VOL VIL VIH

A simplified approach

Inverter GainInverter GainInverter GainInverter Gain0

-10gain

0 0.5 1 1.5 2 2.5-18

Vin (V)

Gain as a function of VGain as a function of VGain as a function of VGain as a function of VDDDD

t(V 17%

0 0 05 0 1 0 15 0 20

Gain=-110%

0 0.05 0.1 0.15 0.2V

in (V)

0 0.5 1 1.5 2 2.5V

in (V)

Impact of Process VariationsImpact of Process VariationsImpact of Process VariationsImpact of Process Variations2.5

2Good PMOSB d NMOS

Bad NMOS

Nominal

Good NMOSBad PMOS

0 0.5 1 1.5 2 2.50

Vin (V)

Propagation DelayPropagation DelayPropagation DelayPropagation Delay

CMOS Inverter Propagation DelayCMOS Inverter Propagation DelayA h 1A h 1Approach 1Approach 1

tpHL = CL Vswing/2tpHL CL Vswing/2

Vout CL~

CLIav kn VDD

Vin = VDD

CMOS Inverter Propagation DelayCMOS Inverter Propagation DelayA h 2A h 2Approach 2Approach 2

tpHL = f(Ron.CL)pHL ( on L)= 0.69 RonCL

Vout ln(0.5)

CLVDD1

Vin = VDDt

0.50.36

tRonCL

CapacitanceCapacitanceCapacitanceCapacitanceVDD VDD

M2M4Cdb2Cgd12

VVinVout

M1 M3Cdb1

Cw Cg3

Interconnect

Fanout

VoutVinSimplified

CLSimplified

CMOS InvertersCMOS InvertersCMOS InvertersCMOS InvertersVDD

PMOSPMOS

1.2 μm=2λ

Polysilicon

InMetal1

NMOSGND

Transient ResponseTransient Response3

tp = 0.69 CL (Reqn+Reqp)/2

tpLHtpHL

0 0.5 1 1.5 2 2.5

x 10-10

t (sec)

Design for PerformanceDesign for PerformanceDesign for PerformanceDesign for Performance

Keep capacitances smallIncrease transistor sizes (W/L)Increase transistor sizes (W/L)

watch out for self-loading! diffusion cap.Increase VDD (????)

VDD ↓Power ↓ but delay ↑S iti t d i i ti (E V )Sensitive to device variation (Ex. VT)Signal swing ↓ sensitive to external noise

Delay as a function of VDelay as a function of VDDDDDelay as a function of VDelay as a function of VDDDD

2.5t p(n

0 8 1 1 2 1 4 1 6 1 8 2 2 2 2 41

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4V

Device SizingDevice Sizing3 8

x 10-11

Device SizingDevice Sizing

tp=0.69Req(Cint+Cext)=0.69Req Cint (1+Cext/Cint)

t (1 C /C )

=tp0 (1+Cext/Cint)

Cint=S Ciref t =0 69(R /S)(S C )(1+C t/SC )

t p(sec

Self-loading effect:Intrinsic capacitances

tp=0.69(Rref/S)(S Ciref)(1+Cext/SCiref)

(for fixed load)

Intrinsic capacitancesdominate

2 4 6 8 10 12 142

NMOS/PMOS ratioNMOS/PMOS ratio5

x 10-11

NMOS/PMOS ratioNMOS/PMOS ratio

tpLH tpHL

tp β = Wp/Wn4

t p(se

Mi i t d l3.5 Minimum worst case delay for large cap. load

1 1.5 2 2.5 3 3.5 4 4.5 53

Minimum gate delay

Inverter SizingInverter SizingInverter SizingInverter Sizing

Inverter ChainInverter ChainInverter ChainInverter Chain

In Out

If CL is given:If CL is given:- How many stages are needed to minimize the delay?- How to size the inverters?

May need some additional constraints.

Inverter DelayInverter DelayInverter DelayInverter Delay

• Minimum length devices, L=0.25μm• Assume that for WP = 2WN =2W

• same pull up and pull down currents2W

• same pull-up and pull-down currents• approx. equal resistances RN = RP• approx. equal rise tpLH and fall tpHL delays Wapprox. equal rise tpLH and fall tpHL delays

• Analyze as an RC network

WW ⎞⎛⎞⎛−− 11

WNunit

PunitP RR

WWRR ==⎟⎟

⎞⎜⎜⎝

⎛≈⎟⎟

⎞⎜⎜⎝

tpHL = (ln 2) RNCL tpLH = (ln 2) RPCLDelay (D):

CWC 3© Digital Integrated Circuits2nd Inverter

unitunit

gin CWWC 3=Load for the next stage:

Inverter with LoadInverter with LoadInverter with LoadInverter with LoadD lDelay

L d (C )

R Load (CL)

tp = k RWCL

Assumptions: no load -> zero delayk is a constant, equal to 0.69

Inverter with LoadInverter with LoadInverter with LoadInverter with LoadD lC 2C DelayCP = 2Cunit

Cint CL

LoadCN = Cunit

Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)= Delay (Internal) + Delay (Load)

Delay FormulaDelay FormulaDelay FormulaDelay Formula

( )~ CCRDelay LintW +( )

( ) ( )/1/1 ftCCCkRt

y LintW

( ) ( )γ/1/1 0int ftCCCkRt pintLWp +=+=

Cint = γCgin with γ ≈ 1f C /C ff ti f tf = CL/Cgin - effective fanoutR = Runit/W ; Cint =WCunitt 0 = 0 69R itC it

tp0 0.69RunitCunit

Apply to Inverter ChainApply to Inverter ChainApply to Inverter ChainApply to Inverter Chain

In Out

CL1 2 N

tp = tp1 + tp2 + …+ tpN

⎞⎛⎟⎟⎠

⎞⎜⎜⎝

⎛+ +

jginunitunitpj C

1,1~γ ⎠⎝ jg

jjpp CC

ttt =⎟⎟⎠

⎞⎜⎜⎝

⎛+== +

+∑∑ 1,1

i jginj C ⎠⎝== 1 ,1 γ

Optimal Tapering for Given Optimal Tapering for Given NNOptimal Tapering for Given Optimal Tapering for Given NN

Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N

Minimize the delay, find N - 1 partial derivatives

R lt C /C C /CResult: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1

Size of each stage is the geometric mean of two neighborsSize of each stage is the geometric mean of two neighbors

1,1,, +−= jginjginjgin CCC

- each stage has the same effective fanout (Cout/Cin)- each stage has the same delay

Optimum Delay and Number of Optimum Delay and Number of StagesStages

/N CCFfWhen each stage is sized by f and has same eff. fanout f:

1,/ ginL CCFf ==

Effective fanout of each stage:

N Ff =

Minimum path delay

( )γ/10N

pp FNtt +=

ExampleExampleExampleExample

In Out

CL= 8 C1C11 f f2

CL/C1 has to be evenly distributed across N = 3 stages:

283 ==f

CL/C1 has to be evenly distributed across N 3 stages:

Optimum Number of StagesOptimum Number of StagesOptimum Number of StagesOptimum Number of Stages

For a given load, CL and given input capacitance CinFind optimal sizing f

fFNCfCFC in

NinL ln

ln with ==⋅=

( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛+=+=

FNtt pNpp ll

ln1/ 0/1

0γγ( ) ⎟

⎠⎜⎝ ffpp lnlnγ

01lnln0 =−−

⋅=∂ ffFtt pp γ 0

ln2∂ ff γ

For γ = 0 f = e N = lnF ( )ff γ+= 1exp

For γ 0, f e, N lnF ( )ff γ+1exp

Optimum Effective Fanout Optimum Effective Fanout ffOptimum Effective Fanout Optimum Effective Fanout ffOptimum f for given process defined by γ

( )ff γ+= 1exp

f 3 6fopt = 3.6for γ=1

Impact of SelfImpact of Self--Loading on Loading on ttImpact of SelfImpact of Self--Loading on Loading on ttpp

No Self-Loading, γ=0 With Self-Loading γ=1

(u) x=10,000

x=1000

1.0 3.0 5.0 7.0u

α=2.7 일반적으로 α=4

Buffer DesignBuffer Design ( )γ/1 N FNtt +=Buffer DesignBuffer DesignN f tp

( )γ/10pp FNtt +=

N f tp

1 64 65

1 8 64 2 8 18

1 644 16 3 4 15

1 642.8 8 22.6 4 2.8 15.3

Power DissipationPower DissipationPower DissipationPower Dissipation

Where Does Power Go in CMOS?Where Does Power Go in CMOS?Where Does Power Go in CMOS?Where Does Power Go in CMOS?• Dynamic Power Consumption• Dynamic Power Consumption

Charging and Discharging Capacitors

• Short Circuit Currents

• Leakage

Short Circuit Path between Supply Rails during Switching

• LeakageLeaking diodes and transistors

Dynamic Power DissipationDynamic Power DissipationDynamic Power DissipationDynamic Power DissipationVdd

Vin Vout

Energy/transition = CL * Vdd2

Power = Energy/transition * f = CL * Vdd2 * f

Not a function of transistor sizes!

Power Energy/transition f CL Vdd f

Vout 0 1되는주기

Need to reduce CL, Vdd, and f to reduce power.Not a function of transistor sizes!

Modification for Circuits with Reduced SwingModification for Circuits with Reduced Swing

Vdd -Vt

E0 1→ CL Vdd Vdd Vt–( )••=→

Can exploit reduced swing to lower power(e.g., reduced bit-line swing in memory)

Transistor Sizing for Minimum Transistor Sizing for Minimum EnergyEnergy In Out

1Cg1 fCext

Goal: Minimize Energy of whole circuitD i t f d VDesign parameters: f and VDD

tp ≤ tpref of circuit with f=1 and VDD =Vref

pp fFftt ⎟⎟

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛++⎟⎟

⎞⎜⎜⎝

⎛+= 0 11

DDp VV

−∝

⎠⎝ ⎠⎝⎠⎝

Transistor Sizing (2)Transistor Sizing (2)Transistor Sizing (2)Transistor Sizing (2)Performance Constraint (γ=1)(γ )

⎟⎟⎠

⎞⎜⎜⎝

−⎟⎟⎠

⎞⎜⎜⎝

VVVfFf

tt TEf

( ) ( ) 1330

⎠⎝−

⎠⎝=F

Energy for single Transition

( )( )[ ]

⎞⎛ ++⎟⎞

⎜⎛

FfCVE gDD

⎟⎠⎞

⎜⎝⎛

⎟⎟⎠

⎞⎜⎜⎝

ref 422

Transistor Sizing (3)Transistor Sizing (3)Transistor Sizing (3)Transistor Sizing (3)VDD=f(f) E/E =f(f)

VDD f(f) E/Eref=f(f)

0.5norm

1 2 3 4 5 6 70

f1 2 3 4 5 6 7

Short Circuit CurrentsShort Circuit CurrentsShort Circuit CurrentsShort Circuit CurrentsVdd

Vin Vout

Vin (V)5.04.03.02.01.00.0

How to keep ShortHow to keep Short--Circuit Currents Low?Circuit Currents Low?How to keep ShortHow to keep Short Circuit Currents Low?Circuit Currents Low?

Short circuit current goes to zero if tfall >> trise,but can’t do this for cascade logic so

but can t do this for cascade logic, so ...

Minimizing ShortMinimizing Short--Circuit PowerCircuit PowerMinimizing ShortMinimizing Short Circuit PowerCircuit Power8

Vdd =3.3

rmVdd =2.5

0 1 2 3 4 50

Vdd =1.50 1 2 3 4 5

tsin/tsout

LeakageLeakageLeakageLeakageVdd

Drain JunctionDrain JunctionLeakage

Sub-ThresholdCurrent

Sub-threshold current one of most compelling issuesin low-energy circuit design!

ReverseReverse--Biased Diode LeakageBiased Diode LeakageReverseReverse--Biased Diode LeakageBiased Diode Leakage

Reverse Leakage Current

IDL = JS × A

JS = 10-100 pA/μm2 at 25 deg C for 0.25μm CMOSJS doubles for every 9 deg C!

Subthreshold Leakage ComponentSubthreshold Leakage ComponentSubt es o d ea age Co po e tSubt es o d ea age Co po e t

Static Power ConsumptionStatic Power ConsumptionppVd d

Vin=5V CL

Pstat = P(In=1).Vdd . Istatstat (In 1) dd stat

Wasted energy …Should be avoided in almost all cases,but could help reducing energy in others (e.g. sense amps)

Principles for Power ReductionPrinciples for Power ReductionPrinciples for Power ReductionPrinciples for Power ReductionPrime choice: Reduce voltage!Prime choice: Reduce voltage!

Recent years have seen an acceleration in l lt d tisupply voltage reduction

Design at very low voltages still open question (0.6 … 0.9 V by 2010!)

Reduce switching activityReduce switching activityReduce physical capacitance

Device Sizing: for F=20– fopt(energy)=3.53, fopt(performance)=4.47

Impact ofImpact ofImpact ofImpact ofTechnology Technology gygyScalingScaling

Goals of Technology ScalingGoals of Technology ScalingGoals of Technology ScalingGoals of Technology Scaling

Make things cheaper:Want to sell more functions (transistors) per chip for the same moneysame moneyBuild same products cheaper, sell the same part for less moneyPrice of a transistor has to be reduced

But also want to be faster smaller lower powerBut also want to be faster, smaller, lower power

Technology ScalingTechnology ScalingTechnology ScalingTechnology Scaling

Goals of scaling the dimensions by 30%:Reduce gate delay by 30% (increase operating frequency by 43%)frequency by 43%)Double transistor densityReduce energy per transition by 65% (50% powerReduce energy per transition by 65% (50% power savings @ 43% increase in frequency

Di i d t i b 14%Die size used to increase by 14% per generation

Technology generation spans 2-3 years

Technology Evolution (2000 data)Technology Evolution (2000 data)Technology Evolution (2000 data)Technology Evolution (2000 data)

I i l T h l R d f S i dInternational Technology Roadmap for Semiconductors

1999 2000 20142011200820042001Year of

1999 2000

30406090130Technology node [nm]

20142011200820042001Introduction

1.5-1.8

109-10987Wiring levels

0.3-0.60.5-0.60.6-0.90.9-1.21.2-1.5Supply [V]

1.6-1.4

6 714.9-3.611-37.1-2.53.5-22.1-1.6Max frequency

[GHz],Local-Global

109 10987Wiring levels

18617717116013010690Max μP power [W]1.4 1.7 2.52.32.12.42.0Bat. power [W]

Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm

ITRS Technology Roadmap ITRS Technology Roadmap A l ti C tiA l ti C tiAcceleration ContinuesAcceleration Continues

Technology Scaling (1)Technology Scaling (1)Technology Scaling (1)Technology Scaling (1)10

Minimum Feature SizeMinimum Feature Size1960 1970 1980 1990 2000 2010

Minimum Feature SizeMinimum Feature Size

Technology Scaling (2) Technology Scaling (2) Technology Scaling (2) Technology Scaling (2)

Number of components per chipNumber of components per chip

Technology Scaling (3)Technology Scaling (3)Technology Scaling (3)Technology Scaling (3)

tp decreases by 13%/year50% every 5 years!50% every 5 years!

Propagation DelayPropagation Delay

p g yp g y

Technology Scaling (4)Technology Scaling (4)Technology Scaling (4)Technology Scaling (4)

x1.4 / 3 years1000

∝ κ 0.7

x4 / 3 year

100 ∝ κ 3

10r Den

MPU DSP

1011Po

(a) Power dissipation vs. year.

95908580Year

Scaling Factor κ （normalized by 4μm design rule）

(b) Power density vs. scaling factor.

Technology Scaling Models Technology Scaling Models Technology Scaling Models Technology Scaling Models

• Full Scaling (Constant Electrical Field)ideal model — dimensions and voltage scalegtogether by the same factor S

• Fixed Voltage Scalingmost common model until recently —only dimensions scale voltages remain constant

• General Scaling

only dimensions scale, voltages remain constant

gmost realistic for todays situation —voltages and dimensions scale with different factors

Scaling Relationships for Long Channel DevicesScaling Relationships for Long Channel Devicesg p gg p g

Transistor ScalingTransistor Scaling(velocity(velocity saturated devices)saturated devices)(velocity(velocity--saturated devices)saturated devices)

μμProcessor ScalingProcessor ScalingμμProcessor ScalingProcessor Scaling

P.Gelsinger: μProcessors for the New Millenium, ISSCC 2001

μμProcessor PowerProcessor PowerμμProcessor PowerProcessor Power

μμProcessor PerformanceProcessor PerformanceμμProcessor PerformanceProcessor Performance

P Gelsinger: μProcessors for the New Millenium ISSCC 2001

2010 Outlook2010 Outlook2010 Outlook2010 Outlook

Performance 2X/16 months1 TIP (terra instructions/s)( )30 GHz clock

SizeNo of transistors: 2 BillionDie: 40*40 mm

Power10kW!!Leakage: 1/3 active Power

Some interesting questionsSome interesting questionsSome interesting questionsSome interesting questions

What will cause this model to break?When will it break?When will it break?Will the model gradually slow down?g y

Power and power densityLeakageLeakageProcess Variation

lecture digital integrated circuits chapter5 [호환 모드]

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