qsys实验手册2014(快速入门 quartus13.0 64位win7)
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1Hello World
11
Nios II
12
PC Quartus II 13.0Nios II EDS 13.0 DE2-115
13
Hello World Nios II
Nios II EDS C FPGA
14
Stept1 Quartus II 13.0 1-1
1-1
Stept2
1 File/New Project Wizard 1-2
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1-2
1 E:/hello 2
3
hello
2
Next File ,
Next 1-3
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1-3
3
Family
Cyclone
EP4CE115F29C7 1-4
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1-4
4 1-4 Next
None
Quartus II
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5Next 1-5
1-5
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6
Finish 1-6
1-6
7
1-6 Assignments-Device Device and Pins Options
1-7 unused pins As input tri-stated. 1-7 OK
1-7
Stept3Nios II
1 ToolsQsys 1-8
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1-8
2 File-save, nios2_small 1-9
1-9
3
Nios II
1-9 Nios II System Contents
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Embedded Processors Nios II Processor Core Nios II 1-10
1-10
Nios II 3 Nios II/eNios II/s
Nios II/f 1-10
Hello World
Nios II/e
Reset Vector
Exception Vector
Nios II JTAG Debug Module
1-11 Nios II/eLevel 1 JTAG
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1-11
4 Finish 1-12 nios2_qsys_0,
clk_0 Rename clk_50.
1-12
5
Nios II System ContentsMemories and
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Memory Controllers On-Chip On-Chip-MemoryRAM or ROM
Total memory sizees 40960 40k
1-13
1-13
6 Finish Onchip-memory2_0 Rename onchip-memory
1-14
1-14
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7Nios II System ContentsInterface
Protocols Serial JTAG UART, 1-15 Finish
1-15
8 Nios II JTAG_UART jtag_uart_0
jtag_uart nios2_qsys_0 cpu, 1-16
1-16
Stept4Nios II
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1 1-17
1-17
ip instuction_master
(2)
cpu
Nios II
Reset Vector
ExceptionVector onchip_memory Finish 1-18
1-18
3 Nios II System-Create Global Reset Network
System-Assign Base addresses Nios II
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IRQ Avalon_jtag_slave IRQ jtag_uart
0
4
System Generation
Generate
save
generate complete
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5 1-19
1-19
4 close Quartus File-New Block Diagram/Schematic File
1-20
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1-20
5 1-20 OK Quartus Project
nios2_small 1-21 1-22
1-21
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generate pin for symbol ports,
1-22
(6) qip
Project-add/remove files in project,
nios2_small.qip add
7 OK, hello.bdf
1-23
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1-23
Stept5Nios II EDS
1 Tools-Niosii software Build for Eclipse Nios II DES 13.0 Workspace
1-24 OKNIOSii C
1-24
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2 Nios II C/C++ File-New- Nios II Application and BSP from Template
Hello World 1-25
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1-24
3 Target Hardware information sopcinfo hello_world
1-25
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1-25
4 FinishHello World hello_world.c 1-26
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1-26
(5) hello_world_bsp BSP Editor, BSP
Editor settings generate
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1-27
6 C Project-Build Project hello_world.c
console 1-28
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1-28
Stept6
1 Quartus II Tools-Programmer
/Nios II FPGA DE2-115 USB-Blaster
JTAG
1-29
Start
1-29
2 hello_world Run As-NiosII Hardware 1-30
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1-30
3 Nios II HardwareTarget Connection Refresh
Connections
1-31
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4 Apply Run C C
1-32 Hello from Nios II! Hello
World
1-32
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28
11
/PIONios II /
12
PC Quartus II 13.0Nios II EDS 13.0 DE2-115
13
8 Nios II
Nios II EDS C FPGA
14
Stept1 Quartus II , seg
1-1
Stept2 Tool-Qsys,
1 seg7
2pio seg7
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3 seg7 export seg7_external
()
4 seg7.qsys generate
Stept3 qip bdfBlock Schematic File,
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View-Utility windows-Tcl Console.
tcl
set_location_assignment PIN_Y2 -to CLOCK_50
set_location_assignment PIN_H22 -to HEX0[6]
set_location_assignment PIN_J22 -to HEX0[5]
set_location_assignment PIN_L25 -to HEX0[4]
set_location_assignment PIN_L26 -to HEX0[3]
set_location_assignment PIN_E17 -to HEX0[2]
set_location_assignment PIN_F22 -to HEX0[1]
set_location_assignment PIN_G18 -to HEX0[0]
set_location_assignment PIN_M23 -to KEY0
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Stept4
1 Tool-NIOSII SBT,
2 Nios II C/C++ File-New- Nios II Application and BSP from Template
seg7.sopcinfo SEG7blank
project.
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3 SEG7 seg_pio.c Ctrl+s
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4Ctrl+b run as
system ID
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#include
#include "system.h"
#include "io.h"
static unsigned char
azmap[]={ 0X40,0X79,0X24,0X30,0X19,0X12,0X02,0X78,0X00,0X10,0X08,0
X03,0X46,0X21,0X06,0X0E};
int main()
{
printf("Hello from Nios II!\n");
unsigned char i=0;
while(1)
{
for(i=0;i
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1 led18_pio ( data on-chip
memory )
2pio led18_pio
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4 led18_pio export led18_pio
()
5 led18.qsys generate
Stept3 qip bdfBlock Schematic File,
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Stept4
2 Tool-NIOSII SBT,
2 Nios II C/C++ File-New- Nios II Application and BSP from Template
led18.sopcinfo LEDblank
project.
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5 LED led.c Ctrl+s
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6Ctrl+b
#include "system.h"
#include "altera_avalon_pio_regs.h"
void delay (void);
int alt_main(void)
{
unsigned int led_data;
unsigned int led_code;
while(1)
{
for(led_data=0;led_data
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{i--;}
}
4
11
/
12
PC Quartus II 13.0Nios II EDS 13.0 DE2-115
13
Nios II
Nios II EDS C FPGA
14
Stept1 Quartus II , key1
1-1
Stept2 Tool-Qsys,
1 seg_pio,key12pio seg_pio
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(3pio key1
5 seg_pio export seg_pio key1 export key1,
()
6 key.qsys generate
Stept3 qip bdfBlock Schematic File,
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Stept4
3 Tool-NIOSII SBT,
2
Nios II C/C++
File-New- Nios II Application and BSP from Template
key.sopcinfo KEY blank
project.
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7 KEY key.c Ctrl+s
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8Ctrl+b run as
system ID
/*
* key.c
*
* Created on: 2014-7-29
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* Author: Administrator
*/
#include"stdio.h"
#include"altera_avalon_pio_regs.h"
#include"sys/alt_irq.h"
#include"alt_types.h"
volatile alt_u32 edge_capture;
static void key1_interrupts(void * context,alt_u32 id)
{
volatile alt_u32 *edge_capture_ptr=(volatile alt_u32*)context;
*edge_capture_ptr=IORD_ALTERA_AVALON_PIO_EDGE_CAP(KEY1_BASE);
IOWR_ALTERA_AVALON_PIO_EDGE_CAP(KEY1_BASE,0);
}
static void init_button_pio()
{
void *edge_capture_ptr=(void*)&edge_capture;
IOWR_ALTERA_AVALON_PIO_IRQ_MASK(KEY1_BASE,0xf);
IOWR_ALTERA_AVALON_PIO_EDGE_CAP(KEY1_BASE,0x0);
alt_irq_register(KEY1_IRQ,edge_capture_ptr,key1_interrupts);
}
int main(void)
{alt_u8 count,seg_code;
alt_u8 code_table[]={0x40,0x79,0x24,0x30,0x19,0x12,0x02,0x78,0x00,0x10,
0x08,0x03,0x46,0x21,0x06,0x0e,0x0c,0x18,0x09,0x3f};
init_button_pio();
IOWR_ALTERA_AVALON_PIO_DATA(SEG_PIO_BASE,code_table[0x0f]);
while(1)
{
while(edge_capture)
{edge_capture=0;
if(count
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5 PWM
11
PWM
12
PC Quartus II 13.0Nios II EDS 13.0 DE2-115
13
PWM LED Nios II
Nios II EDS C
FPGA
14
Stept1 Quartus II ,pwm
Stept2 File-New, Verilog pwm_ip.
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module pwn_ip(
clk,reset_n,
chipselect,
address,
write,
writedata,
read,
byteenable,
readdata,
PWM_out);
input clk;
input reset_n;
input chipselect;
input [1:0]address;
input write;
input [31:0] writedata;
input read;
input [3:0] byteenable;
output [31:0] readdata;output PWM_out;
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reg [31:0] clock_divide_reg;
reg [31:0] duty_cycle_reg;
reg control_reg;
reg clock_divide_reg_selected;reg duty_cycle_reg_selected;
reg control_reg_selected;
reg [31:0] PWM_counter;
reg [31:0] readdata;
reg PWM_out;
wire pwm_enable;
//
always @ (address)
begin
clock_divide_reg_selected
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if(byteenable[2])
clock_divide_reg[23:16]=writedata[23:16];
if(byteenable[3])
clock_divide_reg[31:24]=writedata[31:24];
endend
end
// PWM
always @ (posedge clk or negedge reset_n)
begin
if(reset_n==1'b0)
duty_cycle_reg=0;
else
begin
if(write & chipselect & duty_cycle_reg_selected)
begin
if(byteenable[0])
duty_cycle_reg[7:0]=writedata[7:0];
if(byteenable[1])
duty_cycle_reg[15:8]=writedata[15:8];
if(byteenable[2])
duty_cycle_reg[23:16]=writedata[23:16];
if(byteenable[3])duty_cycle_reg[31:24]=writedata[31:24];
end
end
end
//
always @ (posedge clk or negedge reset_n)
begin
if(reset_n==1'b0)
control_reg=0;
else
begin
if(write & chipselect & control_reg_selected)
begin
if(byteenable[0])
control_reg=writedata[0];
end
end
end
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//
always @ (address or read or clock_divide_reg or duty_cycle_reg or control_reg or chipselect)
begin
if(read & chipselect)
case(address)2'b00:readdata=clock_divide_reg)
PWM_counter
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else
PWM_out
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2 File + Synthesis File
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3 pwm_ip.v Analyze SynthesisFiles
4 Signals PWM_out
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5 interface Reset
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6 finish Yes
7 Qsys pwm_ip
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8
9pwmcpu.qsys generate
Stept3 qip bdfBlock Schematic File,
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Stept4
4 Tool-NIOSII SBT,
2
Nios II C/C++
File-New- Nios II Application and BSP from Template
pwmcpu.sopcinfo PWM
blank project.
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9 PWM pwm.c Ctrl+s
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Ctrl+b
/*
* pwm.c
*
* Created on: 2014-8-6
* Author: Administrator
*/
#include
#include "system.h"
#include
//PWM
typedef struct{
volatile unsigned int divi;
volatile unsigned int duty;
volatile unsigned int enable;
}PWM;
int main()
{
int dir = 1;
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//pwmPWM_0_BASE
PWM *pwm = (PWM *)PWN_IP_0_BASE;
//pwm,divi232-1
pwm->divi = 1000;
pwm->duty = 0;
pwm->enable = 1;
printf("Hello from Nios II!\n");
//dutyLED
while(1){
if(dir > 0){
if(pwm->duty < pwm->divi)
pwm->duty += 100;
else
dir = 0;
}
else{
if(pwm->duty > 0)
pwm->duty -= 100;
else
dir = 1;
}
usleep(100000);
}
return 0;
}
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