vlsi design full-custom ic design flow

VLSI Design

Full-custom IC Design Flow

Introduction to VLSI Circuits and Systems積體電路概論

賴秉樑Dept. of Electronic Engineering

National Chin-Yi University of Technology

Fall 2007

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Outline

Schematic with Composer of ICFB (Cadence)Pre-simulation using HspiceLayout with Virtuoso or LakerVerification using Calibre or Dracula

DRC LVS PEX

Post-simulation using Hspice

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Custom IC Design

We offer the technology files of the following, and copy it to your home directory

Technology File Name Purpose

TSMC035

display.drf Virtuoso 圖層資料檔

035ms.tf 製程檔

mm0355v.l Spice model file

Laker ( a directory) Laker 圖層資料檔

calibre.drc DRC

calibre.lvs LVC

calibre.pex PEX

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Environment

Operation System: Solaris 8 (Sun Blade 2500) Account is personal student’s identity number, ex. g955168 Using X-win32 or ReflectionX to remote WorkStation

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Console

家目錄

1. 目前 source license 的軟體

2. 可修改於 home dir/.cshrc

登入的 Shell is C-shell

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Schematic with Composer

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ICFB

Under home directory Mkdir work_tsmc035 ( 自設一個工作目錄 )

Under work_tsmc035 directory→ icfb &

Cadence 的 ICFB 控制視窗Under your design directory

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Merge Display File to Virtuoso

(1) ../technology/display.drf

(3) ./work_tsmc035/display.drf

(2) Add

加入後 Schematic & Layout view 才能正常顯示顏色與圖層

Key Step: Tools Display Resource Manger…

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建立新的製程 Library

不同的製程需新建不同製程技術的 library Step 1: Select File New Library Step 2: Name tsmc035_techfile (user-define) Step 3: ASCII Technology File ../technology/035ms.tf

Step 1 Step 2

Step 3

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建立新的 Design Library

Step 4: Select File New Library Step 5: Name basic_logic (usr-define) Step 6: Technology Library tsmc035_techfile

Step 5

Step 6

Step 4

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Create a Cellview under Design Library

建立一個 cell inv (inverter) Step 7: Select File New Cellview

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PMOS: pmos4NMOS: nmos4

加入 instance (hot key ‘i’)

Step 8: 呼叫 analogLib 建立基本的 instance

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完成 inverter 設計 (pmos, nmos, vdd, gnd and wire-connection)

加入 input and output (hot key ‘p’)

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Generating Netlist using CDL

Step 9: File Export CDL

Netlist 的副檔名為 name.sp

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Modify the inv.sp and Create a another inv_sim.sp

Delete

NM NCHPM PCH

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Pre-sim. using Hspice

進行 Hspice 時， netlist 與 Spice Model file mm0355v.l要在同一個目錄下

Console soclab02% hspice inv_sim.sp

路徑要注意 !

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Ctrl+a 可將波形視窗分割

確定 hspice job concluded soclab02% awaves & Step 10: Open

Step 10

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觀察 inverter 的 input & output 電壓

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Waveform with Awaves

** 檢查 Pre-sim. 的結果與功能正常後才進行 layout**

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Layout with Virtuoso Editor

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Layout with Virtuoso Editor

Step 1

Step 1: Link Calibre into Virtuoso (load(“/usr/mentor/Calibre_ss/cur/lib/calibre.skl”)

Step 2: File New Cellview

Step 2

Under the same library and cell name

Select Virtuoso, and View Name is layout

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Virtuoso Layout Window

Make sure linking Calibre success!

LSW: 供可選擇之 layer ，如無法正常顯示顏色，請重做 Display resource manger (Merge display.drf)

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N-Well COMS Inverter

The cross-section view and layout of a CMOS(n-well) inverter

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TSMC035 Minimum Design Rule with COMS Inverter

Minimum N-Well width 1.7 um

Minimum Metal1 extension of Contact 0.15 um

Contact size 0.4 * 0.4 um

Minimum N-Well extension of P+ Diffusion 1.2 um

Minimum Metal1 width 0.5 um

Minimum PIMP extension of P+ Diffusion 0.25 um

Minimum Diffusion width 0.3 um

Minimum NIMP extension of N+ Diffusion 0.25 um

Minimum Diffusion extension of Contact is 0.15 um

Minimum Contact to Contact spacing 0.4 um

Minimum Poly1 width 0.35 um

Minimum clearance from Contact on Diffusion region to a Poly gate 0.3 um

Minimum POLY1 extension of Diffusion 0.4 um

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An Inverter Layout

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Layout Verification with Calibre DRC/LVS/PEX

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Calibre DRC (5/1)

須先轉成 Layout 的 GDSII 的格式

Step 1: File Export Stream

Step 1

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Calibre DRC (2/5)

Step 2: Calibre Run DRC

Calibre DRC window

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Calibre DRC (3/5)

Step 3: Rules 將 TSMC035 的 calibre DRC rules file 加入

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Calibre DRC (4/5)

Step 4:Inputs Layout Files inv.gds ( 路徑要注意 )

可直接由 layout view 來執行，但電路假如很大，則需較久時間，一般 disalbe

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Calibre DRC (5/5)

Step 5:Run DRC 　 No error! 但可忽略的 design rule error 可查閱　“可允許之 DRC 錯誤 - 假錯 -申請者常犯錯誤”

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Calibre LVS (1/6)

Step 1: 修改 inv.sp 檔局部的 netlist 成 LVS 可過的形式

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Calibre LVS (2/6)

Step 2: Calibre Run LVS

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Calibre LVS (3/5)

Step 3: Rules 將 TSMC035 的 calibre LVS rules file 加入

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Calibre LVS (4/6)

Step 4:Inputs Layout Files inv.gds ( 路徑要注意 )

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Calibre LVS (5/6)

Step 4:Inputs Netlist Files inv.sp ( 路徑要注意 )

可直接由 schematic view 來執行，但電路假如很大，則需較久時間，一般 disalbe

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Calibre LVS (6/6)

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Calibre PEX (1/8)

Step 1: 修改 inv.sp 檔局部的 netlist 成 PEX 可過的形式

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Calibre PEX (2/8)

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Calibre PEX (3/8)

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Calibre PEX (4/8)

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Calibre PEX (5/8)

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Calibre PEX (6/8)

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Calibre PEX (7/8)

進行 RC值萃取

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Calibre PEX (8/8)

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Modify inv_pex.sp

inv_pex.sp.inv.pxi & inv_pex.sp.pex 為存放 PEX 萃取出後的 RC 參數值

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inv_pex.sp.inv.pxi & inv_pex.sp.pex 為存放 PEX 萃取出後的 RC 參數值

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Post-simulation Result

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附錄 : Layout with Laker Editor

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Laker

g9556168% laker &

開啟 Laker

建立新專案

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檔案存放路徑

專案名稱

製程檔

建立新檔

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選擇專案

檔案名稱Working Window

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將 Layer Table 置於左視窗

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Change GridCIC 的 Grid 為 0.025um

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2NAND

建立 Transistor

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PMOS的Body

NMOS的Body

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Stream Out

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Stream In

專案名稱

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COMS Inverter