reversible vedic multiplier - manisha · pdf filedigital vlsi design vlsi design lab abv-iiitm...

Digital VLSI designVLSI Design Lab

ABV-IIITM Gwalior

Reversible Vedic Multiplier

• Neelam Arya(2011VLSI-02)• Priyanka Mishra(2011VLSI-05)• Shweta Singh(2011VLSI-13 )

5 September 20121

Under Guidance of

Dr. Manisha Pattanaik


ABV-IIITM Gwalior

Existing Multiplication Algorithms

• Shift/Add Multiplication Algorithm• Booth’s Recoding• High Redix Multiplier• Tree and Array Multiplier

These Multiplication Algorithms Differ in the means of Partial product generation and partial product addition.

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Vedic Multiplication Algorithm

• Urdhva Tiryakbhyam• It is the multiplication sutra (algorithm) in Vedic mathematics.Urdhva

means vertical.• Triyagbhyam means Crosswise• The multiplier is based on an algorithm Urdhva Tiryakbhyam (Vertical

and Crosswise) of ancient Indian Vedic Mathematics. Urdhva Tiryakbhyam Sutra is a general multiplication formula applicable to all cases of multiplication. It literally means vertically and crosswise. It is based on a novel concept through which the generation of all partial products can be done with the concurrent addition of these partial products. The algorithm can be generalized for n x n bit number.

•••

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Steps of Urdhva Tiryakbhyam Sutra(Algorithm)

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Extension of VedicMultiplication Algorithm into

Conventional Logic

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Two Logic Blocks are needed to implement 4-bit multiplier

• Four 2*2 Multiplier blocks

• Three 4-bit Full Adder blocks


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Architecture

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Simulation Result

Total Delay Time 12.735ns(8.559ns Logic ,4.177ns Route)(67.2%Logic,32.8%Route)

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Complexity Issue

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•As we will realize higher bit multiplier, complexity increases. Example:-for designing 8-bit multiplier, 4-bit multiplier blocks are used along with 8-bit adders. This increases the gate level complexity by 5 times and the delay time also increases by approx.2 times.

•Therefore we can conclude that realization of higher bit multipliers will need larger gate complexity and increased delay.


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Design Optimization

• 2-bit Multipliers are designed using partial product generation method instead of conventional k-map method.

• 4-bit full adders are replaced with combination of full adder, half adder and xor gates.

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Implementation of Vedic Multiplier in Reversible Logic

• The multiple output Boolean function F (x1 , x2 , ..., xn ) of n Boolean variables is called reversible if

• The number of outputs is equal to the number of inputs;• Maps each input assignment to unique output assignment and vice

versa.

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Basic Reversible Gates Used

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• Quantum Cost 6• Used as a full adder


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• Quantum Cost 4• Used as AND gate and Half Adder


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•Quantum Cost 1•Used as copy gate and xor gate


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Reversible Circuit

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Important Parameters in Reversible Logic Circuit Designing

• Number of constant inputs (Gin): The inputs that are added to an n*k function to make it reversible are called constant inputs.

• Number of garbage outputs (Gout): Garbage outputs are some outputs that are not used for further computations in the circuit.

• Number of Gates (NOG): The number of reversible gates used to realize the function.

• Quantum Cost (QC): The Quantum Cost (QC) of a reversible circuit is defined as the number of 1*1 or 2*2 reversible quantum or logic gates that are needed to realize the circuit.

• Total logical calculations (circuit cost): One of the main factors of a circuit is its hardware complexity.

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• α = A two input EX-OR gate calculation• β = A two input AND gate calculation• δ = A NOT calculation• T = Total logical calculation

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Circuit parameters

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Circuit Optimization

• 2-bit multilpier is realized using partial products (earlier 2-bit multilpier is realized using k-map boolean equations).

• To reduce garbage output and constant inputs, toffoli gate is used in 2-bit multiplier circuit.

• Half adder gates (peres gates) and 2-cnot gate(xor gate) is used in circuit where no carry is generated in the circuit and

• hence full adder gate can be replaced with them.

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Optimization of 2*2 Multiplier

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Optimization of 4-bit full adder

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Results and Comparison

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Conclusions

• Low Delay• Quantum Cost, GO , No of Gates in

acceptable limit.• Regularity in structure.

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References:

• Dr. K.S. Gurumurthy , M.S Prahalad,“Fast and Power Efficient 16X16 Array of Array Multiplier using Vedic Multiplication”,Microsystems Packaging Assembly and Circuits Technology Conference (IMPACT), 2010 5th

International, 20-22 Oct. 2010,pp 1 - 4 .• Haghparast, M., S.J. Jassbi, K. Navi and O. Hashemipour,

2008 “Design of a novel reversible multiplier circuit using HNG gate in nanotechnology”, World Appl. Sci. J., 3(6): 974-978.

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