asynchronous serial communication -- eia rs232...

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Embedded System Lab. II Device Driver in Linux Device Driver in Linux 경희대학교 컴퓨터공학과 조진성 Embedded System Lab. II 1 주요내용 주요내용 UART 이해 LCD 이해 Ethernet 이해 USB 이해 Embedded System Lab. II 2 Asynchronous Serial Communication -- UART Universal asynchronous receiver/transmitter Transmit bits in a single channel simplex (one way) half-duplex (one direction at a time) full-duplex (two way) A sequence of bits – packet or character ASCII code – 7 bits for 128 characters (alphabet, numerical, and control) fixed length or variable length Start, stop, and parity bits Embedded System Lab. II 3 EIA RS232 Connection and signal characteristics Data terminal equipment and data communication equipment Logic '1' (marking) – -3v to -25v with respect to signal ground Logic “0” (spacing) – +3v to +25v Not assigned –between -3v and +3v (a transition region)

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Embedded System Lab. II

Device Driver in LinuxDevice Driver in Linux

경희대학교 컴퓨터공학과

조 진 성

Embedded System Lab. II 1

주요내용

주요내용

UART 이해LCD 이해Ethernet 이해USB 이해

Embedded System Lab. II 2

Asynchronous Serial Communication --UART

Universal asynchronous receiver/transmitterTransmit bits in a single channel

simplex (one way)half-duplex (one direction at a time)full-duplex (two way)

A sequence of bits – packet or characterASCII code – 7 bits for 128 characters (alphabet, numerical, and control)fixed length or variable lengthStart, stop, and parity bits

Embedded System Lab. II 3

EIA RS232Connection and signal characteristicsData terminal equipment and data communication equipmentLogic '1' (marking) – -3v to -25v with respect to signal ground Logic “0” (spacing) – +3v to +25vNot assigned –between -3v and +3v (a transition region)

Embedded System Lab. II 4

RS232(2)

Flow control (handshaking) signals to avoid buffer overflow or lock-up.RTS : to prepare the DCE device for accepting transmissionCTS : to inform the DTE device that transmission may beginDCD: data carrier detectedDSR: DCE readySG: system groundDTR: DTE ready

DTE FEP DB25 DCE MOD DB25

1 FG --------------- 1 FG

2 TX --------------> 2 TX

3 RX <-------------- 3 RX

4 RTS --------------> 4 RTS

5 CTS <-------------- 5 CTS

6 DSR <-------------- 6 DSR

7 SG --------------- 7 SG

8 DCD <-------------- 8 DCD

20 DTR --------------> 20 DTR

Embedded System Lab. II 5

Signal Format for ASCII Character

data, start, stop, and (even or odd) parity bits

Embedded System Lab. II 6

UART(1)

PC Com Port - EIA-574

RS-232 pin out DB-9 pin used for Asynchronous Data

Embedded System Lab. II 7

UART(2)

Is Your Interface a DTE or a DCE?Find out by following these steps: The point of reference for all signals is the terminal (or PC).① Measure the DC voltages between (DB25) pins 2 & 7 and between pins 3 & 7. Be

sure the black lead is connected to pin 7 (Signal Ground) and the red lead to whichever pin you are measuring.

② If the voltage on pin 2 (TD) is more negative than -3 Volts, then it is a DTE, otherwise it should be near zero volts.

③ If the voltage on pin 3 (RD) is more negative than -3 Volts, then it is a DCE.④ If both pins 2 & 3 have a voltage of at least 3 volts, then either you are measuring

incorrectly, or your device is not a standard EIA-232 device. Call technical support.

⑤ In general, a DTE provides a voltage on TD, RTS, & DTR, whereas a DCE provides voltage on RD, CTS, DSR, & CD.

Embedded System Lab. II 8

UART(3)

This is a standard 9 to 25 pin cable layout for async data on a PC AT serial cable

from Modem229RIRing Indicator

from Modem58CTSClear to Send

from Terminal/Computer47RTSRequest to Send

from Modem66DSRData Set Ready

from Modem75SGSignal Ground

From Terminal/Computer204DTRData Terminal Ready

from Terminal/Computer23TDTransmit Data

from Modem32RDCarrier Detect

from Modem81CDCarrier Detect

Source DTE or DEC25-pin DCE

9-pin DTE

SignalDescription

Embedded System Lab. II 9

UART(4)

CSCBSecondary Clear to Send13

CSecondary Rcvd. Line Sig. Detector12

Undefined11

CCFRcvd. Line Signal Detector8

ABSingnal Gnd/Common Return7

CCCSignal Set Ready6

CCBClear to Send5

C(Control)CARequest Data4

DBBReceived Data3

D(Data)BATransmitted Data2

AAFrame Ground1

ToDCE

FromDCE

EIACKT

DescriptionPin

Undefined25

TCHData Sig. Rate Selector(DTE)24

CCCIData Sig. Rate Selector(DCE)23

CCERing Indicator22

CCGSig. Quality Detector21

CCDData Terminal Ready20

CSCASecondary Request to Send19

Undefined18

TDDReceived Sig. Element Timing17

DSBBSecondary Received Data16

T(Timing)DBTransmitted Sig.Element Timing

15

DSBASecondary Transmitted Data14

ToDCE

FromDCE

EIACKT

DescriptionPin

RS-232 interfaceRS-232(EIA Std.) applicable to the 25 pin interconnection of Data Terminal Equipment (DTE)and Data Communication Equipment (DCE) using serial binary data

Embedded System Lab. II 10

UART(5)

RS232D used RJ45 type connectors(similar to telephone connectors)

RTSRequest To Send8

CTSClear To Send7

TxDTransmitted Data6

RxDReceived Data5

SGSignal Ground4

DTRDTE Ready3

DCDReceived Line Signal Detector2

DSR/RIDCE Ready, Ring Indicator1

DCEDTEAbbr.Signal DescriptionPin No.

Embedded System Lab. II 11

Liquid Crystal Display(1)LC(액정)란?일정온도범위에서유동성을지닌액정상태를말함

동시에광학적으로복굴절성을나타내는결정임

보통물질은용융온도에서고체로부터투명한액체로변화하지만, 액정물질은용융온도에서우선불투명하고혼탁한액체로일단변화하고그후더욱온도를올리면보통의투명한액체로변화한다.액정이란명칭은고체상과액체상의중간상태인액정상을가리키는경우와이러한액정상을갖는물질그자체를가리키는경우의두가지의미로사용되고있다.

액정물질의온도변화에의한상태변화

Embedded System Lab. II 12

Liquid Crystal Display(2)LCD액정의특성을이용해만드는디스플레이

LCD 특징장점저소비전력(수∼수십μW/cm2)으로장시간의전지구동이가능한에너지절약형이다.저전압에서동작(수∼10V)하므로직접 IC 구동이가능하고구동전자회로의소형화, 간략화가가능하다.

Embedded System Lab. II 13

Liquid Crystal Display(3)소자가얇고(수mm), 또한대형표시(수십 cm대각) 부터소형표시(수 mm대각)까지가능하다. 특히휴대형(portable) 기기에적합하다.수광형표시이므로밝은장소에서도표시가선명하다.표시의컬러화가쉽기때문에표시기능의확대, 다양화가이루어질수있다.투사확대표시나집적표시가가능하여대화면표시 (수 m대각)가용이하다.

단점비발광형이므로반사형표시인경우어두운곳에서표시의선명함이떨어진다.선명한표시가요구되는경우또는컬러표시의경우후광(back light)을필요로한다.표시콘트라스트가보는방향에의존하는경우가많아서시각에제약을받는다.응답시간이주위온도에의존하기때문에저온동작(-30∼-40℃)에어려움이있다.

Embedded System Lab. II 14

LCD 용도및분류LCD의분류형태에따른분류

투사형 LCD직시형 LCD

구동방식에따른분류

전기적구동(electrically addressed) LCD광학적구동(optically addressed) LCD

Embedded System Lab. II 15

LCD 동작원리동작원리

'OFF' 상태는전압을가하지않은상태를나타내며, 편광판을통과한빛이액정의분자배열을따라꼬여지면서교차된다른편광판을통과하게된다. (즉전압을가하지않은상태에서는빛이통과한다.) 'ON' 상태는전압을가한상태를나타내며, 이때에는전계의방향을따라액정분자가일어서면서편광판을통과한빛을그대로교차된편광판에전달시킴으로써빛은편광판에의해차단된다. (즉전압을가하면빛이차단된다.)

전압을선택적으로인가함으로써상, 하판의전극모양에따라원하는도형또는문자를표시할수있게된다.

Embedded System Lab. II 16

LCD Hardware overview

MMU

PXA250 Core

PXA255

GP[27:0]

D[31:0]A[31:0]

GPIOGPIO Registers GP[27:0]

Bridge

Interrupt ControllerICIPICMRICLR

ICCRICFP

FIQ, IRQ

DMADMARegisters

LCD Controller

ADS 7843

Dynamic Memory Controller

SDCKE[1]SDCLK[1]SDCS[0]#SDRAS#

WE#SDCAS#

DQM[3:0]

MDCNFGMDCAS00MDREFR

LCD CON

LDD[15:0]L-FCLKL-LCLKL-PCLK

LCDControlRegisters

DCLKCS#DINBUSY

PENIRQ#DOUT

GP4

GP5GP26

X+X-

Y-Y+

Inverter Power

L-BIAS

E-PORT0[7:0] GP25E-PORTGP23

E-PORT0 7

TFT LCD & Touch screen

Embedded System Lab. II 17

이더넷(Ethernet)(1)Ethernet

Commonly used to refer to all carrier sense multiple access collision detection (CSMA/CD) LANS that generally conform to Ethernet specifications, including IEEE 802.3

Embedded System Lab. II 18

Ethernet(2)전자적인특성

신호방식(Signaling)기저대역 (Base-band)시스템

Manchester digital Encoding• 디지털대디지털부호화

• 극형 –이상부호화광대역 (Broadband)시스템

differential PSK• 디지털대아날로그부호화

전송속도(data rate)1~100Mbps

Embedded System Lab. II 19

Ethernet(3)Baseband: 디지털신호 (이경우맨체스터부호화를의미)표준

첫숫자는 Mbps 단위로데이터전송율10Base2: 얇은동축케이블이용, 최장길이는 185m10Base5: 굵은동축케이블이용, 최장길이는 500m10Base-F: 광케이블을이용10Base-T: Twisted Pair cable 이용

광대역 (Broadband):아날로그신호 (이경우에는 PSK)한가지표준: 10Broad36

Embedded System Lab. II 20

Ethernet(4)

IEEE 802

Embedded System Lab. II 21

프레임형식(Frame Format)Preamble(7바이트) - alert, timing, start synchronizationSFD(Start frame delimiter) -프레임시작DA(Destination address) -목적지주소SA(Source address) -발신지주소PDU 길이/유형802.2 프레임(PDU) - 46~1500 바이트길이CRC -오류검출정보, CRC-32

Ethernet(5)

Embedded System Lab. II 22

Ethernet(6)

제어(Control) 필드HDLC의제어필드와동일

I-Frame

S-Frame

U-Frame

P/F Poll/final bit

N(S) 프레임송신번호

N(R) 프레임수신번호

Code 비번호나감시코드

Embedded System Lab. II 23

Ethernet(7)ACCESS Method : CSMA/CD

Carrier Sense Multiple Access with Collision Detection : "Listen before talk" 방식

각 Node는 Common Line을계속적으로감시하면서 Data 송신기회감지전송감지 : Listen before talk

경쟁에의한엑세스로충돌발생가능 : Collision 발생시재전송충돌검출 : Listen while talk

구현이간단하지만, 트래픽부하가높을경우에충돌로인한망성능저하발생충돌회수가네트워크의성능을좌우

Embedded System Lab. II 24

Ethernet(8)

CSMA/CD 동작절차컴퓨터가전송을원할때는전송매체를감지하고있다가채널상에트래픽이있으면트래픽이끝날때까지기다리고, 신호가없으면즉시전송을개시

전송도중에도항상버스를감지해서충돌여부를감지하며, 충돌이발생하면즉시전송을중지, 다른스테이션에충돌을알리는 jamming 신호발생

jamming 신호전송이끝나면임의의시간동안대기하였다가다시처음부터시도

채널트래픽여부?

프레임 송신 요구

송신 개시

충돌검출?

충돌검출? jamming발생

송신완료 임의의 시간 대기

Yes

No Yes

No

Yes

No

Carrier Sense

Multi Access

Collision Dection

Embedded System Lab. II 25

Ethernet Hardware예

PXA255

MD(31:0)

T/F

T/F

Prim ary E thernet

Secondary E thernet

ADD R (15 :2)

D (31:0) D (31:0)

DIR OE#

Log icnCS1nCS2nCS3nCS4

RD_nWR

nPWEnOE

MA(25:0)nDQM(3:0)

W E#O E#A(15:2)DQ M (3:0)#

W E#O E#A(15:2)D Q M (3:0)#

nCS1nCS2

GPIO (0)

GPIO (1)

INTR0

INTR0

Ethernet ControllerSMSC 10/100 Ethernet Single Chip LAN91C111Internal 32Bit Wide Data Path8Kbytes Internal Memory (Receive and Transmit FIFO Buffers)External 25MHz-output pin for an external PHY and MACMSC0,1 - Static Chip Select 1,2 (Bank 1,2)Base Address = 0x04000_0000 (Pri) 0x0800_0000(sec)

Embedded System Lab. II 26

Universal Serial Bus – USB(1)Motivation

Connection of the PC to the telephoneEase-of-usePort expansion

Goals for the Universal Serial BusEase-of-use for PC peripheral expansionLow-cost solution that supports transfer rates up to 480 Mb/sFull support for real-time data for voice, audio, and videoProtocol flexibility for mixed-mode isochronous data transfers and asynchronous messagingIntegration in commodity device technologyComprehension of various PC configurations and form factorsProvision of a standard interface capable of quick diffusion into productEnabling new classes of devices that augment the PC’s capabilityFull backward compatibility of USB 2.0 for devices built to previous versions of the specification

Embedded System Lab. II 27

Universal Serial Bus – USB (2)Feature

Easy to use for end userSingle model for cabling and connectorsElectrical details isolated from end user (e.g., bus terminations)Self-identifying peripherals, automatic mapping of function to driver and configurationDynamically attachable and reconfigurable peripherals

Wide range of workloads and applicationsSuitable for device bandwidths ranging from a few kb/s to several hundred Mb/sSupports isochronous as well as asynchronous transfer types over the same set of wiresSupports concurrent operation of many devices (multiple connections)Supports up to 127 physical devicesSupports transfer of multiple data and message streams between the host and devicesAllows compound devices (i.e., peripherals composed of many functions)Lower protocol overhead, resulting in high bus utilization

Embedded System Lab. II 28

Universal Serial Bus – USB (3)Isochronous bandwidth

Guaranteed bandwidth and low latencies appropriate for telephony, audio, video, etc.

FlexibilitySupports a wide range of packet sizes, which allows a range of device buffering optionsAllows a wide range of device data rates by accommodating packet buffer size and latenciesFlow control for buffer handling is built into the protocol

RobustnessError handling/fault recovery mechanism is built into the protocolDynamic insertion and removal of devices is identified in user-perceived real-timeSupports identification of faulty devices

Synergy with PC industryProtocol is simple to implement and integrateConsistent with the PC plug-and-play architectureLeverages existing operating system interfaces

Embedded System Lab. II 29

Universal Serial Bus – USB (4)Low-cost implementation

Low-cost subchannel at 1.5 Mb/sOptimized for integration in peripheral and host hardwareSuitable for development of low-cost peripheralsLow-cost cables and connectorsUses commodity technologies

Upgrade pathArchitecture upgradeable to support multiple USB Host Controllers in a system

Embedded System Lab. II 30

Universal Serial Bus – USB (5)

Embedded System Lab. II 31

Universal Serial Bus – USB (6)Taxonomy of Application Space

Embedded System Lab. II 32

Physical Interface

USB H/W Architectural(1)

Embedded System Lab. II 33

USB H/W Architectural(2)

Embedded System Lab. II 34

USB Host ControllerHost Controller의분류

OHCI(Open Host Controller Interface : Compaq )UHCI(Universal Host Controller Interface : Intel )

※같은 capability를제공

USB Core

Host Controller Driver

USB Client Driver

Host Controller(Compaq or Intel)

USB Device

Application

Linux USB Device Driver Stack

Embedded System Lab. II 35

USB Hub

기능

포트제어연결인식

포트 enable/disablereset/resume 신호

데이터신호신호재생

robustness/recover전력분배

Embedded System Lab. II 36

USB Data Flow

TypeControl Transfers: Used to configure a device at attach time and can be used for other device-specific purposes, including control of other pipes on the device.Bulk Data Transfers: Generated or consumed in relatively large and bursty quantities and have wide dynamic latitude in transmission constraints.Interrupt Data Transfers: Used for timely but reliable delivery of data, for example, characters or coordinates with human-perceptible echo or feedback response characteristics.Isochronous Data Transfers: Occupy a prenegotiated amount of USB bandwidth with a prenegotiated delivery latency. (Also called streaming real time transfers).

Embedded System Lab. II 37

USB모델한개의호스트(마스터모드), 다수의디바이스(client)USB 모델의계층

Embedded System Lab. II 38

호스트 계층

USB host controller매체에대한물리적인연결

low level 프로토콜처리(SIE)H/W + S/W

USB system S/W드라이버층과의인터페이스

standard device 처리Client S/W디바이스드라이버

주변장치의기능처리를위한 S/W

Embedded System Lab. II 39

디바이스 계층

USB bus interface매체에대한물리적인연결

low level 프로토콜처리(SIE)USB logical device호스트에대한소자의

common view pointhigh-level 프로토콜처리

Function장치에의해제공되는기능

Embedded System Lab. II 40

디바이스 추상화

엔드포인트디바이스끝의데이터소스또는싱크

고유주소, unidirection, transfer 특성을가짐파이프호스트 S/W owner와디바이스 endpoint의결합호스트메모리버퍼에서엔드포인트 FIFO의연결파이프통신모드: stream(데이터)과 message(USB 데이터구조)default control pipe : endpoint 0와의파이프

인터페이스파이프의집합

각기능에 map1개의 S/W client에의해소유됨

Embedded System Lab. II 41

USB의 상세 형태