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XILINX CONFIDENTIAL — DISCLOSED UNDER NDA

Zynq-7000 EPP TRM

Chapter 19: UART Controller

XTP152 (Draft) February 15, 2012

NOTICE: This pre-release document contains confidential and proprietary information of Xilinx, Inc. and is being disclosed toyou as a participant in an early access program, under obligation of confidentiality. You may print one (1) copy of thisdocument for evaluation purposes. You may not modify, distribute, or disclose this material to anyone, including youremployees, coworkers, or contractors (these individuals must apply for separate access to the program). This document

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Zynq-7000 EPP Technical Reference Manual www.xilinx.com 2

UG585 (DRAFT) February 15, 2012

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Third Party Intellectual Property Disclosure

This manual contains copyrighted material provided under license from the legal owner of the intellectual property (IP).

The following gives the required disclosure for each IP licensor to their IP used in the specified functional unit:

APU, SCU, Global Timer, GIC, WDT Cortex-A9 MPCore, Part DDI 0407F (ID043010)Copyright ©2008-2010 ARM.

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SDT Part Number: T-CS-PE-0004-100©2008 Cadence Design Systems, Inc. All rights reserved

TTC Triple Timer Counter (TTC)©2000 Cadence Design Systems, Inc. All rights reserved.

USB Chipidea/Synopsys CI13612a (CI133210A) HighSpeed USB OnTheGo ControllerCore,Copyright © 2009 Synopsys, Inc. Synopsys proprietary, used with permission.

GEM Gigabit Ethernet MAC (GEM), Part Number: T-CS-ET-0005-100©2000 Cadence Design Systems, Inc. All rights reserved

SDIO Arasan SD2.0/ SDIO2.0/ MMC3.31 AHB Host ControllerCopyright 2009 Arasan Systems, Inc.

I2C Part Number: T-CS-PE-0007-100©2000 Cadence Design Systems, Inc. All rights reserved.

SPI Part Number: T-CS-PE-0009-100©2000 Cadence Design Systems, Inc. All rights reserved.

UART Part Number: T-CS-PE-0001-100©2003 Cadence Design Systems, Inc. All rights reserved.

DMC IntelliTM DDR Arbiter Interface, Part Number: DS-114-pkg16©2010 Virage Logic Corporation. All rights reserved.

SMC ARM Part number PL353 - DDI 0380G,Copyright © 2005-2007 ARM Limited. All rights reserved.

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Chapter 19

UART Controller

19 UART

19.1 IntroductionThe UART module is a full-duplex asynchronous receiver and transmitter that supports a wide range of

software programmable baud rates and data formats. It can also accommodate for automatic parity

generation and several error detection schemes and provides both receive and transmit FIFO buffering for

the APU.

The UART peripheral is structured into separate receiver and transmitter data paths, which include 64-byte

FIFOs. The rate of operation of these data paths is controlled by the Baud Rate Generator module.

The mode of operation is configured using the Control Logic module, and the current status of the UART is

indicated via the Interrupt Control module. The current mode is also used to control the Mode Switch

module which selects the various loopback modes available.

Data to be transmitted is written from the APU into the Transmitter FIFO using byte operations through the

APB interface.

When the Transmitter FIFO contains enough data to transmit, the Transmitter module pulls the data from

the FIFO and serializes it onto the transmitter serial output.

Data received is deserialized by the Receiver module and written into the Receiver FIFO. The fill level of

the Receiver FIFO module is then used to trigger an interrupt to the APU. The APU pulls data from theReceiver FIFO by reading byte or double bytes using the APB interface.

If the UART is being used in a modem-like application, the Modem Control module detects and generates

the modem handshake signals appropriately and also controls the receiver and transmitter paths according

to the handshaking protocol.

19.1.1 Features

The PS supports two UART devices in the IOP with these key features:

• Programmable baud rate generator

• 64-byte receive and transmit FIFOs

• 6, 7, or 8 data bits

• 1, 1.5, or 2 stop bits

• Odd, even, space, mark, or no parity

• Parity, framing and overrun error detection

• Line-break generation and detection

• Automatic echo, local loopback, and remote loopback channel modes

• Interrupts generation

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• Modem control signals: CTS, RTS, DSR, DTR, RI and DCD

19.1.2 System Viewpoint

The system viewpoint diagram for the UART module is shown in Figure 1.

PLFabric

MIO – EMIO

Routing

PS Master

Interconnect APB

MIO

Pins

EMIO

Signals

UART{0, 1}_REF_CLK

IRQ ID# {59, 82}

Tx, Rx

UART{0, 1}_REF_RST

T x , R

x , C T S

N , D

C D N ,

D S R N , R

I N , D

T R N , R

T S N

Control

and Status

Registers

Slave

ports

CPU_1x clock

UART{0, 1}_CPU1X_RST

UART

Interface

Controller

Figure 1: UART System Viewpoint

There are two UARTs in the PS. Each UART can be configured independently. The TX and RX interface

can be mapped to either the EMIO interface or the GPIO interface. The Modem control signals are only

available through the EMIO interface. The clocks and resets to the UART are sourced from the global

clock and reset blocks for the PS. The APB interface is connected to an AMBA interconnect which allows

multiple masters to have access to the

Software-driven modem flow control signals can be implemented via the GPIO controller and route the IOsignals to either the MIO or EMIO.



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19.2 Funct ional Descript ion

19.2.1 Block Diagram

The block diagram for the UART module is shown in Figure 2.

Transmit

Interrupts

Transmitter

FIFOTransmitter

Receiver

FIFOReceiver

Modem

Control

Mode

Switch

Baud Rate

Generator

APB

Receive

Control

APB

Interface

Control

Logic

Interrupt

Control

Figure 2 UART Block Diagram

19.2.2 Microprocessor APB Interface

The UART APB module implements a standard AMBA 2.0 APB slave interface. This allows an external

APB master to read and write to the defined UART registers, which are distributed throughout the other

UART modules.

19.2.3 Control Logic

The Control Logic module contains the Control register and the Mode register, which are used to select

the various operating modes of the UART.

The Control register enables, disables, and issues soft resets to the Receiver and Transmitter modules. In

addition, it restarts the receiver timeout period, and controls the transmitter break logic.

The Mode register selects the clock used by the baud rate generator. It also selects the bit length, parity bit

and stop bit to be used by transmitted and received data. In addition, it selects the mode of operation of the

UART, switching between normal UART mode, automatic echo, local loopback, or remote loopback as

required.

19.2.4 Baud Rate Generator

The baud rate generator furnishes the bit period clock, or baud rate clock, for both the receiver and the

transmitter. The baud rate clock is implemented by distributing the base clock uar t _cl k and a singlecycle clock enable to achieve the effect of clocking at the appropriate frequency division.

The effective logic for the baud rate generation is shown in Figure 3.



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CLKS CD

Divide

by 8 Divide

by

(BDIV + 1)

Divide by CD CC > 1

CC = 0

CC = 1

sel_clk

uart_clk

uart_clk8

baud_sample

baud_tx_rate

baud_rx_rate

0

1

Figure 3: Baud Rate Generator

The baud rate generator uses the master clock signal, uart _ref _cl k.

The uart_ref_clk clock is divided down to provide three further clocks enable pulses, baud_sampl e,baud_t x_r at e and baud_r x_r ate. The baud_t x_r ate is the target baud rate used fortransmitting data. The baud_r x_r at e is nominally at the same rate, but gets resynchronised to the incoming received data. The baud_sampl e runs at a multiple of baud_r x_rate andbaud_t x_r at e and is used to oversample the received data.

First, uar t _r ef _cl k is divided by the CD field value in the Baud Rate Generator register to generatethe baud_sampl e clock enable. This register may be programmed with a value between 1 and 65535,and its reset value may be defined at compile time.

Secondly, the baud_sampl e clock is divided by BDI V plus 1. BDI V is a programmable field in theBaud Rate Divider register and may be programmed with a value between 0 and 255. It has a reset value

of 15, inferring a default ratio of 16 baud_sampl e clocks per baud_t x_cl ock / baud_r x_r ate.

Thus the frequency of the baud_sample clock enable is shown in Equation (1).

Equation (1)

The frequency of the baud_r x_r ate and baud_t x_r at e clock enables is show in Equation (2) .

Equation (2)

It is essential to disable the transmitter and receiver before writing to the baud rate generator register,

ua_br gr , or the baud rate divider register, ua_di v. Issue a soft reset to both the transmitter andreceiver before they are re-enabled.

Some examples of the relationship between the uart_ref_clk clock, baud rate, clock divisor, and the rate of

error are shown in Table 1. The highlighted entry shows the default reset values for CD and BDI V. For



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D1 D2 D3 D4 D5 D6 D7 D8 PA S

this example a system clock rate of Uart _r ef _cl k = 13 MHz and Uart _r ef _cl k/ 8 = 1.625MHz is assumed. See Chapter 25, Clocks for details on system clock generation.

Table 1: Typical UART Parameter Values

Clock Baud Rate

Calc’d CD

Actual CD

BDIV ActualBaud Rate

Error(BPS)

% Error

Uart_ref_clk 600 1354.167 1354 15 600.074 0.074 0.012

Uart_ref_clk/8 9600 13.021 13 12 9615.385 15.385 0.160

Uart_ref_clk 9600 84.635 85 15 9558.823 -41.176 -0.429

Uart_ref_clk 28800 41.035 41 10 28824.834 -24.834 -0.086

Uart_ref_clk/8 230400 1.008 1 6 232142.875 -1742.857 -0.756

Notes:

1. Highlighted row shows CD and BDIV reset values.

2. System clock assumed with Uart _r ef _cl k = 13 MHz and Uart _r ef _cl k/ 8 = 1.625 MHz.

19.2.5 Transmitter FIFO

The transmitter FIFO stores data written from the APB Interface until it is popped out by the Transmitter

module and loaded into its shift register. The FIFO size is 8 bits maximum data width.

Data is loaded into the transmitter FIFO by writing to the Transmit FIFO register.

When data is loaded into the FIFO, the transmit FIFO empty flag is cleared and remains in this low state

until the last word in the FIFO has been popped out and loaded into the transmitter shift register. This

means that the host SW has another full serial word time until the next data is needed, allowing it to react to

the empty flag being set and write another word in the FIFO without loss in transmission time.

The transmit FIFO full flag indicates that the FIFO is completely full and prevents any further data from

being loaded into the FIFO. If another APB write to the FIFO is performed an overflow will be triggered

and the write data will not be loaded into the FIFO.The transmit FIFO nearly-full flag indicates that there is only byte free in the FIFO and writing one more

byte.

A threshold trigger can be setup on the transmitter FIFO fill level. The Transmitter Trigger register may be

used to setup this value, such that the trigger is set when the FIFO fill level reaches this programmed value.

19.2.6 Transmitter

The Transmitter module pops parallel data from the Transmitter FIFO and loads it into the transmitter

shift register so that it can be serialised.

The transmitter shifts out the start bit, data bits, parity bit, and stop bits as a serial data stream. Data is

transmitted, least significant bit first, on the falling edge of the transmit baud clock enable,baud_t x_r ate. A typical transmitted data stream is illustrated in Figure 4.

baud_tx_rate

TXD

Figure 4: Transmitted Data Stream



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The CHRL in the Mode register selects the character length, in terms of the number of data bits. TheNBSTOP field in the Mode register selects the number of stop bits to transmit.

19.2.7 Receiver FIFO

The receiver FIFO stores the data that is received by the receiver serial shift register. The FIFO size has amaximum data width of 8 bits.

When data is loaded into the FIFO, the receive FIFO empty flag is cleared and this state remains low until

all data in the FIFO has been popped out through the APB interface. Reading from an empty receiver

FIFO returns zero.

The receive FIFO full flag, r f i f o_f ul l , indicates that the FIFO is full and prevents any further datafrom being loaded into the FIFO, although this will result in an overflow. When a space becomes available

in the receiver FIFO, any character stored in the receiver will be loaded.

A threshold trigger can be setup on the receiver FIFO fill level. The Receiver Trigger register may be used

to setup this value, such that the trigger is set when the FIFO fill level reaches this programmed value.

19.2.8 Receiver

The UART continuously over-samples the ua_r xd signal using uar t _cl k and the clock enable,baud_sampl e. When the samples detect a transition to a low level, it may indicate the beginning of astart bit. When the UART senses a low level at the ua_r xd input, it waits for a count of half of BDI V baud rate clock cycles and then samples three more times. If all three bits still indicate a low level, the

receiver considers this to be a valid start bit, as illustrated in Figure 5 for the default BDI V of 15.

Figure 5: Default BDIV Receiver Data Stream

When a valid start bit is identified, the receiver baud rate clock enable, baud_r x_r at e, isresynchronised so that further sampling of the incoming ua_r xd happens around the theoretical mid- point of each bit, as illustrated in Figure 6.

Figure 6: Resynchronized Receiver Data Stream

When the resynchronised baud_r x_r ate is high, the last three sampled bits are compared. The logicvalue is determined by majority voting, two samples having the same value define the value of the data



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bit. When the value of a serial data bit has been determined, it is shifted to the receive shift register. When a

complete character has been assembled, the contents of the register are then pushed to the receive FIFO.

Receiver Parity Error

Each time a character is received, the receiver calculates the parity of the received data bits in accordance

with the field PAR in the Control register. It then compares the result with the received parity bit. If adifference is detected, the parity error bit PARE in the Channel Interrupt Status register, ua_ci sr , is setand an interrupt event generated if enabled.

Receiver Framing Error

When the receiver fails to receive a valid stop bit at the end of a frame, the frame error bit FRAME in theChannel Interrupt Status register, ua_ci sr , is set and an interrupt event generated if enabled.

Receiver Overflow Error

When a character has been fully loaded into the receiver shift register it must be pushed into the receiverFIFO. The push will fail if the FIFO is already full, or the push may experience a delay as this involves a

transition across a clock boundary from uar t _cl k to pcl k. When a further start bit is detected beforethe previous character has been transferred to the receiver FIFO, the ROVR error bit in the Channel Interrupt Status register, ua_ci sr , is set and an interrupt event is generated if enabled.

Receiver Timeout Error

The receiver timeout function enables the receiver to detect an idle condition on the ua_r xd line. Themaximum delay for which the UART should wait for a new character to arrive while the ua_r xd line isinactive (a high level is present on the ua_r xd line) is programmed in the Receiver Timeout register

(ua_rto). A non-zero value in this register represents the maximum time before a timeout is issued, in terms of multiples of four bit periods. When this register is set to 0, the timeout detection is disabled.

Note that when a new timeout value is written into ua_r t o, it is not actually loaded into the timeoutcounter until either a new start bit is received or when the reset timeout bit, RSTTO, is written high in theControl register. If no start bit or reset timeout occurs for 1023 bit periods, a timeout will occur. When a

start bit or reset timeout is seen, the most significant 8 bits of the 10 bit timeout down counter are initialized

with the value of ua_rto. The counter decrements at each bit period and is reloaded at the start of eachcharacter frame or if the reset timeout bit is written. If the counter reaches 0, a timeout interrupt event is

generated and the appropriate bit in the Channel Interrupt Status register is set if unmasked.

Timeout duration is calculated by multiplying the timeout value (RTO) by four times the bit period.

19.2.9 Mode Switch The mode switch module provides an interface between the external transmit and receive signals, and the

rest of the UART. This block is used to implement the mode selected by the Mode register: normal mode,

automatic echo, local loopback or remote loopback. For details, refer to Modes of Operation.



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19.2.10 Modem Control

The Modem Control module facilitates the control of communication between a modem and the UART. It

contains the Modem Status register and the Modem Control register.

The read-only Modem Status register (ua_msr ) is used to read the values of the clear to send(ua_nct s), data carrier detect (ua_ndcd), data set ready (ua_ndsr ) and ring indicator (ua_nr i )modem inputs. It also reports changes in any of these inputs and indicates whether automatic flow control

mode is currently enabled.

The bits in the ua_msr are cleared by writing a high to the particular bit.

The read/write only Modem Control register (ua_mcr ) is used to set the data terminal ready (ua_ndt r )and request to send (ua_nrts) outputs, and to enable the automatic flow control mode register.

By default the automatic flow control mode is disabled, meaning that the modem inputs and outputs work

completely under software control. When the automatic flow control mode is enabled by setting the FCM bit in the Modem Control register, the UART transmission and reception status is automatically controlled

using the modem handshake inputs and outputs.

In automatic flow control mode the request to send output, ua_nr t s, is asserted and de-asserted basedon the current fill level of the receiver FIFO, which will result in the far-end transmitter pausing

transmission and preventing an overflow of the UART receiver FIFO. The FDEL field in the Flow Delayregister is used to setup a trigger level on the Receiver FIFO which will cause the de-assertion of

ua_nr t s. It remains low until the FIFO level has dropped to below four less than FDEL .

Additionally in automatic flow control mode, the UART will only transmit whilst the ua_nct s input isasserted. When the ua_nct s is de-asserted the UART will pause transmission at the next character

boundary.

19.2.11 Interrupt Control

The Interrupt Control module detects events from the other UART modules and conditions them for

reporting through the Channel Interrupt Status register, ua_ci sr , and the Channel Status register,

ua_csr . The ua_ci sr register presents the latched version of the interrupt events. The ua_csrregister provides raw unmasked read-only status.

Interrupts are enabled and disabled individually using the Interrupt Enable register, ua_i er , and theInterrupt Disable register, ua_i dr . The resulting status of whether the interrupt is enabled or disabled isindicated in the Interrupt Mask register, ua_i mr . This arrangement of the three registers allows eachindividual interrupt to be enabled or disabled without affecting the current mask of the other interrupts.

The current value of ua_i mr is applied to the latched versions of the interrupt events, and onlyinterrupts which are unmasked (enabled) can generate an interrupt event to the system CPU by asserting

the ua_i nt output. This output remains asserted until the latched version is cleared, thus making theinterrupt output level sensitive.

The ua_csr contains read-only unmasked versions of some of the ua_ci sr bits, which are cleared

under control of the ua_ci sr .

The configuration may be changed at compile time such that the ua_ci sr register is unmasked and its bits are set on an interrupt event regardless of the current state of the mask. In this configuration the

duplicate unmasked ua_csr bits are removed from the design. Note that the mask is still applied to thegeneration of the ua_i nt output, such that only enabled interrupts will cause a CPU interrupt.

The bits in the ua_ci sr are cleared by writing a high to the particular bit.



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The ua_csr register is a read-only register and its bits are cleared only when the asserting conditionfinishes. Similarly, if the duplicate bits are included in ua_csr register from the ua_ci sr register,these are only cleared when the ua_ci sr is cleared.

19.3 Modes

of O

pe

rat i

on The UART can operate in a number of modes, set using the Mode register, ua_mr .

19.3.1 Clock Modes

The UART baud rate is derived from the uar t _ref _cl k provided by the clock controller .

See Chapter 25, Clocks for details on system clock generation.

19.3.2 Bit Frame Modes

The Mode register can be programmed to control the UART serial bit frame format, including using frame

formats of 6, 7 or 8 databits, generating or checking even, odd, space, mark, or no parity. For each bit

frame format, 1, 1.5 or 2 stop bits can be used, as shown in Figure 7.

Figure 7: Bit Frame Modes

19.3.3 Operational Modes

The CHMODE field in the Mode register can be programmed to use one of the four operating modes of theUART; Normal, Automatic Echo, Local Loopback and Remote Loopback. Each of the operating modes

is described in the following sections.



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Normal Mode

In this mode the UART operates as a standard UART.

UART UART

Mode Switch

Transmitter

Receiver

uart_tx

uart_rx

Device Core Pins

Figure 8: Normal Operating Mode

Automatic Echo

In this mode the receiver data input is immediately transmitted through the transmitter output pin. No

internal data can be transmitted from the UART but received data can be read by the processor.

Figure 9: Automatic Echo Operating Mode

Local Loopback

In this mode the signal transmitted from the UART is connected to the receiver input. No data can be

transmitted and no external data can be received.



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Figure 10: Local Loopback Operating Mode

Remote Loopback

In this mode the receiver input data is immediately transmitted through the transmitter output pin,ua_t xd. No internal data can be transmitted from the UART and the UART cannot access received data.

Figure 11: Remote Loopback Operating Mode



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19.4 Register OverviewAn overview of the UART Registers is shown in Table 2.

Table 2:UART Register Overview

Function Register Names Overview

Configuration Control_reg

Mode_reg

Baud_rate_reg_reg

Baud_rate_divider_reg

Channel_sts_reg

Configure mode and baud rate.

Read status.

Interrupt processing Intrpt_en_reg

Intrpt_dis_reg

Intrpt_mask_reg

Chnl_int_sts_reg

Enable/disable the interrupt detection,

mask interrupt sent to the interrupt

controller, read raw interrupt status.

Receiver Rcvr_timeout_reg

Rcvr_FIFO_trigger_reg

Configure receiver timeout and FIFO

trigger level value

Transmitter Tx_FIFO_trigger_reg Configure transmitter FIFO trigger level

value

Modem Modem_ctrl_reg

Modem_sts_reg

Configure modem-like application

Data TX_RX_FIFO Read data Received. Write data to be

Transmitted.



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19.5 Signal Int erf ace

19.5.1 UART Rx Tx Interface Signals

Table 3 shows the interface signals for UART0. For UART1, simply substitute the uart0 portion of each

signal name with uart1.

Table 3: UART0 interface for RS232 Protocol

Signal Name I/O UART Pin Description

uart0_rx I 0 UART receiver serial input pin

uart0_tx O 1 UART transmitter serial output pin

19.5.2 UART EMIO SignalsTable 4 shows the pins for UART0. For UART1, simply substitute the UART0 portion of each pin name

with UART1.

Table 4: UART Pin List Details

Pin Name Dir Name Description

EMIOUART0TX O EMIO_UART0_TX UART transmitter serial output pin

EMIOUART0RX I EMIO_UART0_RX UART receiver serial input pin

EMIOUART0CTSN I EMIO_UART0_CTSN Clear-to-send flow control

EMIOUART0RTSN O EMIO_UART0_RTSN Request-to-send flow control

EMIOUART0DSRN I EMIO_UART0_DSRN Modem data set ready

EMIOUART0DCDN I EMIO_UART0_DCDN Modem data carrier detect

EMIOUART0RIN I EMIO_UART0_RIN Modem ring indicator

EMIOUART0DTRN O EMIO_UART0_DTRN Modem data terminal ready

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