automatic synthesis and code-generation of real-time embedded software ...
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Automatic Synthesis and Code-Generation of Real-Time Embedded Software 即時嵌入式軟體之自動合成及程式碼之產生. 熊博安 國立中正大學資訊工程學系 民國九十一年四月二十六日. What will I talk about ?. What is a real-time system? What is an embedded system? Why software? Why synthesis? What is software synthesis & code generation? - PowerPoint PPT PresentationTRANSCRIPT
Automatic Synthesis and Code-Generation of Real-Time Embedded Software 即時嵌入式軟體之自動合成及程式碼之產生
熊博安國立中正大學資訊工程學系
民國九十一年四月二十六日
2002/04/26 2
What will I talk about ?
What is a real-time system? What is an embedded system? Why software? Why synthesis? What is software synthesis & code
generation? Real-world applications? Future work?
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What is a REAL-TIME SYSTEM?
Timely Response Predictable Response System Correctness:
Timing (period, deadlines, etc.) Function
Constraints: Hard (meet ALL deadlines) Soft (miss SOME deadlines)
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Examples of Real-Time Systems
multimedia servers automobiles
air craftstelecommunications
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What is an EMBEDDED SYSTEM? Installed in a larger system Dedicated task Small Memory Space (200~400 KB) Low Processing Power (100~200 MHz) Unstable Environment (mobile, …) Reactive Real-Time
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Embedded Systems Example
medical instrumentshome appliances office equipments
space crafts research lab equipments
factory automation
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Embedded System Architecture
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Why SOFTWARE?
more than 70% software in many real-time embedded systems!!!
software is more flexible and easily reconfigurable, hence more errors!!!
real-time need for temporally correct
software
embedded need for small, efficient software
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Why SYNTHESIS?
More software high complexity need for automatic design (synthesis)
Eliminate human and logical errors
Relatively immature synthesis techniques for software
Code optimizations size
efficiency
Automatic code generation
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What is software synthesis & code generation?
Model for real-time embedded systems?Set of concurrent tasks with memory and timing constraints!
How to feasibly execute in an embedded system? (e.g. a 100MHz CPU, 256 KB RAM)Task scheduling!
How to generate code?Map schedules to software code!
Code optimizations?Minimize size, maximize efficiency!
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Synthesis Issues and Solutions2. Real-Time
Constraints1. Bounded
Memory Execution
Extended Quasi-Static Scheduling
(EQSS)
Proposed Solutions
:
Real-Time Scheduling
(RTS)
Hard Real-Time
Firing Interval Bound Synthesis
(FIBS)
Soft Real-Time
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Real-Time Embedded System Model
Time Complex-Choice Petri Nets
(TCCPN)
t1
t4(3, 10)
t2(1, 4)
2
p1
p2
p4 p3 t3
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Synthesis Algorithm (Hard RTES)
Synthesize_Hard_RTES(S, ,
EQSS = Ext_Quasi_Static_Schedule(S, if (EQSS == NULL) return MemOverFlow; RTS = Real_Time_Sched(S, QSS, if (RTS == NULL) return RTS_Error;
else Code = Code_Gen(S, QSS, RTS); return Code;
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Synthesis Algorithm (Soft RTES)
Synthesize_Soft_RTES(S, ,
EQSS = Ext_Quasi_Static_Schedule(S, if (EQSS == NULL) return MemOverFlow; FIB = Firing_Interv_Synth(S, QSS, ); if (FIB == NULL) return FIB_Error;
else Code = Code_Gen(S, QSS, FIB); return Code;
2002/04/26 18
Quasi-Static Scheduling
TFCPN
net
decomposition
Conflict-Free Components
Quasi-Static Schedules
t1
t3(5, 10)
t2(1, 4)
2
p1
p2
p3
t1
t2(1, 4)
2
p1
p2
t1
t3(5, 10)
p1
p3
• Finite Complete Cycle
• Deadlock Free
• Satisfy Memory ReqtsMemoryOK!!!
2002/04/26 19Exclusion Set
Extended Quasi-Static Scheduling
Transition Exclusive Transitions
t4 t5
t5 t4, t6
t6 t5, t7
t7 t6
t1
t2
t3
t4
t5
t6
t7
p1
p2
p3
Exclusion TableTCCPN
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Decomposition of Exclusion Set
t4
t5
t6
t7
t4
t5
t6
t7
t4
t5
t6
t7
t4
t5
t6
t7
t4
t5
t6
t7
t1
t2
t3
t4
t5
t6
t7
p1
p2
p3
Transition Exclusive Trans
t4 t5
t5 t4, t6
t6 t5, t7
t7 t6
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Reduction of Decomposed Exclusion Set
t4
t5
t6
t7
t4
t5
t6
t7
t4
t5
t6
t7
t4
t5
t6
t7
t4
t5
t6
t7
t4
t5
t6
t7
t4
t5
t6
t7
Reduce
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EQSS Schedules
t1t4p1
t2
t3
t6
p2
p3
t1
t2
t5
p1
p2
t3 t7
p3
f(s) = (t1 t2 t3 t4 t6) f(s) = (t1 t2 t3 t5 t5 t7)
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Real-Time Scheduling
Single Processor
Worst Case Timing Analysis:
Rate Monotonic (RM) fixed priority
small period high priority
Earliest Deadline First (EDF) dynamic priority
early deadline high priority
ijkiA
iQSSt
kCF
A tLFTWCT Max
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Firing Interval Bound Synthesis
2 issues in the synthesis of SOFT real-time embedded systems: Synchronization Wait:
(for completion of other tasks) Real-Time Specification:
(complete before deadlines)
Proposed Solutions: Postpone Release Time:
+ w, w> 0 Advance Finish Time:
n, n>0
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Code Generation
generate_code(S, QSS1, QSS2, …, QSSn, RTS) {
for i = 1, …, n { Di = create_process(QSSi);
for j = 1, …, Indep_Tasks(Ai) {
dij = create_task(QSSi);
generate_task_code(dij);
add_task(dij, Di); }
} create_main(); output “for(i=0, i<length(RTS); i++) {”; for k = 1, …, RTS output_code(Dik);
output “}”; }
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Optimal Code Hierarchy
Main Program
Processi
Task 1 Task 2 Task k…
TCCPN
# Tasks = # Independent Source Transitions
2002/04/26 27
Illustration Example
S = {F1, F2}
t11(2, 3)
t12(1, 3)
t13(3, 5)
p1
p2
p3
2
t14(5, 10)
t15(4, 9)
2
F1:
t21(0, 1)
t22(1, 2)
t23(1, 2)
p7
p2
p3
2
t24(2, 4)
t25(2, 4)
2
2
p4
p5
p6
t27(4, 8)
t26(5, 10)
2
t28(0, 5) t29(1, 2) F2:
p1
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Conflict Free Components for F1
t11(2, 3)
t12(1, 3)
p1
p2 2
t14(5, 10)
t11(2, 3)
t13(3, 5)
p1
p3 t15(4, 9)
2 R12:
R11:
v12 = (t11, t13, t15, t15)
13 (v12) 26
Quasi-Static Scheduling
v11 = (t11, t12, t11, t12, t14)
11 (v11) 22
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Conflict Free Components for F2
t21(0, 1)
t22(1, 2)
p7
p2 2
t24(2, 4)
2 p4
t26(5, 10)
t28(0, 5) t29(1, 2)
t21(0, 1)
t23(1, 2)
p7
p3 t25(2, 4)
2
p4
p5
p6
t27(4, 8)
t26(5, 10)
2
t28(0, 5) t29(1, 2)
R21:
R22:
p1
p1
v21 = (t21, t22, 2t24, 4t26, t28, t29, t26)
31 (v21) 68v22 = (t21, t23, t25,
2t27, t28, t29, t26)
15 (v22) 36
Quasi-Static Scheduling
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Real-Time Scheduling
Task Priority i max(1) max(2)
T1 1 100 26 48
T2 2 110 68 68
Schedulable Yes No
Algorithms RM, EDF
1 = {v11, v12} 2 = {v12, t11 t12 k v12 t11 t12 t14, k 1}
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ATM Virtual Private Network Server Example
CLASSIFIERCLASSIFIERCONGESTION CONGESTION
CONTROL CONTROL (MSD)(MSD)
SUPERVISORSUPERVISOR
WFQ WFQ SCHEDULERSCHEDULER
ATM INATM IN
(155 Mbit/s)(155 Mbit/s)
ATM OUTATM OUT
(155 Mbit/s)(155 Mbit/s)DISCARDED DISCARDED
CELLSCELLS
2002/04/26 32
ATM Server Example CID READ_STATE_VCC UPDATE_STATE_INIT
p1
p2
p3
p4
p5
p6
p7
p8
p10
MSD
PTI
TI
t1
READ_OUT_QUID
t2
t6
t9
p9
p11
p12
p15
p16
p19
p13
p14
p17
p18
p20
p22
p23
t3
t4
t5
READ_MAX_QLENGTH
CHECK_QLENGTH
t8
READ_THRESHOLD
CHECK_QLENGTH
t7
t11
UPDATE_STATE_REJ
t10
t12
PUSH
Qlength < thres ?
UPDATE_STATE_ACC
N
Y
Qlength <max ?
Y
N
p21
Qlength = 0 ?
*SCHEDULE_WFQ
COMPUTE_OUT_TIME
Y
N
p24 st=2
st=0
st=1
PTI = 1/3 ?
Y
N
[1, 16]
[10, 25]
[9, 9]
[6, 15]
[12, 37]
2002/04/26 33
14 Schedules of MSD in ATM
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0
MSD
1
CID
2
PTI
3
t1
4
READ_STATE_VCC
7
READ_OUT_QUID
10
t2
11
t3 t4 t5
12
t6 UPDATE_STATE_INIT
13 18
12
READ_MAX_QLENGTH
15
CHECK_QLENGTH1
18
t7
19
t6 UPDATE_STATE_INIT
12
READ_THRESHOLD
15
CHECK_QLENGTH2
18
t8
19
t10 t9
PUSH
COMPUTE_OUT_TIME t12
*SCHEDULE_WFQ
t10 t9
PUSH
COMPUTE_OUT_TIME t12
*SCHEDULE_WFQ
PUSH
t11 UPDATE_STATE_REJ
PUSH
*SCHEDULE_WFQ COMPUTE_OUT_TIME
t12
*SCHEDULE_WFQ
COMPUTE_OUT_TIME t12
*SCHEDULE_WFQ
UPDATE_STATE_ACC
UPDATE_STATE_ACC
t11 UPDATE_STATE_REJ
t6 UPDATE_STATE_INIT 20
21 21
30
431
52
20
21 26
30
36
46 37
58
25
26 31
35
41
51 42
63
25
26 26
35
4 36
57
Schedule Results:
49 markings
14 schedules
63 instructions
12 Kbytes Memory
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Master/Slave Role Switch in the Bluetooth Wireless Comm Protocol In Bluetooth protocol:
Piconet = 1 master + 7 active slaves Frequently, master and slave switch roles
new active slave joining piconet overtaking of master duties creation of a new piconet with old master as sl
ave Model
2 TCCPN for Host A and Host B 2 TCCPN for Host Control / Link Manager
2002/04/26 36
TCCPNs for Host A and Host BHost_A
ACL_Connection
Initialize
Send HA2LA_HCI_Switch_Role
Receive LA2HA_HCI_Command_status_event
Receive LA2HA_HCI_Role_change_event
End
Host_B
ACL_Connection
Initialize
Send HB2LB_HCI_Switch_Role
Receive LB2HB_HCI_Command_status_event
Receive LB2HB_HCI_Role_change_event
End
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TCCPN for Host Control / Link Manager of Device A
HC/LM_A
Initialize
ACL_Connection
End
ReceiveHA2LA_HCI_Switch_Role
Receive N2LA_LMP_Switch_reg
SendLA2HA_HCI_Command
_States_event
SendLA2N_LMP_slot_
offset_sub2
SendLA2N_LMP_Switch
_req
Receive N2LA_LMP_Slot_offset_sub1
Checking NetWork
SendLA2N_LMP_accepted
SendLA2N_LMP_not_accepted
ReceiveN2LA_LMP_
accepted ReceiveN2LA_LMP_not
_accepted
SendTDD_Swit
chA
ReceiveBA2LA_TimeOu
t1Receive
BA2LA_Role_SwitchA_Success
End
SendLA2HA_HCI_
Role_Change_event
End
2002/04/26 38
TCCPN for Host Control / Link Manager of Device B
HC/LM_B
Initialize
ACL_Connection
End
ReceiveHB2LB_HCI_Switch
_RoleReceive N2LB_LMP_Switch_reg
Send LB2HB_HCI_Command_States_
event
SendLB2N_LMP_slot_
offset_sub2
SendLB2N_LMP_Switch
_req
ReceiveN2LB_LMP_Slot_offse
t_sub1
Checking NetWork
SendLB2N_LMP_accepted
SendLB2N_LMP_not_accepted
ReceiveN2LB_LMP_acc
eptedReceive
N2LB_LMP_not_accepted
SendTDD_Swit
chB
ReceiveBB2LB_TimeOu
t1ReceiveBB2LB_Role_SwitchB_Success
End
SendLB2HB_HCI_
Role_Change_event
End
2002/04/26 39
Synthesis Results for M/S switch
CCPN #T #P #S Schedules
Host A 7 5 2 <0,1,2,4,5,6>,<0,1,3,5,6>
HC/LM A 21 15 6 <0,1,2,4,6,7,10,11,12,14>,<0,1,3,5,6,8,10,14>,<0,1,2,4,6,7,10,11,13,15,16,18>,<0,1,2,4,7,11,13,15,16,18>,<0,1,2,4,6,7,10,11,13,15,17,19,20>,<0,1,3,5,6,9,15,17,19,20>
Host B 7 5 2 Same as for Host A
HC/LM B 21 15 6 Same as for HC/LM A
2002/04/26 40
Mnemonics for Host A Transitions
t_0: Initialize, t_1: ACL_Connection, t_2: Send HA2LA_HCI_Switch_Role, t_3: t4, t_4: Receive LA2HA_HCI_Command_status_
event, t_5: Receive LA2HA_HCI_Role_change_even
t, t_6: End.
2002/04/26 41
Mnemonics for HC/LM A Transitions
t_0: Initialize, t_1: ACL_Connection, t_2: Receive HA2LA_HCI_Switch_Role, t_3: Receive N2LA_LMP_Switch_reg, t_4: Send LA2HA_HCI_Command_States_event, t_5: Receive N2LA_LMP_Slot_offset_sub1, t_6: Checking NetWork, t_7: Send LA2N_LMP_slot_offset_sub2, t_8: Send LA2N_LMP_not_accepted, t_9: Send LA2N_LMP_accepted, t_10: End Checking Network, t_11: Send LA2N_LMP_Switch_req, t_12: Receive N2LA_LMP_not_accepted, t_13: Receive N2LA_LMP_accepted, t_14: End, t_15: Send TDD_SwitchA, t_16: Receive BA2LA_TimeOut1, t_17: Receive BA2LA_Role_SwitchA_Success, t_18: End, t_19: Send LA2HA_HCI_Role_Change_event, t_20: End
2002/04/26 42
Conclusions
Software needs to be synthesized automatically because it is getting more and more complex!
Hard RTES Synthesis Method = EQSS + RTS + Code-Generation
Soft RTES Synthesis Method = EQSS + FIBS + Code-Generation
ATM VPN Server example showsfeasibility of our approach
2002/04/26 43
Current and Future Work
Integrate Real-Time Scheduling & EQSS
A general Petri Net system model
Java Implementation: install into embedded systems such as PDA for dynamic code change and management by user (web computing)
C Code Generation: for embedding into prototyping systems such as SoC design and verification platform
2002/04/26 44
References (EQSS, FIBS, etc.)
All papers are downloadable at http://www.cs.ccu.edu.tw/~pahsiung/publications/publications.html
F.-S. Su and P.-A. Hsiung, “Extended Quasi-Static Scheduling for Formal Synthesis and Code Generation of Embedded Software,” Proc. of the 10th IEEE/ACM International Symposium on Hardware/Software Codesign, (CODES'02), Colorado, USA, May 6-8, 2002 (accepted for presentation).
P.-A. Hsiung, “Formal Synthesis and Control of Soft Embedded Real-Time Systems,” Proc. 21st IFIP WG 6.1 International Conference on Formal Techniques for Networked and Distributed Systems (FORTE'01), (Cheju Island, Korea), pp. 35-50, Kluwer Academic Publishers, August 2001.
P.-A. Hsiung, "Formal Synthesis and Code Generation of Embedded Real-Time Software," Proc. ACM/IEEE 9th International Symposium on Hardware/Software Codesign (CODES'01), (Copenhagen, Denmark), pp. 208-213, ACM Press, New York, USA, April 2001.
2002/04/26 45
References (Time-Mem Sched.)
P.-A. Hsiung and C.-H. Gau, “Formal Synthesis of Real-Time Embedded Software by Time-Memory Scheduling of Colored Time Petri Nets,” Proc. of the Workshop on Theory and Practice of Timed Systems (TPTS'2002, Grenoble, France), April 6-7, 2002.
C.-H. Gau and P.-A. Hsiung, “Time-Memory Scheduling and Code Generation of Real-Time Embedded Software,” Proc. of the 8th International Conference on Real-Time Computing Systems and Applications (RTCSA'02, Tokyo, Japan), pp. 19-27, March 18-20, 2002.
2002/04/26 46
References (VERTAF)
P.-A. Hsiung, T.-Y. Lee, W.-B. See, J.-M. Fu, and S.-J. Chen, "VERTAF: An Object-Oriented Application Framework for Embedded Real-Time Systems," Proc. of the 5th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC'2002, Washington, D.C., USA), April 29-May 1, 2002 (accepted for presentation).
P.-A. Hsiung, W.-B. See, T.-Y. Lee, J.-M. Fu, and S.-J. Chen, "Formal Verification of Embedded Real-Time Software in Component-Based Application Frameworks," Proc. 8th Asia-Pacific Software Engineering Conference (APSEC'01) , (Macau SAR, China), pp. 71-78, IEEE CS Press, December 2001.
P.-A. Hsiung, F.-S. Su, C.-H. Gau, S.-Y. Jeng, and Y.-M. Chang, "Verifiable Embedded Real-Time Application Framework," Proc. IEEE International Real-Time Technology and Applications Symposium (RTAS'01), Work-In-Progress Session, (Taipei, Taiwan), pp. 109-110, IEEE Computer Society Press, May 2001.