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7/21/2019 Automotive Basics

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Automotive Interview QuestionsCAN INTERVIEW QUESTIONS:

1. What is CAN and its uses?

Answer: ! CA" is a mu#ti$master broa%cast seria# bus stan%ar% &or connectin' e#ectronic

contro# unit ()CUs*!

2! Contro##er+area network (CA" or CA"$bus* is a ve,ic#e bus stan%ar% %esi'ne% to a##ow

microcontro##ers a %evices to communicate wit, eac, ot,er wit,in a ve,ic#e wit,out a ,ost

computer!

-! CA" is a messa'e$base% protoco#. %esi'ne% speci/ca##0 &or automotive app#ications but

now a#so use% in ot,er areas suc, as in%ustria# automation an% me%ica# e1uipment!

! T,e Contro##er Area "etwork (CA"* bus is a seria# as0nc,ronous bus use% in

instrumentation app#ications &or in%ustries suc, as automobi#es!

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USES:

+ 3ore re#iab#0. e!'!. &ewer p#u'$in connectors t,at mi',t cause

errors!

+ Wirin' #ess comp#icate%. more economic!

+ )as0 to imp#ement. c,an'es. too!

+ A%%itiona# e#ements (e!'!. contro# units* are eas0 to inte'rate!+ Insta##ation p#ace e4c,an'eab#e wit,out e#ectric prob#ems!

+ Wire ma0 be %ia'nose%!

. CAN !rame w"r#s?

Answer: SO5 + ominant

Arbitration 5ie#% + bit I%enti/er. bit RTR (or* bit. SRR. I). 7 bit. RTR

Contro# 5ie#% + I). r8. bits (9C*

ata 5ie#% + (8$7* B0tes

CRC 5ie#% + : bits. e#imiter ( bit recessive*

AC; 5ie#% + bit. e#imiter ( bit recessive*

)O5 + < bits recessive

I5S + - bits recessive

T0pes o& &rames + ata. remote. )rror &rame an% Over#oa% &rame

T0pes o& errors + AC; error. Bit error. Stu= error. 5orm error. CRC error

)rror &rame + 8$2 superposition >a's. 7 recessive (e#imiter*

Over#oa% &rame + 8$2 superposition >a's. 7 recessive (e#imiter*

$. Wh% CAN is ha&in' 1( "hms at ea)h end?

Answer: To minimi?e t,e re>ection re&erence. to re%uce noise . To ensure t,at re>ection

%oes not cause communication &ai#ure. t,e transmission #ine must be terminate%!

*. Wh% CAN is messa'e "riented +r"t")",?



Answer: CA" protoco# is a messa'e$base% protoco#. not an a%%ress base% protoco#! T,is

means t,at messa'es are not transmitte% &rom one no%e to anot,er no%e base% on

a%%resses! )mbe%%e% in t,e CA" messa'e itse#& is t,e priorit0 an% t,e contents o& t,e %ata

bein' transmitte%! A## no%es in t,e s0stem receive ever0 messa'e transmitte% on t,e bus

(an% wi## acknow#e%'e i& t,e messa'e was proper#0 receive%*! It is up to eac, no%e in t,e

s0stem to %eci%e w,et,er t,e messa'e receive% s,ou#% be imme%iate#0 %iscar%e% or kept tobe processe%! A sin'#e messa'e can be %estine% &or one particu#ar no%e to receive. or man0

no%es base% on t,e wa0 t,e network an% s0stem are %esi'ne%! 5or e4amp#e. an automotive

airba' sensor can be connecte% via CA" to a sa&et0 s0stem router no%e on#0! T,is router

no%e takes in ot,er sa&et0 s0stem in&ormation an% routes it to a## ot,er no%es on t,e sa&et0

s0stem network! T,en a## t,e ot,er no%es on t,e sa&et0 s0stem network can receive t,e

#atest airba' sensor in&ormation &rom t,e router at t,e same time. acknow#e%'e i& t,e

messa'e was receive% proper#0. an% %eci%e w,et,er to uti#i?e t,is in&ormation or %iscar% it!

-. CAN ,"'i) what it !",,"ws?

Answer: Wire% A" #o'ic

. What is CAN Ar/itrati"n?Answer: CA" Arbitration is not,in' but t,e no%e tr0in' to take contro# on t,e CA" bus!

0. "w CAN wi,, !",,"w the Ar/itrati"n?

Answer: CS3A@C A3 (Arbitration on 3essa'e riorit0*

Two bus no%es ,ave 'ot a transmission re1uest! T,e bus access met,o% is CS3A@CA3

(Carrier Sense 3u#tip#e Access wit, Co##ision etection an% Arbitration on 3essa'e riorit0*!

Accor%in' to t,is a#'orit,m bot, network no%es wait unti# t,e bus is &ree (Carrier Sense*! In

t,at case t,e bus is &ree bot, no%es transmit t,eir %ominant start bit (3u#tip#e Access*!

)ver0 bus no%e rea%s back bit b0 bit &rom t,e bus %urin' t,e comp#ete messa'e an%

compares t,e transmitte% va#ue wit, t,e receive% va#ue! As #on' as t,e bits are i%entica#

&rom bot, transmitters not,in' ,appens! T,e /rst time t,ere was a %i=erence + in t,is

e4amp#e t,e <t, bit o& t,e messa'e + t,e arbitration process takes p#ace "o%e A transmits a

%ominant #eve#. no%e B transmits a recessive #eve#! T,e recessive #eve# wi## be overwritten b0

t,e %ominant #eve#! T,is is %etecte% b0 no%e B because t,e transmitte% va#ue is not e1ua# to

t,e receive% va#ue (Co##ision etection*! At t,is point o& time no%e B ,as #ost t,e arbitration.

stops t,e transmission o& an0 &urt,er bit imme%iate#0 an% switc,es to receive mo%e.

because t,e messa'e t,at ,as won t,e arbitration must possib#0 be processe% b0 t,is no%e

(Arbitration on 3essa'e riorit0*

5or e4amp#e. consi%er t,ree CA" %evices eac, tr0in' to transmit messa'es

D evice + a%%ress -- (%ecima# or 888888 binar0*

D evice 2 + a%%ress : (8888888*D evice - + a%%ress 7< (88888*

Assumin' a## t,ree see t,e bus is i%#e an% be'in transmittin' at t,e same time. t,is is ,ow

t,e arbitration works out! A## t,ree %evices wi## %rive t,e bus to a %ominant state &or t,e

start$o&$&rame (SO5* an% t,e two most si'ni/cant bits o& eac, messa'e i%enti/er! )ac,

%evice wi## monitor t,e bus an% %etermine success! W,en t,e0 write bit 7 o& t,e messa'e I.



t,e %evice writin' messa'e I -- wi## notice t,at t,e bus is in t,e %ominant state w,en it

was tr0in' to #et it be recessive. so it wi## assume a co##ision an% 'ive up &or now! T,e

remainin' %evices wi## continue writin' bits unti# bit :. t,en t,e %evice writin' messa'e I

7< wi## notice a co##ision an% abort transmission! T,is #eaves t,e %evice writin' messa'e I

: remainin'! It wi## continue writin' bits on t,e bus unti# comp#ete or an error is %etecte%!

"otice t,at t,is met,o% o& arbitration wi## a#wa0s cause t,e #owest numerica# va#ue messa'eI to ,ave priorit0! T,is same met,o% o& bit$wise arbitration an% prioriti?ation app#ies to t,e

7$bit e4tension in t,e e4ten%e% &ormat as we##!

2. What is the s+eed "! CAN?

Answer: 8m E3bps an% i& t,e cab#e #en't, increases wi## %ecrease t,e spee%. %ue to R9C

on t,e cab#e!

3. I! master sends 0* and S,a&e sends 0** whi)h wi,, 'et the ar/itrati"n?

Answer: Starts &rom 3SB. /rst nibb#e is same. 3aster sen%s <. s#aves a#so sen%s < t,e

messa'e wit, more %ominant bits wi## 'ain t,e arbitration. #owest t,e messa'e i%enti/er

,i',er t,e priorit0!1(. Standard CAN and E4tended CAN di5eren)e?

Answer: "umber o& i%enti/ers can be accommo%ate% &or stan%ar% &rame are 2power!

"umber o& i%enti/ers more compare to base &rame. &or e4ten%e% &rame are 2power2F!

I) bit + &or e4ten%e% &rame!

I) bit + 8 &or Stan%ar% &rame!

11. What is /it stu6n'?

Answer: CA" uses a "on$Return$to$Gero protoco#. "RG$:. wit, bit stun'! T,e i%ea be,in%

bit stun' is to provi%e a 'uarantee% e%'e on t,e si'na# so t,e receiver can res0nc,roni?ewit, t,e transmitter be&ore minor c#ock %iscrepancies between t,e two no%es can cause a

prob#em! Wit, "RG$: t,e transmitter transmits at most /ve consecutive bits wit, t,e same

va#ue! A&ter /ve bits wit, t,e same va#ue (?ero or one*. t,e transmitter inserts a stu= bit wit,

t,e opposite state!

1. What is the use "! /it stu6n'?

Answer: 9on' "RG messa'es cause prob#ems in receivers

D C#ock %ri&t means t,at i& t,ere are no e%'es. receivers #ose track o& bits

D erio%ic e%'es a##ow receiver to res0nc,roni?e to sen%er c#ock

1$. What are the !un)ti"ns "! CAN trans)ei&er?

Answer: T,e transceiver provi%es %i=erentia# transmit capabi#it0 to t,e bus an% %i=erentia#

receive capabi#it0 to t,e CA" contro##er! Transceiver provi%es an a%vance% inter&ace between

t,e protoco# contro##er an% t,e p,0sica# bus in a Contro##er Area "etwork (CA"* no%e!

T0pica##0. eac, no%e in a CA" s0stem must ,ave a %evice to convert t,e %i'ita# si'na#s

'enerate% b0 a CA" contro##er to si'na#s suitab#e &or transmission over t,e bus cab#in'

(%i=erentia# output*! It a#so provi%es a bu=er between t,e CA" contro##er an% t,e ,i',$



vo#ta'e spikes t,at can be 'enerate% on t,e CA" bus b0 outsi%e sources ()3I. )S.

e#ectrica# transients. etc!*!

T,e can transceiver is a %evice w,ic, %etects t,e si'na# #eve#s t,at are use% on t,e CA" bus

to t,e #o'ica# si'na# #eve#s reco'ni?e% b0 a microcontro##er!

1*. 7un)ti"na,it% "! 8ata ,in# ,a%er in CAN?

Answer: 99C 9"'i)a, 9in# C"ntr",; < Over#oa% contro#. noti/cation. 3essa'e /#terin' an%

Recover0 mana'ement &unctions!

MAC Medium A))ess C"ntr",; < )ncapsu#ation@ %e$capsu#ation. error %etection an%

contro#. stun' an% %e$stun' an% seria#i?ation@%e$seria#i?ation!

1-. What is meant /% s%n)hr"ni=ati"n?

Answer: S0nc,roni?ation is timekeepin' w,ic, re1uires t,e coor%ination o& events to

operate a s0stem in unison!

1. What is meant /% ard s%n)hr"ni=ati"n and s"!t s%n)hr"ni=ati"n?

Answer: Har% S0nc,roni?ation to be per&orme% at ever0 e%'e &rom recessive$to$%ominante%'e %urin' Bus I%#e! A%%itiona##0. Har% S0nc,roni?ation is re1uire% &or eac, receive% SO5

bit! An SO5 bit can be receive% bot, %urin' Bus I%#e. an% a#so %urin' Suspen% Transmission

an% at t,e en% o& Inter&rame Space! An0 no%e %isab#es Har% S0nc,roni?ation i& it samp#es an

e%'e &rom recessive to %ominant or i& it starts to sen% t,e %ominant SO5 bit!

Two t0pes o& s0nc,roni?ation are supporte%

< ard s%n)hr"ni=ati"n is %one wit, a &a##in' e%'e on t,e bus w,i#e t,e bus is i%#e. w,ic,

is interprete% as a Start o& &rame (SO5*! It restarts t,e interna# Bit Time 9o'ic!

< S"!t s%n)hr"ni=ati"n is use% to #en't,en or s,orten a bit time w,i#e a CA" &rame is

receive%!10. What is the di5eren)e /etween !un)ti"n and +h%si)a, addressin'?

Answer: 5unctiona# a%%ressin' is an a%%ressin' sc,eme t,at #abe#s messa'es base%

upon t,eir operation co%e or content! ,0sica# a%%ressin' is an a%%ressin' sc,eme t,at

#abe#s messa'es base% upon t,e p,0sica# a%%ress #ocation o& t,eir source an%@or

%estination(s*!

12. What ha++ens i! I ha&e t" send m"re than 2>/%tes "! data?

Answer: T,e F-F stan%ar% ,as %e/ne% a met,o% o& communicatin' more t,an 7 b0tes o&

%ata b0 sen%in' t,e %ata in packets as speci/e% in t,e Transport rotoco# (T*! T,ere are two

t0pes o& T. one &or broa%castin' t,e %ata. an% t,e ot,er &or sen%in' it to a speci/c a%%ress!

TC consists o& components + S". 53I. OC an% C3!

A TC is a combination o& &our in%epen%ent /e#%s t,e Suspect arameter "umber (S"* o&

t,e c,anne# or &eature t,at can ,ave &au#tsJ a 5ai#ure 3o%e I%enti/er (53I* o& t,e speci/c

&au#tJ t,e occurrence count (OC* o& t,e S"@53I combinationJ an% t,e S" conversion

met,o% (C3* w,ic, te##s t,e receivin' mo%e ,ow to interpret t,e S"! To'et,er. t,e S".

53I. OC an% C3 &orm a number t,at a %ia'nostic too# can use to un%erstan% t,e &ai#ure t,at

is bein' reporte%!



5i'ure + 3essa'e &ormat

13. What is W@(((?

Answer: ;W 2888(ISO2-8* is a ia'nostic communications stan%ar%! Speci/es possib#e

s0stem con/'urations usin' t,e ; K 9 #ines! As F$2 but #imite% to t,e p,0sica#

c,aracteristics! Speci/es possib#e s0stem con/'urations usin' t,e ; K 9 #ines!

: Bau% wake up as F$ 2

"ew &ast initia#isation met,o%

(. What is O8II?

Answer: On$Boar% ia'nostics in an automotive conte4t is a 'eneric term re&errin' to a

ve,ic#eLs se#&$%ia'nostic an% reportin' capabi#it0

1. Wh% 8ia'n"sti) Standards?

Answer: As s0stems 'ot more comp#e4 t,e #ink between cause an% s0mptom became #ess

obvious! T,is meant t,at e#ectronic s0stems ,a% to ,ave some #eve# o& se#& %ia'nosis an% to

communicate to t,e outsi%e wor#%! Initia##0 man0 s0stems use% t,eir own protoco#s w,ic,

meant t,at 'ara'es ,a% to ,ave a #ar'e number o& too#s + even to %ia'nose a sin'#e ve,ic#e!

. What is meant /% &eriB)ati"n and &a,idati"n??Answer: Meri/cation an% Ma#i%ation (MKM* is t,e process o& c,eckin' t,at a so&tware s0stem

meets speci/cations an% t,at it &u#/##s its inten%e% purpose! It is norma##0 part o& t,e

so&tware testin' process o& a proNect!

Accor%in' to t,e Capabi#it0 3aturit0 3o%e# (C33I$SW v!*.

Meri/cation T,e process o& eva#uatin' so&tware to %etermine w,et,er t,e pro%ucts o&

a 'iven %eve#opment p,ase satis&0 t,e con%itions impose% at t,e start o& t,at p,ase!

Ma#i%ation T,e process o& eva#uatin' so&tware %urin' or at t,e en% o& t,e

%eve#opment process to %etermine w,et,er it satis/es speci/e% re1uirements!

VeriB)ati"n s,ows con&ormance wit, speci/cationJ &a,idati"n s,ows t,at t,epro'ram meets t,e customerLs nee%s

$. Can %"u ha&e tw" transmitters usin' the same e4a)t header Be,d?

Answer: "o + t,at wou#% pro%uce a bus con>ict

D Un#ess 0ou ,ave mi%%#eware t,at ensures on#0 one no%e can transmit at a time

+ 5or e4amp#e use a #ow priorit0 messa'e as a token to emu#ate token$passin'



*. CAN +h%si)a, ,a%er &",ta'e ,e&e,s

-. CAN /it timin':

Accor%in' to t,e CA" speci/cation. t,e bit time is %ivi%e% into &our se'ments! T,e

S0nc,roni?ation Se'ment. t,e ropa'ation Time Se'ment. t,e ,ase Bu=er Se'ment . an%

t,e ,ase Bu=er Se'ment 2! )ac, se'ment consists o& a speci/c. pro'rammab#e number o&

time 1uanta (see Tab#e *! T,e #en't, o& t,e time 1uantum (t1*. w,ic, is t,e basic time unit

o& t,e bit time. is %e/ne% b0 t,e CA" contro##erLs s0stem c#ock &s0s an% t,e Bau% Rate

resca#er (BR* t1 BR @ &s0s! T0pica# s0stem c#ocks are &s0s &osc or &s0s &osc@2!

T,e S0nc,roni?ation Se'ment S0ncPSe' is t,at part o& t,e bit time w,ere e%'es o& t,e CA"

bus #eve# are e4pecte% to occurJ t,e %istance between an e%'e t,at occurs outsi%e o&

S0ncPSe' an% t,e S0ncPSe' is ca##e% t,e p,ase error o& t,at e%'e! T,e ropa'ation Time

Se'ment ropPSe' is inten%e% to compensate &or t,e p,0sica# %e#a0 times wit,in t,e CA"network! T,e ,ase Bu=er Se'ments ,asePSe' an% ,asePSe'2 surroun% t,e Samp#e

oint! T,e (Re$*S0nc,roni?ation ump Wi%t, (SW* %e/nes ,ow &ar a res0nc,roni?ation ma0

move t,e Samp#e oint insi%e t,e #imits %e/ne% b0 t,e ,ase Bu=er Se'ments to

compensate &or e%'e p,ase errors!



Two t0pes o& s0nc,roni?ation e4ist Har% S0nc,roni?ation an% Res0nc,roni?ation! A Har%

S0nc,roni?ation is %one once at t,e start o& a &rameJ insi%e a &rame on#0 Res0nc,roni?ations

occur!

ard S%n)hr"ni=ati"n A&ter a ,ar% s0nc,roni?ation. t,e bit time is restarte% wit, t,e en%

o& S0ncPSe'. re'ar%#ess o& t,e e%'e p,ase error! T,us ,ar% s0nc,roni?ation &orces t,e e%'e

w,ic, ,as cause% t,e ,ar% s0nc,roni?ation to #ie wit,in t,e s0nc,roni?ation se'ment o& t,e

restarte% bit time!

it Res%n)hr"ni=ati"n Res0nc,roni?ation #ea%s to a s,ortenin' or #en't,enin' o& t,e bit

time suc, t,at t,e position o& t,e samp#e point is s,i&te% wit, re'ar% to t,e e%'e!

. 7"rmu,a !"r audrate )a,)u,ati"n?

T,e bau% rate is ca#cu#ate% as

baud rate (bits per second) = 18.432 x 10^6 / BRP / (1 + TSEG1 + TSEG2)

0. What ha++en when tw" CAN n"des are sendin' same identiBer at a same

time?

Two no%es on t,e network are not a##owe% to sen% messa'es wit, t,e same i%! I& two no%es

tr0 to sen% a messa'e wit, t,e same i% at t,e same time arbitration wi## not work! Instea%.

one o& t,e transmittin' no%es wi## %etect t,at ,is messa'e is %istorte% outsi%e o& t,e

arbitration /e#%! T,e no%es wi## t,en use t,e error ,an%#in' o& CA". w,ic, in t,is case

u#timate#0 wi## #ea% to one o& t,e transmittin' no%e bein' switc,e% o= (bus$o= mo%e*!

2. what is the di5eren)e /etween it Rate and aud Rate?

T,e %i=erence between Bit an% Bau% rate is comp#icate% an% intertwinin'! Bot, are

%epen%ent an% inter$re#ate%! But t,e simp#est e4p#anation is t,at a Bit Rate is ,ow man0%ata bits are transmitte% per secon%! A bau% Rate is t,e number o& times per secon% a

si'na# in a communications c,anne#c,an'es!Bit rates measure t,e number o& %ata bits

(t,at is 8s an% s* transmitte% in one secon% in a communication c,anne#! A /'ure o& 288

bits per secon% means 288 ?eros or ones can be transmitte% in one secon%. ,ence t,e

abbreviation bps! In%ivi%ua# c,aracters (&or e4amp#e #etters or numbers* t,at are a#so

re&erre% to as b0tes are compose% o& severa# bits!A bau% rate is t,e number o& times a si'na#

in a communications c,anne# c,an'es state or varies! 5or e4amp#e. a 288 bau% rate means

t,at t,e c,anne# can c,an'e states up to 288 times per secon%! T,e term c,an'e state

means t,at it can c,an'e &rom 8 to or &rom to 8 up to (in t,is case. 288* times per

secon%! It a#so re&ers to t,e actua# state o& t,e connection. suc, as vo#ta'e. &re1uenc0. orp,ase #eve#*!T,e main %i=erence between t,e two is t,at one c,an'e o& state can transmit

one bit. or s#i',t#0 more or #ess t,an one bit. t,at %epen%s on t,e mo%u#ation tec,ni1ue

use%! So t,e bit rate (bps* an% bau% rate (bau% per secon%* ,ave t,is connectionbps

bau% per secon% 4 t,e number o& bit per bau%T,e mo%u#ation tec,ni1ue %etermines t,e

number o& bit per bau%! Here are two e4amp#esW,en 5S; (5re1uenc0 S,i&t ;e0in'. a

transmission tec,ni1ue* is use%. eac, bau% transmits one bit! On#0 one c,an'e in state is

re1uire% to sen% a bit! T,us. t,e mo%emLs bps rate is e1ua# to t,e bau% rate! W,en a bau%



rate o& 288 is use%. a mo%u#ation tec,ni1ue ca##e% p,ase mo%u#ation t,at transmits &our

bits per bau% is use%! So288 bau% 4 bits per bau% F688 bpsSuc, mo%ems are capab#e

o& F688 bps operation!

C Inter&iew Questi"ns :

1. What is the di5eren)e /etween

de),arati"n and deBniti"n?Answer: 8eBniti"n means w,ere a variab#e or

&unction is %e/ne% in rea#it0 an% actua# memor0

is a##ocate% &or variab#e or &unction!

8e),arati"n means Nust 'ivin' a re&erence o& a

variab#e an% &unction!

. What are the di5erent st"ra'e

),asses in C?

Answer: AUTOD STATICD ETERND REFISTER

aut" is t,e %e&au#t stora'e c#ass &or #oca# variab#es!

int CountJ

auto int 3ont,J

V

re'ister is use% to %e/ne #oca# variab#es t,at s,ou#% be store% in a re'ister instea% o& RA3

T,is means t,at t,e variab#e ,as a ma4imum si?e e1ua# to t,e re'ister si?e (usua##0 one

wor%* an% cannot ,ave t,e unar0 KL operator app#ie% to it (as it %oes not ,ave a memor0#ocation*! {

register int Miles;

}

Re'ister s,ou#% on#0 be use% &or variab#es t,at re1uire 1uick access + suc, as counters! It

s,ou#% a#so be note% t,at %e/nin' re'isterL 'oes not mean t,at t,e variab#e wi## be store% in

a re'ister! It means t,at it 3IXHT be store% in a re'ister + %epen%in' on ,ar%ware an%imp#ementation restrictions!

stati) < St"ra'e C,ass

stati) is t,e %e&au#t stora'e c#ass &or '#oba# variab#es! T,e two variab#es be#ow

()"unt an% r"ad* bot, ,ave a static stora'e c#ass!

static int CountJint Roa%Jmain(*



print&(Y%Zn. Count*Jprint&(Y%Zn. Roa%*JV

staticL can a#so be %e/ne% wit,in a &unction! I& t,is is %one. t,e variab#e is inita#i?e% at

compi#ation time an% retains its va#ue between ca##s! Because it is initia#i?e% at compi#ation

time. t,e initia#i?ation va#ue must be a constant! T,is is serious stu= + trea% wit, care!

voi% 5unc(voi%*static CountJVHere is an e4amp#e

T,ere is one ver0 important use &or staticL! Consi%er t,is bit o& co%e!

c,ar [5unc(voi%*Jmain(*c,ar [Te4tJTe4t 5unc(*JVc,ar [5unc(voi%*c,ar

Te4t2\8]martinJreturn(Te4t2*JV

5uncL returns a pointer to t,e memor0 #ocation w,ere Te4t2 starts BUT Te4t2 ,as a stora'e

c#ass o& auto an% wi## %isappear w,en we e4it t,e &unction an% cou#% be overwritten b0

somet,in' e#se! T,e answer is to speci&0

static c,ar Te4t\8]martinJ

T,e stora'e assi'ne% to Te4t2 wi## remain reserve% &or t,e %uration i& t,e pro'ram!

e4tern < st"ra'e C,ass

e4tern %e/nes a '#oba# variab#e t,at is visab#e to A99 obNect mo%u#es! W,en 0ou use

e4ternL t,e variab#e cannot be inita#i?e% as a## it %oes is point t,e variab#e name at a stora'e

#ocation t,at ,as been previous#0 %e/ne%!

Source Source 2

^^+ ^^+

e4tern int countJ int count:J

write(* main(*

print&(count is Y%Zn. count*J write(*J

V V

Count in source wi## ,ave a va#ue o& :! I& source c,an'es t,e va#ue o& count + source 2

wi## see t,e new va#ue! Here are some e4amp#e source /#es!

$. What is interru+t?



Answer: Interrupts (a#so known as traps or e4ceptions in some processors* are a tec,ni1ue

o& %ivertin' t,e processor &rom t,e e4ecution o& t,e current pro'ram so t,at it ma0 %ea# wit,

some event t,at ,as occurre%! Suc, an event ma0 be an error &rom a perip,era#. or simp#0

t,at an I@O %evice ,as /nis,e% t,e #ast task it was 'iven an% is now rea%0 &or anot,er! An

interrupt is 'enerate% in 0our computer ever0 time 0ou t0pe a ke0 or move t,e mouse! _ou

can t,ink o& it as a ,ar%ware$'enerate% &unction ca##! *. What is ardware Interru+t?

Answer: T,ere are two wa0s o& te##in' w,en an I@O %evice (suc, as a seria# contro##er or a

%isk contro##er* is rea%0 &or t,e ne4t se1uence o& %ata to be trans&erre%! T,e /rst is bus0

waitin' or po##in'. w,ere t,e processor continuous#0 c,ecks t,e %eviceLs status re'ister unti#

t,e %evice is rea%0! T,is wastes t,e processorLs time but is t,e simp#est to imp#ement! 5or

some time$critica# app#ications. po##in' can re%uce t,e time it takes &or t,e processor to

respon% to a c,an'e o& state in a perip,era#!

-. What is S"!tware Interru+t?

Answer: A so&tware interrupt is 'enerate% b0 an instruction! It is t,e #owest$priorit0

interrupt an% is 'enera##0 use% b0 pro'rams to re1uest a service to be per&orme% b0 t,es0stem so&tware (operatin' s0stem or /rmware*!

8i5eren)e /etween ardware Interru+t and S"!tware Interru+t

An interrupt is a specia# si'na# t,at causes t,e computerLs centra# processin' unit to

suspen% w,at it is %oin' an% trans&ers its contro# to a specia# pro'ram ca##e% an interru+t

hand,er! T,e responsibi#it0 o& an interrupt ,an%#er is to %etermine w,at cause% t,e

interrupt. service t,e interrupt an% t,en return t,e contro# to t,e point &rom w,ere t,e

interrupt was cause%! T,e %i=erence between hardware interru+t an% s"!tware

interru+t is as be#ow

ardware Interru+t T,is interrupt is cause% b0 some e4terna# %evice suc, as re1uest to

start an I@O or occurrence o& a ,ar%ware &ai#ure!

S"!tware Interru+t T,is interrupt can be invoke% wit, t,e ,e#p o& I"T instruction! A

pro'rammer tri''ere% t,is event t,at imme%iate#0 stops e4ecution o& t,e pro'ram an%

passes e4ecution over to t,e I"T ,an%#er! T,e I"T ,an%#er is usua##0 a part o& t,e operatin'

s0stem an% %etermines t,e action to be taken e!'! output to t,e screen. e4ecute /#e etc!

T,us a so&tware interrupt as itLs name su''ests is %riven b0 a so&tware instruction an% a

,ar%ware interrupt is t,e resu#t o& e4terna# causes!

. What is Interru+t ,aten)%? "w d" %"u measure interru+t ,aten)%? "w t"

redu)e the interru+t ,aten)%?

Answer: Interrupt #atenc0 is t,e time between interrupt re1uest an% e4ecution o& /rst

instruction o& t,e ISR!We nee% a osci##oscope or a #o'ic state ana#0?er! B0 enterin' t,e interrupt service routine

(ISR*. 0ou nee% to activate an avai#ab#e port on 0our ,ar%ware (#ike a #e% port or so on* an%

%eactivate it Nust be&ore returnin' &rom t,e ISR! _ou can %o t,at b0 writin' t,e appropriate

co%e!



B0 connectin' one input o& t,e osci##oscope (or #o'ic state ana#0?er* to t,e I"TR pin o& t,e

microprocessor an% t,e secon% one to t,e port 0ou activate@%eactivate. 0ou can measure

t,e #atenc0 time an% t,e %uration o& t,e ISR

Causes "! interru+t ,aten)ies

T,e /rst %e#a0 is t0pica##0 in t,e ,ar%ware T,e interrupt re1uest si'na# nee%s to be

s0nc,roni?e% to t,e CU c#ock! epen%in' on t,e s0nc,roni?ation #o'ic. t0pica##0 up

to - CU c0c#es can be #ost be&ore t,e interrupt re1uest ,as reac,e% t,e CU core!

T,e CU wi## t0pica##0 comp#ete t,e current instruction! T,is instruction can take a #ot

o& c0c#esJ on most s0stems. %ivi%e. pus,$mu#tip#e or memor0$cop0 instructions are

t,e instructions w,ic, re1uire most c#ock c0c#es! On top o& t,e c0c#es re1uire% b0 t,e

CU. t,ere are in most cases a%%itiona# c0c#es re1uire% &or memor0 access! In an

AR3< s0stem. t,e instruction ST3B S`.R8$R.9RVJ us, parameters an% perm!

Re'isters is t0pica##0 t,e worst case instruction! It stores - -2$bit re'isters on t,e

stack! T,e CU re1uires : c#ock c0c#es! T,e memor0 s0stem ma0 re1uire a%%itiona#

c0c#es &or wait states! A&ter comp#etion o& t,e current instruction. t,e CU per&orms a mo%e switc, or

pus,es re'isters (t0pica##0 C an% >a' re'isters* on t,e stack! In 'enera#. mo%ern

CUs (suc, as AR3* per&orm a mo%e switc,. w,ic, re1uires #ess CU c0c#es t,an

savin' re'isters!

ipe#ine /## 3ost mo%ern CUs are pipe#ine%! )4ecution o& an instruction ,appens in

various sta'es o& t,e pipe#ine! An instruction is e4ecute% w,en it ,as reac,e% its /na#

sta'e o& t,e pipe#ine! Since t,e mo%e switc, ,as >us,e% t,e pipe#ine. a &ew e4tra

c0c#es are re1uire% to re/## t,e pipe#ine!

0. V"nneuman and har&ard ar)hite)ture di5eren)es?

Answer: T,e name Harvar% Arc,itecture comes &rom t,e Harvar% 3ark I re#a0$base%

computer! T,e most obvious c,aracteristic o& t,e Harvar% Arc,itecture is t,at it ,as

p,0sica##0 separate si'na#s an% stora'e &or co%e an% %ata memor0! It is possib#e to access

pro'ram memor0 an% %ata memor0 simu#taneous#0! T0pica##0. co%e (or pro'ram* memor0 is

rea%$on#0 an% %ata memor0 is rea%$write! T,ere&ore. it is impossib#e &or pro'ram contents to

be mo%i/e% b0 t,e pro'ram itse#&!

T,e vonneumann Arc,itecture is name% a&ter t,e mat,ematician an% ear#0 computer

scientist o,n von "eumann! von "eumann mac,ines ,ave s,are% si'na#s an% memor0 &or

co%e an% %ata! T,us. t,e pro'ram can be easi#0 mo%i/e% b0 itse#& since it is store% in rea%$

write memor0!

ar&ard ar)hite)ture ,as separate %ata an% instruction busses. a##owin' trans&ers to be

per&orme% simu#taneous#0 on bot, buses! V"n Neumann ar)hite)ture ,as on#0 one bus

w,ic, is use% &or bot, %ata trans&ers an% instruction &etc,es. an% t,ere&ore %ata trans&ers

an% instruction &etc,es must be sc,e%u#e% + t,e0 cannot be per&orme% at t,e same time!

It is possib#e to ,ave two separate memor0 s0stems &or a ar&ard ar)hite)ture! As #on' as

%ata an% instructions can be &e% in at t,e same time. t,en it %oesnLt matter w,et,er it

comes &rom a cac,e or memor0! But t,ere are prob#ems wit, t,is! Compi#ers 'enera##0



embe% %ata (#itera# poo#s* wit,in t,e co%e. an% it is o&ten a#so necessar0 to be ab#e to write

to t,e instruction memor0 space. &or e4amp#e in t,e case o& se#& mo%i&0in' co%e. or. i& an

AR3 %ebu''er is use%. to set so&tware breakpoints in memor0! I& t,ere are two comp#ete#0

separate. iso#ate% memor0 s0stems. t,is is not possib#e! T,ere must be some kin% o& bri%'e

between t,e memor0 s0stems to a##ow t,is!

Usin' a simp#e. uni/e% memor0 s0stem to'et,er wit, a Harvar% arc,itecture is ,i',#0inecient! Un#ess it is possib#e to &ee% %ata into bot, buses at t,e same time. it mi',t be

better to use a von "eumann arc,itecture processor!

Use "! )a)hes

At ,i',er c#ock spee%s. cac,es are use&u# as t,e memor0 spee% is proportiona##0

s#ower! ar&ard ar)hite)tures ten% to be tar'ete% at ,i',er per&ormance s0stems. an% so

cac,es are near#0 a#wa0s use% in suc, s0stems!

V"n Neumann ar)hite)tures usua##0 ,ave a sin'#e uni/e% cac,e. w,ic, stores bot,

instructions an% %ata! T,e proportion o& eac, in t,e cac,e is variab#e. w,ic, ma0 be a 'oo%

t,in'! It wou#% in princip#e be possib#e to ,ave separate instruction an% %ata cac,es. storin'%ata an% instructions separate#0! T,is probab#0 wou#% not be ver0 use&u# as it wou#% on#0 be

possib#e to ever access one cac,e at a time!

Cac,es &or Harvar% arc,itectures are ver0 use&u#! Suc, a s0stem wou#% ,ave separate

cac,es &or eac, bus! Tr0in' to use a s,are% cac,e on a Harvar% arc,itecture wou#% be ver0

inecient since t,en on#0 one bus can be &e% at a time! Havin' two cac,es means it is

possib#e to &ee% bot, buses simu#taneous#0!e4act#0 w,at is necessar0 &or a Harvar%

arc,itecture!

T,is a#so a##ows to ,ave a ver0 simp#e uni/e% memor0 s0stem. usin' t,e same a%%ress

space &or bot, instructions an% %ata! T,is 'ets aroun% t,e prob#em o& #itera# poo#s an% se#&mo%i&0in' co%e! W,at it %oes mean. ,owever. is t,at w,en startin' wit, empt0 cac,es. it is

necessar0 to &etc, instructions an% %ata &rom t,e sin'#e memor0 s0stem. at t,e same time!

Obvious#0. two memor0 accesses are nee%e% t,ere&ore be&ore t,e core ,as a## t,e %ata

nee%e%! T,is per&ormance wi## be no better t,an a von "eumann arc,itecture! However. as

t,e cac,es /## up. it is muc, more #ike#0 t,at t,e instruction or %ata va#ue ,as a#rea%0 been

cac,e%. an% so on#0 one o& t,e two ,as to be &etc,e% &rom memor0! T,e ot,er can be

supp#ie% %irect#0 &rom t,e cac,e wit, no a%%itiona# %e#a0! T,e best per&ormance is ac,ieve%

w,en bot, instructions an% %ata are supp#ie% b0 t,e cac,es. wit, no nee% to access e4terna#

memor0 at a##!

T,is is t,e most sensib#e compromise an% t,e arc,itecture use% b0 AR3s Harvar% processor

cores! Two separate memor0 s0stems can per&orm better. but wou#% be %icu#t to

imp#ement

2. RISC and CISC di5eren)es?

Answer:

CISC: Comp#e4 Instruction Set Computer*



E': Inte# an% A3 CULs

CISC c,ips ,ave a #ar'e amount o& %i=erent an% comp#e4 instructions!

CISC c,ips are re#ative#0 s#ow (compare% to RISC c,ips* per instruction. but use #itt#e

(#ess t,an RISC* instructions!

CISC arc,itecture is to comp#ete a task in as &ew #ines o& assemb#0 as possib#e! T,is is

ac,ieve% b0 bui#%in' processor ,ar%ware t,at is capab#e o& un%erstan%in' an%e4ecutin' a series o& operations!

In CISC. compi#er ,as to %o ver0 #itt#e work to trans#ate a ,i',$#eve# #an'ua'e

statement into assemb#0! Because t,e #en't, o& t,e co%e is re#ative#0 s,ort. ver0 #itt#e

RA3 is re1uire% to store instructions! T,e emp,asis is put on bui#%in' comp#e4

instructions %irect#0 into t,e ,ar%ware!

W,en e4ecute%. t,is instruction #oa%s t,e two va#ues into separate re'isters.

mu#tip#ies t,e operan%s in t,e e4ecution unit. an% t,en stores t,e pro%uct in t,e

appropriate re'ister!

RISC: Re%uce% Instruction Set Computer;

E': App#e. AR3 processors 5ewer. simp#er an% &aster instructions wou#% be better. t,an t,e #ar'e. comp#e4 an%

s#ower CISC instructions! However. more instructions are nee%e% to accomp#is, a

task!

RISC c,ips re1uire &ewer transistors. w,ic, makes t,em easier to %esi'n an% c,eaper

to pro%uce!

itLs easier to write power&u# optimi?e% compi#ers. since &ewer instructions e4ist!

RISC is c,eaper an% &aster!

RISC puts a 'reater bur%en on t,e so&tware! So&tware nee%s to become more

comp#e4! So&tware %eve#opers nee% to write more #ines &or t,e same tasks! T,ere&ore

t,e0 ar'ue t,at RISC is not t,e arc,itecture o& t,e &uture. since conventiona# CISC

c,ips are becomin' &aster an% c,eaper Simp#e instructions t,at can be e4ecute% wit,in one c#ock c0c#e!

3U9T comman% %escribe% above cou#% be %ivi%e% into t,ree separate comman%s

9OA. w,ic, moves %ata &rom t,e memor0 bank to a re'ister. RO. w,ic, /n%s

t,e pro%uct o& two operan%s #ocate% wit,in t,e re'isters. an% STOR). w,ic, moves

%ata &rom a re'ister to t,e memor0 banks!

At /rst. t,is ma0 seem #ike a muc, #ess ecient wa0 o& comp#etin' t,e operation!

Because t,ere are more #ines o& co%e. more RA3 is nee%e% to store t,e assemb#0

#eve# instructions! T,e compi#er must a#so per&orm more work to convert a ,i',$#eve#

#an'ua'e statement into co%e o& t,is &orm!

Separatin' t,e 9OA an% STOR) instructions actua##0 re%uces t,e amount o&work t,at t,e computer must per&orm!

3aNor prob#em o& RISC + t,e0 %onLt a=or% t,e wi%esprea% compatibi#it0. t,at 476

c,ips %o!

CISC RISC)mp,asis on ,ar%ware )mp,asis on so&twareInc#u%es mu#ti$c#ockcomp#e4 instructions

Sin'#e$c#ock.re%uce% instruction on#0



3emor0$to$memor09OA an% STOR)incorporate% in instructions

Re'ister to re'ister9OA an% STOR)are in%epen%ent instructions

Sma## co%e si?es.,i', c0c#es per secon%

9ow c0c#es per secon%.#ar'e co%e si?es

Transistors use% &or storin'

comp#e4 instructions

Spen%s more transistors

on memor0 re'istersCISC RISCComp#e4 instructions re1uire mu#tip#ec0c#es

Re%uce% instructionstake c0c#e

3an0 instructions can re&erencememor0

On#0 9oa% an% Storeinstructions canre&erence memor0

Instructions are e4ecute% one at a timeUses pipe#inin' toe4ecute instructions

5ew 'enera# re'isters 3an0 'enera# re'isters

3. What are the startu+ )"de ste+s?

Answer:

! isab#e a## t,e interrupts!

2! Cop0 an% initia#i?e% %ata &rom RO3 to RA3!

-! Gero t,e uninitia#i?e% %ata area!

! A##ocate space an% &or initia#i?e t,e stack!

:! Initia#i?e t,e processor stack pointer

6! Ca## main

1(. What are the /""tin' ste+s !"r a C@U?

Answer:

T,e power supp#0 %oes a se#& c,eck an% sen%s a power$'oo% si'na# to t,e CU!

T,e CU starts e4ecutin' t,e co%e store% in RO3 on t,e mot,erboar% starts t,e a%%ress

8455558!

T,e routines in RO3 test t,e centra# ,ar%ware. searc, &or vi%eo RO3. per&orm a

c,ecksum on t,e vi%eo RO3 an% e4ecutes t,e routines in vi%eo RO3!

T,e routines in t,e mot,er boar% RO3 t,en continue searc,in' &or an0 RO3.

c,ecksum an% e4ecutes t,ese routines!

A&ter per&ormin' t,e OST (ower On$Se#& Test* is e4ecute%! T,e s0stem wi## searc,

&or a boot %evice!

Assumin' t,at t,e va#i% boot %evice is &oun%. IO!S_S is #oa%e% into memor0 an%

e4ecute%!IO!S_S consists primari#0 o& initia#i?ation co%e an% e4tension to t,e

memor0 boar% RO3 BIOS!

3SOS!S_S is #oa%e% into memor0 an% e4ecute%! 3SOS!S_S contains t,e OSroutines!

CO"5IX!S_S (create% an% mo%i/e% b0 t,e user! #oa% a%%itiona# %evice %rivers &or

perip,era# %evices*. CO33A"!CO3 (It is comman% interpreter$ It trans#ates t,e

comman%s entere% b0 t,e user! It a#so contains interna# OS comman%s! It e4ecutes

an% AUTO))C!BAT*.AUTO))C!BAT (It contains a## t,e comman%s t,at t,e

user wants w,ic, are e4ecute% automatica##0 ever0 time t,e compute% is starte%*!



8 finc#u%e gst%io!,g82 f%e/ne BIXP)"IA" 88- f%e/ne 9ITT9)P)"IA" 8 int main(*8: 86 int va#ueJ

8< va#ue en%ian(*J87 i& (va#ue *8F print&(g3ac,ine is #itt#e en%ianZng.va#ue*J8 e#se print&(g3ac,ine is Bi' )n%ianZng.va#ue*J2 V- int en%ian(* s,ort int wor% 84888J: c,ar [b0te (c,ar [* Kwor%J6 return (b0te\8] 9ITT9)P)"IA" BIXP)"IA"*J< V

1$. Swa+ &aria/,es with"ut usin' tem+"rar% &aria/,eH

a a b

b a + ba a + b

1*. Write a +r"'ram t" 'enerate the 7i/"na))i Series?

finc#u%edst%io!,

finc#u%edconio!,

main(*

int n.i.c.a8.bJ

print&()nter 5ibonacci series o& nt, term *J

scan&(Y%.Kn*J

print&(Y% Y% .a.b*J&or(i8Jid(n$-*Ji*

cabJ

abJ

bcJ

print&(Y% .c*J

V

'etc,(*J

VOutput

)nter 5ibonacci series o& nt, term <

8 2 - : 7

1-. Write a +r"'ram t" Bnd uniue num/ers in an arra%?

Answer:

&or (iJidarra0!#en't,Ji*

&oun%&a#seJ

&or (kiJkdarra0!#en't,Jk*

i& (arra0\i]arra0\k]* &oun%trueJ



V

i& (`&oun%* print#n(arra0\i]*J

V

1. Write a C +r"'ram t" +rint Eui,atera, Trian',e usin' num/ers?

8 @[ C pro'ram to print )1ui#atera# Trian'#e[@

82 finc#u%edst%io!,8- main(*8 8: int i.N.k.nJ868< print&(g)nter number o& rows o& t,e trian'#e Zng*J87 scan&(gY%g.Kn*J8F8 &or(iJidnJi* 2 &or(NJNdn$iJN*- print&(g g*J

: V6 &or(kJkd(2[i*$Jk*< 7 print&(gig*JF V28 print&(gZng*J2 V22 'etc,(*J

10. Write a +r"'ram !"r de,eti"n and inserti"n "! a n"de in sin',e ,in#ed ,ist?

finc#u%edst%io!,

finc#u%edst%#ib!,

t0pe%e& struct "o%e

int %ataJ

struct "o%e [ne4tJ

Vno%eJ

voi% insert(no%e [pointer. int %ata*

@[ Iterate t,rou', t,e #ist ti## we encounter t,e #ast no%e![@

w,i#e(pointer$ne4t`"U99*

pointer pointer $ ne4tJ

V@[ A##ocate memor0 &or t,e new no%e an% put %ata in it![@

pointer$ne4t (no%e [*ma##oc(si?eo&(no%e**J

pointer pointer$ne4tJ

pointer$%ata %ataJ

pointer$ne4t "U99J

V

int /n%(no%e [pointer. int ke0*



pointer pointer $ ne4tJ @@5irst no%e is %umm0 no%e!

@[ Iterate t,rou', t,e entire #inke% #ist an% searc, &or t,e ke0! [@

w,i#e(pointer`"U99*

i&(pointer$%ata ke0* @@ke0 is &oun%!

return J

V

pointer pointer $ ne4tJ@@Searc, in t,e ne4t no%e!

V

@[;e0 is not &oun% [@

return 8J

V

voi% %e#ete(no%e [pointer. int %ata*

@[ Xo to t,e no%e &or w,ic, t,e no%e ne4t to it ,as to be %e#ete% [@

w,i#e(pointer$ne4t`"U99 KK (pointer$ne4t*$%ata ` %ata*

pointer pointer $ ne4tJ

V

i&(pointer$ne4t"U99*

print&()#ement Y% is not present in t,e #istZn.%ata*J

returnJ

V

@[ "ow pointer points to a no%e an% t,e no%e ne4t to it ,as to be remove% [@

no%e [tempJ

temp pointer $ ne4tJ

@[temp points to t,e no%e w,ic, ,as to be remove%[@

pointer$ne4t temp$ne4tJ

@[We remove% t,e no%e w,ic, is ne4t to t,e pointer (w,ic, is a#so temp* [@

&ree(temp*J

@[ Beacuse we %e#ete% t,e no%e. we no #on'er re1uire t,e memor0 use% &or it !

&ree(* wi## %ea##ocate t,e memor0!

[@

returnJV

voi% print(no%e [pointer*

i&(pointer"U99*

returnJ

V



print&(Y% .pointer$%ata*J

print(pointer$ne4t*J

V

int main(*

@[ start a#wa0s points to t,e /rst no%e o& t,e #inke% #ist!temp is use% to point to t,e #ast no%e o& t,e #inke% #ist![@

no%e [start.[tempJ

start (no%e [*ma##oc(si?eo&(no%e**J

temp startJ

temp $ ne4t "U99J

@[ Here in t,is co%e. we take t,e /rst no%e as a %umm0 no%e!

T,e /rst no%e %oes not contain %ata. but it use% because to avoi% ,an%#in' specia# cases

in insert an% %e#ete &unctions!

[@

print&(! InsertZn*Jprint&(2! e#eteZn*J

print&(-! rintZn*J

print&(! 5in%Zn*J

w,i#e(*

int 1uer0J

scan&(Y%.K1uer0*J

i&(1uer0*

int %ataJ

scan&(Y%.K%ata*J

insert(start.%ata*J

V

e#se i&(1uer02*

int %ataJ

scan&(Y%.K%ata*J

%e#ete(start.%ata*J

V

e#se i&(1uer0-*

print&(T,e #ist is *J

print(start$ne4t*J

print&(Zn*J

V

e#se i&(1uer0*

int %ataJ



scan&(Y%.K%ata*J

int status /n%(start.%ata*J

i&(status*

print&()#ement 5oun%Zn*J

Ve#se

print&()#ement "ot 5oun%Zn*J V

V

VV

12. Can a &aria/,e /e /"th const and volatile? _es! T,e const mo%i/er means t,at

t,is co%e cannot c,an'e t,e va#ue o& t,e variab#e. but t,at %oes not mean t,at t,e va#ue

cannot be c,an'e% b0 means outsi%e t,is co%e! 5or instance. in t,e e4amp#e in 5AQ 7. t,e

timer structure was accesse% t,rou', a vo#ati#e const pointer! T,e &unction itse#& %i% not

c,an'e t,e va#ue o& t,e timer. so it was %ec#are% const! However. t,e va#ue was c,an'e% b0,ar%ware on t,e computer. so it was %ec#are% vo#ati#e! I& a variab#e is bot, const an% vo#ati#e.

t,e two mo%i/ers can appear in eit,er or%er!

13. what are C"nstant and V",ati,e Qua,iBers?

const

constis use% wit, a %atat0pe %ec#aration or %e/nition to speci&0 an unc,an'in' va#ue

)4amp#es const int five = 5;

const double pi = 3.141593;

constobNects ma0 not be c,an'e%

T,e &o##owin' are i##e'a# const int five = 5;

const double pi = 3.141593;

pi = 3.2;

five = 6;

vo#ati#e

vo#ati#especi/es a variab#e w,ose va#ue ma0 be c,an'e% b0 processes outsi%e t,e

current pro'ram

One e4amp#e o& a vo#ati#eobNect mi',t be a bu=er use% to e4c,an'e %ata wit, an

e4terna# %evice



int

check_iobuf(void)

{

volatile int iobuf;

int val;

while (iobuf == 0) {

}

val = iobuf;

iobuf = 0;

return(val);

}

i& iobu& ,a% not been %ec#are% vo#ati#e. t,e compi#er wou#% notice t,at not,in'

,appens insi%e t,e #oop an% t,us e#iminate t,e #oop

const an% vo#ati#e can be use% to'et,er

An input$on#0 bu=er &or an e4terna# %evice cou#% be %ec#are% as const

vo#ati#e (or vo#ati#e const. or%er is not important* to make sure t,e compi#er

knows t,at t,e variab#e s,ou#% not be c,an'e% (because it is input$on#0* an%

t,at its va#ue ma0 be a#tere% b0 processes ot,er t,an t,e current pro'ram

T,e ke0wor%s const an% vo#ati#e can be app#ie% to an0 %ec#aration. inc#u%in' t,ose o&

structures. unions. enumerate% t0pes or t0pe%e& names! App#0in' t,em to a %ec#aration is

ca##e% 1ua#i&0in' t,e %ec#aration^t,atLs w,0 const an% vo#ati#e are ca##e% t0pe 1ua#i/ers.

rat,er t,an t0pe speci/ers! Here are a &ew representative e4amp#esvolatile i;

volatile int j;

const long q;



const volatile unsigned long int rt_clk;

struct{

const long int li;

signed char sc;

}volatile vs;

onLt be put o=J some o& t,em are %e#iberate#0 comp#icate% w,at t,e0 mean wi## be

e4p#aine% #ater! Remember t,at t,e0 cou#% a#so be &urt,er comp#icate% b0 intro%ucin'

stora'e c#ass speci/cations as we##` In &act. t,e tru#0 spectacu#ar

extern const volatile unsigned long int rt_clk;

is a stron' possibi#it0 in some rea#$time operatin' s0stem kerne#s!

C"nst9etLs #ook at w,at is meant w,en const is use%! ItLs rea##0 1uite simp#e const means t,at

somet,in' is not mo%i/ab#e. so a %ata obNect t,at is %ec#are% wit, const as a part o& its t0pe

speci/cation must not be assi'ne% to in an0 wa0 %urin' t,e run o& a pro'ram! It is ver0 #ike#0

t,at t,e %e/nition o& t,e obNect wi## contain an initia#i?er (ot,erwise. since 0ou canLt assi'n to

it. ,ow wou#% it ever 'et a va#ue*. but t,is is not a#wa0s t,e case! 5or e4amp#e. i& 0ou were

accessin' a ,ar%ware port at a /4e% memor0 a%%ress an% promise% on#0 to rea% &rom it.

t,en it wou#% be %ec#are% to be const but not initia#i?e%!

Takin' t,e a%%ress o& a %ata obNect o& a t0pe w,ic, isnLt const an% puttin' it into a pointer to

t,e const$1ua#i/e% version o& t,e same t0pe is bot, sa&e an% e4p#icit#0 permitte%J 0ou wi## be

ab#e to use t,e pointer to inspect t,e obNect. but not mo%i&0 it! uttin' t,e a%%ress o& a const

t0pe into a pointer to t,e un1ua#i/e% t0pe is muc, more %an'erous an% conse1uent#0

pro,ibite% (a#t,ou', 0ou can 'et aroun% t,is b0 usin' a cast*! Here is an e4amp#e#include <stdio.h>

#include <stdlib.h>

main(){

int i;



const int ci = 123;

/* declare a pointer to a const.. */

const int *cpi;

/* ordinary pointer to a non-const */

int *ncpi;

cpi = &ci;

ncpi = &i;

/*

* this is allowed

*/

cpi = ncpi;

/*

* this needs a cast

* because it is usually a big mistake,

* see what it permits below.

*/



ncpi = (int *)cpi;

/*

* now to get undefined behaviour...

* modify a const through a pointer

*/

*ncpi = 0;

exit(EXIT_SUCCESS);

}

Example 8.3

As t,e e4amp#e s,ows. it is possib#e to take t,e a%%ress o& a constant obNect. 'enerate a

pointer to a non$constant. t,en use t,e new pointer! T,is is an error in 0our pro'ram an%

resu#ts in un%e/ne% be,aviour!

T,e main intention o& intro%ucin' const obNects was to a##ow t,em to be put into rea%$on#0store. an% to permit compi#ers to %o e4tra consistenc0 c,eckin' in a pro'ram! Un#ess 0ou

%e&eat t,e intent b0 %oin' nau',t0 t,in's wit, pointers. a compi#er is ab#e to c,eck

t,at const obNects are not mo%i/e% e4p#icit#0 b0 t,e user!

An interestin' e4tra &eature pops up now! W,at %oes t,is mean

char c;

char *const cp = &c;

ItLs simp#e rea##0J cp is a pointer to a c,ar. w,ic, is e4act#0 w,at it wou#% be i&t,e const werenLt t,ere! T,e const means t,at cp is not to be mo%i/e%. a#t,ou', w,atever it

points to can be^t,e pointer is constant. not t,e t,in' t,at it points to! T,e ot,er wa0 roun%

isconst char *cp;



w,ic, means t,at now cp is an or%inar0. mo%i/ab#e pointer. but t,e t,in' t,at it points to

must not be mo%i/e%! So. %epen%in' on w,at 0ou c,oose to %o. bot, t,e pointer an% t,e

t,in' it points to ma0 be mo%i/ab#e or notJ Nust c,oose t,e appropriate %ec#aration!

V",ati,eA&ter const. we treat vo#ati#e! T,e reason &or ,avin' t,is t0pe 1ua#i/er is main#0 to %o wit,

t,e prob#ems t,at are encountere% in rea#$time or embe%%e% s0stems pro'rammin' usin' C!

Ima'ine t,at 0ou are writin' co%e t,at contro#s a ,ar%ware %evice b0 p#acin' appropriate

va#ues in ,ar%ware re'isters at known abso#ute a%%resses!

9etLs ima'ine t,at t,e %evice ,as two re'isters. eac, 6 bits #on'. at ascen%in' memor0

a%%ressesJ t,e /rst one is t,e contro# an% status re'ister (csr* an% t,e secon% is a %ata port!

T,e tra%itiona# wa0 o& accessin' suc, a %evice is #ike t,is

/* Standard C example but without const or volatile */

/*

* Declare the device registers

* Whether to use int or short

* is implementation dependent

*/

struct devregs{

unsigned short csr; /* control & status */

unsigned short data; /* data port */

};

/* bit patterns in the csr */

#define ERROR 0x1



#define READY 0x2

#define RESET 0x4

/* absolute address of the device */

#define DEVADDR ((struct devregs *)0xffff0004)

/* number of such devices in system */

#define NDEVS 4

/*

* Busy-wait function to read a byte from device n.

* check range of device number.

* Wait until READY or ERROR

* if no error, read byte, return it

* otherwise reset error, return 0xffff

*/

unsigned int read_dev(unsigned devno){

struct devregs *dvp = DEVADDR + devno;

if(devno >= NDEVS)



return(0xffff);

while((dvp->csr & (READY | ERROR)) == 0)

; /* NULL - wait till done */

if(dvp->csr & ERROR){

dvp->csr = RESET;

return(0xffff);

}

return((dvp->data) & 0xff);

}

Example 8.4 T,e tec,ni1ue o& usin' a structure %ec#aration to %escribe t,e %evice re'ister #a0out an%

names is ver0 common practice! "otice t,at t,ere arenLt actua##0 an0 obNects o& t,at t0pe

%e/ne%. so t,e %ec#aration simp#0 in%icates t,e structure wit,out usin' up an0 store!

To access t,e %evice re'isters. an appropriate#0 cast constant is use% as i& it were pointin' to

suc, a structure. but o& course it points to memor0 a%%resses instea%!

However. a maNor prob#em wit, previous C compi#ers wou#% be in t,e w,i#e #oop w,ic, tests

t,e status re'ister an% waits &or t,e )RROR or R)A_ bit to come on! An0 se#&$respectin'

optimi?in' compi#er wou#% notice t,at t,e #oop tests t,e same memor0 a%%ress over an%over a'ain! It wou#% a#most certain#0 arran'e to re&erence memor0 once on#0. an% cop0 t,e

va#ue into a ,ar%ware re'ister. t,us spee%in' up t,e #oop! T,is is. o& course. e4act#0 w,at we

%onLt wantJ t,is is one o& t,e &ew p#aces w,ere we must #ook at t,e p#ace w,ere t,e pointer

points. ever0 time aroun% t,e #oop!

Because o& t,is prob#em. most C compi#ers ,ave been unab#e to make t,at sort o&

optimi?ation in t,e past! To remove t,e prob#em (an% ot,er simi#ar ones to %o wit, w,en to



write to w,ere a pointer points*. t,e ke0wor% vo#ati#e was intro%uce%! It te##s t,e compi#er

t,at t,e obNect is subNect to su%%en c,an'e &or reasons w,ic, cannot be pre%icte% &rom a

stu%0 o& t,e pro'ram itse#&. an% &orces ever0 re&erence to suc, an obNect to be a 'enuine

re&erence!

Here is ,ow 0ou wou#% rewrite t,e e4amp#e. makin' use o& const an% vo#ati#e to 'et w,at

0ou want!/*

* Declare the device registers

* Whether to use int or short

* is implementation dependent

*/

struct devregs{

unsigned short volatile csr;

unsigned short const volatile data;

};

/* bit patterns in the csr */

#define ERROR 0x1

#define READY 0x2

#define RESET 0x4

/* absolute address of the device */

#define DEVADDR ((struct devregs *)0xffff0004)



/* number of such devices in system */

#define NDEVS 4

/*

* Busy-wait function to read a byte from device n.

* check range of device number.

* Wait until READY or ERROR

* if no error, read byte, return it

* otherwise reset error, return 0xffff

*/

unsigned int read_dev(unsigned devno){

struct devregs * const dvp = DEVADDR + devno;

if(devno >= NDEVS)

return(0xffff);

while((dvp->csr & (READY | ERROR)) == 0)

; /* NULL - wait till done */



if(dvp->csr & ERROR){

dvp->csr = RESET;

return(0xffff);

}

return((dvp->data) & 0xff);

}

Example 8.5 T,e ru#es about mi4in' vo#ati#e an% re'u#ar t0pes resemb#e t,ose &or const! A pointer to

a vo#ati#e obNect can be assi'ne% t,e a%%ress o& a re'u#ar obNect wit, sa&et0. but it is

%an'erous (an% nee%s a cast* to take t,e a%%ress o& a vo#ati#e obNect an% put it into a pointer

to a re'u#ar obNect! Usin' suc, a %erive% pointer resu#ts in un%e/ne% be,aviour!

I& an arra0. union or structure is %ec#are% wit, const or vo#ati#e attributes. t,en a## o& t,e

members take on t,at attribute too! T,is makes sense w,en 0ou t,ink about it^,ow cou#% a

member o& a const structure be mo%i/ab#e

T,at means t,at an a#ternative rewrite o& t,e #ast e4amp#e wou#% be possib#e! Instea% o&

%ec#arin' t,e %evice re'isters to be vo#ati#e in t,e structure. t,e pointer cou#% ,ave been

%ec#are% to point to a vo#ati#e structure instea%. #ike t,is

struct devregs{

unsigned short csr; /* control & status */

unsigned short data; /* data port */

};

volatile struct devregs *const dvp=DEVADDR+devno;

Since %vp points to a vo#ati#e obNect. it not permitte% to optimi?e re&erences t,rou', t,e

pointer! Our &ee#in' is t,at. a#t,ou', t,is wou#% work. it is ba% st0#e! T,e vo#ati#e %ec#aration

be#on's in t,e structure it is t,e %evice re'isters w,ic, are vo#ati#e an% t,at is w,ere t,e

in&ormation s,ou#% be keptJ it rein&orces t,e &act &or a ,uman rea%er!

So. &or an0 obNect #ike#0 to be subNect to mo%i/cation eit,er b0 ,ar%ware or as0nc,ronous

interrupt service routines. t,e vo#ati#e t0pe 1ua#i/er is important!



"ow. Nust w,en 0ou t,ou',t t,at 0ou un%erstoo% a## t,at. ,ere comes t,e /na# twist! A

%ec#aration #ike t,is

volatile struct devregs{

/* stuff */

}v_decl;

%ec#ares t,e t0pe struct %evre's an% a#so a vo#ati#e$1ua#i/e% obNect o& t,at t0pe.

ca##e% vP%ec#! A #ater %ec#aration #ike t,isstruct devregs nv_decl;

%ec#ares nvP%ec# w,ic, is not 1ua#i/e% wit, vo#ati#e` T,e 1ua#i/cation is not part o& t,e t0pe

o& struct %evre's but app#ies on#0 to t,e %ec#aration o& vP%ec#! 9ook at it t,is wa0 roun%.

w,ic, per,aps makes t,e situation more c#ear (t,e two %ec#arations are t,e same in t,eir

e=ect*struct devregs{

/* stuff */

}volatile v_decl;

I& 0ou %o want to 'et a s,ort,an% wa0 o& attac,in' a 1ua#i/er to anot,er t0pe. 0ou can

use t0pe%e& to %o itstruct x{

int a;

};

typedef const struct x csx;

csx const_sx;

struct x non_const_sx = {1};



const_sx = non_const_sx; /* error - attempt to modify a const */

(.What are the di5eren)es /etween a uni"n and a stru)ture in C?

A union is a wa0 o& provi%in' an a#ternate wa0 o& %escribin' t,e same memor0 area! In t,is

wa0. 0ou cou#% ,ave a struct t,at contains a union. so t,at t,e static. or simi#ar portion o&

t,e %ata is %escribe% /rst. an% t,e portion t,at c,an'es is %escribe% b0 t,e union! T,e i%ea

o& a union cou#% be ,an%#e% in a %i=erent wa0 b0 ,avin' 2 %i=erent structs %e/ne%. an%

makin' a pointer to eac, kin% o& struct! T,e pointer to struct a cou#% be assi'ne% to t,e

va#ue o& a bu=er. an% t,e pointer to struct b cou#% be assi'ne% to t,e same bu=er. but

now a$some /e#% an% b$some ot,er/e#% are bot, #ocate% in t,e same bu=er! T,at is t,e

i%ea be,in% a union! It 'ives %i=erent wa0s to break %own t,e same bu=er area!

T,e %i=erence between structure an% union are ! union a##ocates t,e memor0 e1ua# to t,e

ma4imum memor0 re1uire% b0 t,e member o& t,e union but structure a##ocates t,e memor0

e1ua# to t,e tota# memor0 re1uire% b0 t,e members! 2! In union. one b#ock is use% b0 a## t,e

member o& t,e union but in case o& structure. eac, member ,ave t,eir own memor0 space

8i5eren)e etween Stu)ture and Uni"n :

Stru)ture Uni"ni. A))ess Mem/ersWe can access a## t,e members o&structure at an0time!

On#0 one member o& union can be accesse% atan0time!

ii. Mem"r% A,,")ati"n

3emor0 is a##ocate% &or a## variab#es!A##ocates memor0 &or variab#e w,ic, variab#ere1uire more memor0!

iii. Initia,i=ati"nA## members o& structure can beinitia#i?e%

On#0 t,e /rst member o& a union can beinitia#i?e%!

i&. e%w"rdstructL ke0wor% is use% to %ec#arestructure! unionL ke0wor% is use% to %ec#are union!&. S%nta4struct struct_name

{

structure element 1;

structure element 2;

----------

----------

structure element n;

union union_name

{

union element 1;

union element 2;

----------

----------

union element n;



}struct_var_nm; }union_var_nm;

&i. E4am+,estruct item_mst

{

int rno;

char nm[50];

}it;

union item_mst

{

int rno;

char nm[50];

}it;

8i5eren)e in their Usa'e:

W,i#e structure enab#es us treat a number o& %i=erent variab#es store% at %i=erent inmemor0 . a union enab#es us to treat t,e same space in memor0 as a number o& %i=erent

variab#es! T,at is a Union o=ers a wa0 &or a section o& memor0 to be treate% as a variab#e o&

one t0pe on one occasion an% as a %i=erent variab#e o& a %i=erent t0pe on anot,er occasion!

T,ere is &re1uent re1uirement w,i#e interactin' wit, ,ar%ware to access access a b0te or

'roup o& b0tes simu#taneous#0 an% sometimes eac, b0te in%ivi%ua##0! Usua##0 union is t,e

answer!

i=erence Wit, e4amp#e

9ets sa0 a structure containin' an int.c,ar an% >oat is create% an% a union containin' int

c,ar >oat are %ec#are%!

struct TT int aJ >oat bJ c,ar cJ V Union UU int aJ >oat bJ c,ar cJ V

si?eo& TT(struct* wou#% be F b0tes (compi#er %epen%ent$i& int.>oat. c,ar are taken as ..*

si?eo& UU(Union* wou#% be b0tes as suppose% &rom above!I& a variab#e in %oub#e e4ists in

union t,en t,e si?e o& union an% struct wou#% be 7 b0tes an% cumu#ative si?e o& a## variab#es

in struct!

8etai,ed E4am+,e:struct &oo

c,ar cJ#on' #J

c,ar [pJ

VJ

union bar



c,ar cJ

#on' #J

c,ar [pJ

VJ

A struct &oo contains a## o& t,e e#ements c. #. an% p! )ac, e#ement is separate an% %istinct!

A union bar contains on#0 one o& t,e e#ements c. #. an% p at an0 'iven time! )ac, e#ement is

store% in t,e same memor0 #ocation (we##. t,e0 a##

start at t,e same memor0 #ocation*. an% 0ou can on#0 re&er to t,e e#ement w,ic, was #ast

store%! (ie a&ter barptr$c 2J 0ou cannot re&erence

an0 o& t,e ot,er e#ements. suc, as barptr$p wit,out invokin' un%e/ne% be,avior!*

Tr0 t,e &o##owin' pro'ram! (_es. I know it invokes t,e above$mentione% un%e/ne%

be,avior. but most #ike#0 wi## 'ive some sort o& output on most computers!*

finc#u%e

struct &oo

c,ar cJ

#on' #J

c,ar [pJ

VJ

union bar

c,ar cJ

#on' #J

c,ar [pJ

VJ

int main(int ar'c.c,ar [ar'v\]*

struct &oo m0&ooJ

union bar m0barJ

m0&oo!c J

m0&oo!# 29J

m0&oo!p T,is is m0&ooJ



m0bar!c J

m0bar!# 29J

m0bar!p T,is is m0barJ

print&(m0&oo Y% Y#% YsZn.m0&oo!c.m0&oo!#.m0&oo!p*J

print&(m0bar Y% Y#% YsZn.m0bar!c.m0bar!#.m0bar!p*J

return 8J

V

On m0 s0stem. I 'et

m0&oo 2 T,is is m0&oom0bar 88 F<<6 T,is is m0bar

cre%it to ori'ina# aut,or!

Stru)ture: Structure is a combination e#ements. w,ic, can be pre%e/ne% %ata t0pes or

ot,er structure! T,e #en't,@si?e o& t,e structure is t,e sum o& t,e #en't, o& its e#ements!

In C, structures cannot contain functions. in C++ it can.

Uni"n Union is a combination e#ements. w,ic, can be pre%e/ne% %ata t0pes or ot,er

union ! But. t,e si?e@#en't, o& union is t,e ma4imum o& interna# e#ements!

t,e sizeof() operator returns t,e si?e s#i',t#0 more t,an ca#cu#ate% si?e %ue to pa%%in'.

w,ic, a'ain %epen%s on OS

Answer Union a##ocates t,e memor0 e1ua# to t,e ma4imum memor0 re1uire% b0 t,e

member o& t,e union but structure a##ocates t,e memor0 e1ua# to t,e tota# memor0 re1uire%

b0 t,e members! In union.one b#ock is use% b0 a## t,e member o& t,e union but in case o&

structure. eac, member ,ave t,eir own memor0 space!

1. What is meant /% stru)ture +addin'?

Answer: compi#ers pa% structures to optimi?e %ata trans&ers! T,is is an ,ar%ware

arc,itecture issue! 3ost mo%ern CUs per&orm best w,en &un%amenta# t0pes. #ike intL or

>oatL. are a#i'ne% on memor0 boun%aries o& a particu#ar si?e (e'! o&ten a b0te wor% on

-2bit arc,s*! 3an0 arc,itectures %onLt a##ow misa#i'ne% access or i& t,e0 %o inoccur a

per&ormance pena#it0! W,en a compi#er processes a structure %ec#aration it wi## a%% e4trab0tes between /e#%s to meet a#i'nment nee%s!

3ost processors re1uire speci/c memor0 a#i'nment on variab#es certain t0pes! "orma##0 t,e

minimum a#i'nment is t,e si?e o& t,e basic t0pe in 1uestion. &or instance t,is is common

c,ar variab#es can be b0te a#i'ne% an% appear at an0 b0te boun%ar0



s,ort (2 b0te* variab#es must be 2 b0te a#i'ne%. t,e0 can appear at an0 even b0te boun%ar0!

T,is means t,at 84888:6< is not a va#i% #ocation &or a s,ort variab#e but 84888:66 is!

#on' ( b0te* variab#es must be b0te a#i'ne%. t,e0 can on#0 appear at b0te boun%aries t,at

are a mu#tip#e o& b0tes! T,is means t,at 84888:66 is not a va#i% #ocation &or a #on'

variab#e but 84888:67 is!

Structure pa%%in' occurs because t,e members o& t,e structure must appear at t,e correct

b0te boun%ar0. to ac,ieve t,is t,e compi#er puts in pa%%in' b0tes (or bits i& bit /e#%s are in

use* so t,at t,e structure members appear in t,e correct #ocation! A%%itiona##0 t,e si?e o&

t,e structure must be suc, t,at in an arra0 o& t,e structures a## t,e structures are correct#0

a#i'ne% in memor0 so t,ere ma0 be pa%%in' b0tes at t,e en% o& t,e structure too

struct e4amp#e

c,ar cJ

s,ort sJ

c,ar c2J

#on' #J

c,ar c-J

V

In t,is structure. assumin' t,e a#i'nment sc,eme I ,ave previous#0 state% t,en

c can appear at an0 b0te boun%ar0. ,owever s must appear at a 2 b0te boun%ar0 so t,ere

is a pa%%in' b0te between c an% s!

c2 can t,en appear in t,e avai#ab#e memor0 #ocation. ,owever # must be at a b0te

boun%ar0 so t,ere are - pa%%in' b0tes between c2 an% #

c- t,en appear in t,e avai#ab#e memor0 #ocation. ,owever because t,e structure contains a

#on' member t,e structure must be b0te a#i'ne% an% must be a mu#tip#e o& b0tes in si?e!

T,ere&ore t,ere are - pa%%in' b0tes at t,e en% o& t,e structure! It wou#% appear in memor0

in t,is or%er

cpa%%in' b0te

s b0te

s b0te 2

c2

pa%%in' b0te

pa%%in' b0te

pa%%in' b0te



# b0te

# b0te 2

# b0te -

# b0te

c-

pa%%in' b0tepa%%in' b0te

pa%%in' b0te

T,e structure wou#% be 6 b0tes #on'!

re$written #ike t,is

struct e4amp#e

#on' #J

s,ort sJ

c,ar cJ

c,ar c2J

c,ar c-J

V

T,en # appears at t,e correct b0te a#i'nment. s wi## be correct#0 a#i'ne% so no nee% &or

pa%%in' between # an% s! c. c2. c- can appear at an0 #ocation! T,e structure must be a

mu#tip#e o& b0tes in si?e since it contains a #on' so - pa%%in' b0tes appear a&ter c-

It appears in memor0 in t,e or%er

# b0te

# b0te 2

# b0te -

# b0te

s b0te

s b0te 2

c

c2

c-

pa%%in' b0tepa%%in' b0te

pa%%in' b0te

an% is on#0 2 b0tes #on'!



I s,ou#% point out t,at structure packin' is p#at&orm an% compi#er (an% in some cases

compi#er switc,* %epen%ent!

3emor0 oo#s are Nust a section o& memor0 reserve% &or a##ocatin' temporari#0 to ot,er parts

o& t,e app#ication

A memor0 #eak occurs w,en 0ou a##ocate some memor0 &rom t,e ,eap (or a poo#* an% t,en

%e#ete a## re&erences to t,at memor0 wit,out returnin' it to t,e poo# it was a##ocate% &rom!

@r"'ram:

struct 30StructA

c,ar aJ

c,ar bJ

int cJ

VJ

struct 30StructB

c,ar aJ

int cJ

c,ar bJ

VJ

int main(voi%*

int si?eA si?eo&(struct 30StructA*J

int si?eB si?eo&(struct 30StructB*J

print&(A Y%Zn. si?eA*J

print&(B Y%Zn. si?eB*J

return 8J

V

. What is the di5eren)e /etween ma)r" and )"nstant &aria/,es in C?

3acros are rep#ace% b0 preprocessor. but in constant %ata t0pe wi## be c,ecke% b0 compi#er!

3acros are rep#ace% wit,out c,eckin' t,e va#ues sometimes t,e pro'rammer want to

c,an'e va#ues on#0 in a sin'#e &unction at t,at pre&er to use constant t,an a macro!

T,e /rst tec,ni1ue comes &rom t,e C pro'rammin' #an'ua'e! Constants ma0 be %e/ne%

usin' t,e preprocessor %irective. f%e/ne T,e preprocessor is a pro'ram t,at mo%i/es 0our

source /#e prior to compi#ation! Common preprocessor %irectives are finc#u%e. w,ic, is use%

to

inc#u%e a%%itiona# co%e into 0our source /#e. f%e/ne. w,ic, is use% to %e/ne a constant an%

fi&@fen%i&. w,ic, can be use% to con%itiona##0 %etermine w,ic, parts o& 0our co%e wi## be

compi#e%! T,e f%e/ne %irective is use% as &o##ows!



f%e/ne pi -!:f%e/ne i%Pno 2-:

W,erever t,e constant appears in 0our source /#e. t,e preprocessor rep#aces it b0 its va#ue!

So. &or instance. ever0 pi in 0our source co%e wi## be rep#ace b0 -!:! T,e compi#er wi##

on#0 see t,e va#ue -!: in 0our co%e. not pi! T,e prob#em wit, t,is tec,ni1ue is t,at t,e

rep#acement is %one #e4ica##0. wit,out an0 t0pe c,eckin'. wit,out an0 boun% c,eckin' an%

wit,out an0 scope c,eckin'! )ver0 pi is Nust rep#ace% b0 its va#ue! T,e tec,ni1ue isout%ate%. e4ists to support #e'ac0 co%e an% s,ou#% be avoi%e%!

C"nst

T,e secon% tec,ni1ue is to use t,e ke0wor% const w,en %e/nin' a variab#e! W,en use% t,e

compi#er wi## catc, attempts to mo%i&0 variab#es t,at ,ave been %ec#are% const!

const >oat pi -!:Jconst int i%Pno 2-:J

T,ere are two main a%vanta'es over t,e /rst tec,ni1ue!

5irst. t,e t0pe o& t,e constant is %e/ne%! pi is >oat! i%Pno is int! T,is a##ows some t0pe

c,eckin' b0 t,e compi#er!Knbs pJ

Secon%. t,ese constants are variab#es wit, a %e/nite scope! T,e scope o& a variab#e re#atesto parts o& 0our pro'ram in w,ic, it is %e/ne%! Some variab#es ma0 e4ist on#0 in certain

&unctions or in certain b#ocks o& co%e!

)4 _ou ma0 want to use i%Pno in one &unction

an% a comp#ete#0 unre#ate% i%Pno in 0our main pro'ram!

$. What is di5eren)e /etween re>entrant !un)ti"n and re)ursi&e !un)ti"n in C?

Answer: Re entrant &unction is a &unction w,ic, 'uarantee% t,at w,ic, can be work we##

un%er mu#ti t,rea%e% environment! mean w,i#e &unction is access b0 one t,rea%. anot,er

t,rea% can ca## it mean t,ere is separate e4ecution stack an% ,an%#in' &or eac,! So &unctions,ou#% not contain an0 static or s,are% variab#e w,ic, can ,arm or %isturb t,e e4ecution!

3ean &unction w,ic, can be ca##e% b0 t,rea%. w,i#e runnin' &rom anot,er t,rea% sa&e#0 an%

proper#0

E4am+,e:int t;

void swap(int *x, int *y)

{

int s;



s = t; // save global variable

t = *x;

*x = *y;

// hardware interrupt might invoke isr() here!

*y = t;

t = s; // restore global variable

}

void isr()

{

int x = 1, y = 2;

swap(&x, &y);

}

Re)ursi&e !un)ti"n E4am+,e:

voi% %o## ( int si?e *

i& ( si?e 8 * @@ "o %o## can be sma##er t,an atom (8h8* so %oesnLt ca## itse#&

returnJ @@ Return %oes not ,ave to return somet,in'. it can be use%

@@ to e4it a &unction

%o## ( si?e + *J @@ ecrements t,e si?e variab#e so t,e ne4t %o## wi## be sma##er!

V

int main(*

%o## ( 8 *J @@Starts o= wit, a #ar'e %o## (itLs a #o'arit,mic sca#e*

*. What is V>M"de, ? What are the /eneBts?

T,e V>m"de, represents a so&tware %eve#opment process (a#so app#icab#e to ,ar%ware

%eve#opment* w,ic, ma0 be consi%ere% an e4tension o& t,e water&a## mo%e#! Instea% o&

movin' %own in a #inear wa0. t,e process steps are bent upwar%s a&ter t,e co%in' p,ase. to



&orm t,e t0pica# M s,ape! T,e M$3o%e# %emonstrates t,e re#ations,ips between eac, p,ase

o& t,e %eve#opment #i&e c0c#e an% its associate% p,ase o& testin'!

T,e M mo%e# ,as a number o& bene/ts

! S0stems %eve#opment proNects usua##0 ,ave a test approac,. or test strate'0 %ocument.

w,ic, %e/nes ,ow testin' wi## be per&orme% t,rou',out t,e #i&ec0c#e o& t,e proNect! T,e M

mo%e# provi%es a consistent basis an% stan%ar% &or part o& t,at strate'0!

2! T,e M mo%e# e4p#icit#0 su''ests t,at testin' (1ua#it0 assurance* s,ou#% be consi%ere%

ear#0 on in t,e #i&e o& a proNect! Testin' an% /4in' can be %one at an0 sta'e in t,e #i&ec0c#e!

However. t,e cost o& /n%in' an% /4in' &au#ts increases %ramatica##0 as %eve#opment

pro'resses! )vi%ence su''ests t,at i& a &au#t uncovere% %urin' %esi'n costs !8 monetar0

unit to correct. t,en t,e same &au#t uncovere% Nust be&ore testin' wi## cost 6!: units. %urin'

testin' : units. an% a&ter re#ease between 68 an% 88 units! T,e nee% to /n% &au#ts as soon

as possib#e rein&orces t,e nee% &or t,e 1ua#it0 assurance o& %ocuments suc, as t,e

re1uirements speci/cation an% t,e &unctiona# speci/cation! T,is is per&orme% usin' statictestin' tec,ni1ues suc, as inspections an% wa#kt,rou',s!

-! It intro%uces t,e i%ea o& speci&0in' test re1uirements an% e4pecte% outcomes prior to

per&ormin' t,e actua# tests! 5or e4amp#e. t,e acceptance tests are per&orme% a'ainst a

speci/cation o& re1uirements. rat,er t,an a'ainst some criteria %reame% up w,en t,e

acceptance sta'e ,as been reac,e%

! T,e M mo%e# provi%es a &ocus &or %e/nin' t,e testin' t,at must take p#ace wit,in eac,

sta'e! T,e %e/nition o& testin' is assiste% b0 t,e i%ea o& entr0 an% e4it criteria! Hence. t,e

mo%e# can be use% to %e/ne t,e state a %e#iverab#e must be in be&ore it can enter an% #eaveeac, sta'e! T,e e4it criteria o& one sta'e are usua##0 t,e entr0 criteria o& t,e ne4t! In man0

or'ani?ations. t,ere is concern about t,e 1ua#it0 o& t,e pro'ram co%e re#ease% b0 in%ivi%ua#

pro'rammers! Some pro'rammers re#ease co%e t,at appears to be &au#t$&ree. w,i#e ot,ers

re#ease co%e t,at sti## ,as man0 &au#ts in it! T,e prob#em o& pro'rammers re#easin' co%e wit,

%i=erent #eve#s o& robustness wou#% be a%%resse% in t,e e4it criteria o& unit %esi'n an% unit

testin'! Unit %esi'n wou#% re1uire pro'rammers to speci&0 t,eir inten%e% test cases be&ore

t,e0 wrote an0 pro'ram co%e! Co%in' cou#% not be'in unti# t,ese test cases ,a% been

a'ree% wit, an appropriate mana'er! Secon%. t,e test cases wou#% ,ave to be con%ucte%

success&u##0 be&ore t,e pro'ram cou#% #eave t,e unit test sta'e an% be re#ease% to

inte'ration testin'!

:! 5ina##0. t,e M mo%e# provi%es a basis &or %e/nin' w,o is responsib#e &or per&ormin' t,e

testin' at eac, sta'e! Here are some t0pica# responsibi#ities

acceptance testin' per&orme% b0 users

s0stem testin' per&orme% b0 s0stem testers



inte'ration testin' per&orme% b0 pro'ram team #ea%ers

unit testin' per&orme% b0 pro'rammers!

T,e M mo%e# is t,ere&ore an e4ce##ent basis &or t,e partitionin' o& testin'. ,i',#i',tin' t,e

&act t,at a## t,e participants in t,e %eve#opment o& a s0stem ,ave a responsibi#it0 &or 1ua#it0

assurance an% testin'!

-. What is meant /% ,a)# /"4 testin' and white /"4 testin'?

White>/"4 testin' (a#so known as ),ear /"4 testin'. ',ass /"4 testin'. trans+arent

/"4 testin'. an% stru)tura, testin'* is a met,o% o& testin' so&tware t,at tests interna#

structures or workin's o& an app#ication. as oppose% to its &unctiona#it0 (i!e! b#ack$bo4

testin'*! In w,ite$bo4 testin' an interna# perspective o& t,e s0stem. as we## as pro'rammin'

ski##s. are use% to %esi'n test cases! T,e tester c,ooses inputs to e4ercise pat,s t,rou', t,e

co%e an% %etermine t,e appropriate outputs! T,is is ana#o'ous to testin' no%es in a circuit.

e!'! in$circuit testin' (ICT*!

W,i#e w,ite$bo4 testin' can be app#ie% at t,e unit. inte'ration an% s0stem #eve#s o& t,e

so&tware testin' process. it is usua##0 %one at t,e unit #eve#! It can test pat,s wit,in a unit.pat,s between units %urin' inte'ration. an% between subs0stems %urin' a s0stem+#eve#

test! T,ou', t,is met,o% o& test %esi'n can uncover man0 errors or prob#ems. it mi',t not

%etect unimp#emente% parts o& t,e speci/cation or missin' re1uirement!

,a)#>/"4 testin' is a met,o% o& so&tware testin' t,at tests t,e &unctiona#it0 o& an

app#ication as oppose% to its interna# structures or workin's (see w,ite$bo4 testin'*! T,is

met,o% o& test can be app#ie% to a## #eve#s o& so&tware testin' unit. inte'ration. s0stem an%

acceptance! It t0pica##0 comprises most i& not a## testin' at ,i',er #eve#s. but can a#so

%ominate unit testin' as we##!

White "4 Testin': 3eans testin' t,e app#ication wit, co%in' @pro'rammin' know#e%'e!

T,at means t,e tester ,as to correct t,e co%e a#so!

,a)# /"4 testin': Testin' t,e app#ication wit,out co%in' @pro'rammin' know#e%'e t,at

means t,e tester %oesnLt re1uire co%in' know#e%'e! ust ,e e4amines t,e app#ication

e4terna# &unctiona# be,aviour an% XUI &eatures!

S,.N" ,a)# "4 White "4

5ocuses on t,e &unctiona#it0 o& t,es0stem

5ocuses on t,e structure (ro'ram* o&t,e s0stem

2 Tec,ni1ues use% are

)1uiva#ence partitionin' Boun%ar0$va#ue ana#0sis )rror 'uessin' Race con%itions Cause$e=ect 'rap,in' S0nta4 testin' State transition testin' Xrap, matri4

Tec,ni1ues use% are

Basis at, Testin' 5#ow Xrap, "otation Contro# Structure Testin'

! Con%ition Testin'

2! ata 5#ow testin'

9oop Testin'



! Simp#e 9oops

2! "este% 9oops

-! Concatenate% 9oops

! Unstructure% 9oops

- Tester can be non tec,nica# Tester s,ou#% be tec,nica#

He#ps to i%enti&0 t,e va'ueness an%contra%iction in &unctiona#speci/cations

He#ps to i%enti&0 t,e #o'ica# an% co%in'issues!

. What are the t%+es "! testin's?

unit testin'

Component testin'

Inte'ration testin'

S0stem testin'

0. The 8i5eren)e /etween it Rate and aud Rate?

T,e %i=erence between Bit an% Bau% rate is comp#icate% an% intertwinin'! Bot, are

%epen%ent an% inter$re#ate%! But t,e simp#est e4p#anation is t,at a Bit Rate is ,ow man0

%ata bits are transmitte% per secon%! A bau% Rate is t,e number o& times per secon% a

si'na# in a communications c,anne# c,an'es!

Bit rates measure t,e number o& %ata bits (t,at is 8s an% s* transmitte% in one secon% in a

communication c,anne#! A /'ure o& 288 bits per secon% means 288 ?eros or ones can be

transmitte% in one secon%. ,ence t,e abbreviation bps! In%ivi%ua# c,aracters (&or e4amp#e

#etters or numbers* t,at are a#so re&erre% to as b0tes are compose% o& severa# bits!

A bau% rate is t,e number o& times a si'na# in a communications c,anne# c,an'es state or

varies! 5or e4amp#e. a 288 bau% rate means t,at t,e c,anne# can c,an'e states up to 288

times per secon%! T,e term c,an'e state means t,at it can c,an'e &rom 8 to or &rom

to 8 up to (in t,is case. 288* times per secon%! It a#so re&ers to t,e actua# state o& t,e

connection. suc, as vo#ta'e. &re1uenc0. or p,ase #eve#*!

T,e main %i=erence between t,e two is t,at one c,an'e o& state can transmit one bit. or

s#i',t#0 more or #ess t,an one bit. t,at %epen%s on t,e mo%u#ation tec,ni1ue use%! So t,e bit

rate (bps* an% bau% rate (bau% per secon%* ,ave t,is connection

bps bau% per secon% 4 t,e number o& bit per bau%



T,e mo%u#ation tec,ni1ue %etermines t,e number o& bit per bau%! Here are two e4amp#es

W,en 5S; (5re1uenc0 S,i&t ;e0in'. a transmission tec,ni1ue* is use%. eac, bau% transmits

one bit! On#0 one c,an'e in state is re1uire% to sen% a bit! T,us. t,e mo%emLs bps rate is

e1ua# to t,e bau% rate! W,en a bau% rate o& 288 is use%. a mo%u#ation tec,ni1ue ca##e%

p,ase mo%u#ation t,at transmits &our bits per bau% is use%! So

288 bau% 4 bits per bau% F688 bps

Suc, mo%ems are capab#e o& F688 bps operation!

$;8i5eren)e /etween Jash and EE+r"m

! Simi#arities

Bot, >as, an% ))RO3 are %i'ita# stora'e met,o%s use% b0 computers an% ot,er

%evices! Bot, are non$vo#ati#e RO3 tec,no#o'ies to w,ic, 0ou can write an% &rom

w,ic, 0ou can erase mu#tip#e times!

i=erences

T,e primar0 %i=erence between >as, an% ))RO3 is t,e wa0 t,e0 erase %ata! W,i#e

))RO3 %estro0s t,e in%ivi%ua# b0tes o& memor0 use% to store %ata. >as, %evices

can on#0 erase memor0 in #ar'er b#ocks! T,is makes >as, %evices &aster at rewritin'.

as t,e0 can a=ect #ar'e portions o& memor0 at once! Since a rewrite ma0 a=ect

unuse% b#ocks o& %ata. it a#so a%%s unnecessari#0 to usa'e o& t,e %evice. s,ortenin'

its #i&espan in comparison wit, ))RO3!

Usa'e

5#as, stora'e is common#0 use% in USB memor0 %rives an% so#i% state ,ar% %rives!

))RO3 is use% in a variet0 o& %evices. &rom pro'rammab#e MCRs to C p#a0ers!

2. Can stru)tures /e +assed t" the !un)ti"ns /% &a,ue?

Ans 0es structures can be passe% b0 va#ue! But unnecessar0 memor0 wasta'e!

3. Wh% )ann"t arra%s /e +assed /% &a,ues t" !un)ti"ns?

Ans W,en a arra0 is passe% to a &unction. t,e arra0 is interna##0 c,an'e% to a pointer! An%

pointers are a#wa0s passe% b0 re&erence!

$(. What is meant /% stati) !un)ti"ns?

Ans: stati) !un)ti"ns are &unctions t,at are on#0 visib#e to ot,er &unctions in t,e same /#e

E4am+,e:

main.) #include <STDIO.H>

main()

{

Func1();

Func2();

}



!un)s.) /*************************************

*

* Function declarations (prototypes).

*

*************************************/

/* Func1 is only visable to functions in this file. */

static void Func1(void);

/* Func2 is visable to all functions. */

void Func2(void);

/*************************************

*

* Function definitions

*

*************************************/

void Func1(void)

{

puts("Func1 called");

}

/*************************************/ void Func2(void)

{

puts("Func2 called");

}

$1. 8i5eren)e /etween de),arati"nD deBniti"n K initia,i=ati"n?

Ans: A %ec#aration intro%uces a name + an i%enti/er + to t,e compi#er! It te##s t,e compi#erT,is &unction or t,is variab#e e4ists somew,ere. an% ,ere is w,at it s,ou#% #ook #ike!

A %e/nition. on t,e ot,er ,an%. sa0s 3ake t,is variab#e ,ere or 3ake t,is &unction ,ere!

It a##ocates stora'e &or t,e name! T,is meanin' works w,et,er

0ouLre ta#kin' about a variab#e or a &unctionJ in eit,er case. at t,e point o& %e/nition t,e

compi#er a##ocates stora'e!



e4tern const int 4 J @[ Initia#i?ation [@

T,is initia#i?ation estab#is,es t,is as a %e/nition. not a %ec#aration!

e4tern const int 4J @[ ec#aration [@

T,is %ec#aration in C means t,at t,e %e/nition e4ists e#sew,ere!

$. What is the di5eren)e /etween +ass /% &a,ue /% re!eren)e in ) and +ass /%

re!eren)e in )?

@ass % Re!eren)e :

In Pass b reference a!!ress of t"e #ariable is passe! to a function.

$"ate#er c"an%es ma!e to t"e formal parameter &ill a'ect to t"e actual

parameters

ame memor location is use! for bot" #ariables.(*ormal an! ctual)

it is useful &"en ou re-uire! to return more t"en #alues

@ass % Va,ue:

In t"is met"o! #alue of t"e #ariable is passe!. C"an%es ma!e to formal &illnot a'ect t"e actual parameters.

/i'erent memor locations &ill be create! for bot" #ariables.

0ere t"ere &ill be temporar #ariable create! in t"e function stac1 &"ic"

!oes not a'ect t"e ori%inal #ariable.

$$. What is the di5eren)e /etween Jash mem"r%D E@ROM and EE@ROM?

))RO3 is an o#%er. more re#iab#e tec,no#o'0! It is somew,at s#ower t,an 5#as,! 5#as, an%

))RO3 are ver0 simi#ar. but t,ere is a subt#e %i=erence! 5#as, an% ))RO3 bot, use

1uantum ce##s to trap e#ectons! )ac, ce## represents one bit o& %ata! T,e presence + or

absence + o& e#ectons in a ce## in%icates w,et,er t,e bit is a or 8!T,e ce##s ,ave a /nite #i&e

+ ever0 time a ce## is erase%. it wears out a #itt#e bit! In ))RO3. ce##s are erase% one$b0$one! T,e on#0 ce##s erase% are t,ose w,ic, are but nee% to be ?ero! (Writin' a to a ce## t,atLs 8

causes ver0 #itt#e wear. IIRC*In 5#as,. a #ar'e b#ock is erase% a## at once! In some %evices. t,is

b#ock is t,e entire %evice! So in >as,. ce##s are erase% w,et,er t,e0 nee% it or not! T,is

cuts %own on t,e #i&espan o& t,e %evice. but is muc,. muc, &aster t,an t,e ))RO3 met,o%

o& 'oin' ce##$b0$ce##!

Erasure meth"d: Bot, 5#as, an% ))RO3 erase ce##s b0 means o& an e#ectric /e#%! I t,ink it

is ,i',$&re1uenc0 an% pops t,e e#ectrons out o& t,e Ot,er simi#ar %evices are )RO3

(sometimes UM)RO3* an% OTRO3 (sometimes RO3*! )RO3@UM)RO3 #acks t,e

structures t,at 'enerate t,e e#ectrica# /e#% &or erasure! T,ese %evices ,ave a win%ow on top.

usua##0 covere% b0 a paper sticker! To erase. t,e sticker is remove% an% t,e %evice is

e4pose% to intense u#travio#et #i',t &or -8$: minutes! T,e on#0 %i=erence between OTRO3

an% UM)RO3 is t,at OTRO3 #acks t,e UM win%ow + t,ere is no wa0 to erase t,e %ata!

A%%in' t,e UM win%ow to t,e %evice packa'e si'ni/cant#0 increases cost. so t,ere is a nic,e

&or one$time$pro'rammab#e %evices

Erasa/,e @r"'ramma/,e Read On,% Mem"r% Chi+s



T,e in&ormation store% in an )RO3 c,ip can be erased b0 e4posin' t,e c,ip to stron' UM

#i',t! )RO3 c,ips are easi#0 reco'ni?e% b0 t,e sma## 1uart? win%ow use% &or erasure! Once

erase% t,e c,ip can be re>+r"'rammed!

)RO3 is more e4pensive to bu0 per unit cost. but can prove c,eaper in t,e #on' run &or

some app#ications! 5or e4amp#e i& RO3 was use% &or /rmware t,at nee%e% up'ra%e% ever0

6 mont,s or so + it cou#% prove 1uite e4pensive bu0in' new c,ips`

E,e)tr"ni)a,,% Erasa/,e @r"'ramma/,e Read On,%Mem"r%

T,is ,as t,e a%%e% a%vanta'e t,at t,e in&ormation store% can be re$written in /,")#s an%

,ence can be use% to store s%stem settin's t,at t,e user ma0 want to c,an'e perio%ica##0!

T,is so#i% state memor0 ,as consi%erab#0 re%uce% in price over recent 0ears an% is

nowa%a0s common#0 use% to store s0stem settin's suc, as BIOS settin's

$*. What is di5eren)e /etween V",ati,e K N"n V",ati,e Mem"r%?V",ati,e mem"r%

Mo#ati#e memor0 is computer memor0 t,at re1uires power to maintain t,e store%

in&ormation! 3ost mo%ern semicon%uctor vo#ati#e memor0 is eit,er Static RA3 (see SRA3* or

%0namic RA3 (see RA3*! SRA3 retains its contents as #on' as t,e power is connecte% an%

is eas0 to inter&ace to but uses si4 transistors per bit! 0namic RA3 is more comp#icate% to

inter&ace to an% contro# an% nee%s re'u#ar re&res, c0c#es to prevent its contents bein' #ost!

However. RA3 uses on#0 one transistor an% a capacitor per bit. a##owin' it to reac, muc,

,i',er %ensities an%. wit, more bits on a memor0 c,ip. be muc, c,eaper per bit! SRA3 is

not wort,w,i#e &or %esktop s0stem memor0. w,ere RA3 %ominates. but is use% &or t,eir

cac,e memories! SRA3 is commonp#ace in sma## embe%%e% s0stems. w,ic, mi',t on#0 nee%

tens o& ki#ob0tes or #ess! 5ort,comin' vo#ati#e memor0 tec,no#o'ies t,at ,ope to rep#ace or

compete wit, SRA3 an% RA3 inc#u%e G$RA3. TTRA3. A$RA3 an% )TA RA3!

N"n>&",ati,e mem"r%"on$vo#ati#e memor0 is computer memor0 t,at can retain t,e store% in&ormation even w,en

not powere%! )4amp#es o& non$vo#ati#e memor0 inc#u%e rea%$on#0 memor0 (see RO3*. >as,

memor0. most t0pes o& ma'netic computer stora'e %evices (e!'! ,ar% %isks. >opp0 %iscs

an% ma'netic tape*. optica# %iscs. an% ear#0 computer stora'e met,o%s suc, as paper tape

an% punc,e% car%s! 5ort,comin' non$vo#ati#e memor0 tec,no#o'ies inc#u%e 5eRA3. CBRA3.

RA3. SO"OS. RRA3. Racetrack memor0. "RA3 an% 3i##ipe%e!

$-. What is a reentrant !un)ti"n?

A reentrant !un)ti"n is a &unction w,ic, can be sa&e#0 e4ecute% )"n)urrent,%! T,is

means it s,ou#% a##ow a re$entr0 w,i#e it is runnin'! T,e reentrant &unction s,ou#% work on#0

on t,e %ata 'iven b0 t,e ca##in' &unction! It must not ,ave an0 static %ata a#so!

T,e term reentrant is use% to re&er to si%e wa## pro/#es o& t,e no??#es. w,erein e4it

%iameters o& t,e no??#es are sma##er t,an entrance %iameters o& t,e no??#es so t,at t,e si%e



wa##s o& t,e no??#es are not perpen%icu#ar to a p#ane %e/ne% b0 an e4it sur&ace o& t,e no??#e

member!

A Reentrant &unction is a &unction w,ic, 'uarantee% t,at w,ic, can be work we## un%er mu#ti

t,rea%e% environment! 3ean w,i#e &unction is access b0 one t,rea%. anot,er t,rea% can ca##

it mean t,ere is separate e4ecution stack an% ,an%#in' &or eac,! So &unction s,ou#% not

contain an0 static or s,are% variab#e w,ic, can ,arm or %isturb t,e e4ecution!

$. Wh% we are usin' U8SD I! CAN su++"rt dia'n"sti)s )"mmuni)ati"n?

In CA" it wi## support interna# %ia'nostic messa'es! US K ;W2888 are use% &or to test wit,

e4terna# tester an% to know t,e t0pe o& prob#em

$0. "w t" re)"&er !r"m CAN> us"5?

To %istin'uis, between temporar0 an% permanent &ai#ures ever0 CA" bus contro##er ,as two

)rror Counters T,e R)C (Receive )rror Counter* an% t,e T)C (Transmit )rror Counter*! T,e

counters are incremente% upon %etecte% errors respective#0 are %ecremente% upon correct

transmissions or receptions! epen%in' on t,e counter va#ues t,e state o& t,e no%e is

c,an'e% T,e initia# state o& a CA" bus contro##er is )rror Active t,at means t,e contro##er

can sen% active )rror 5#a's! T,e contro##er 'ets in t,e )rror assive state i& t,ere is an

accumu#ation o& errors!

On CA" bus contro##er &ai#ure or an e4treme accumu#ation o& errors t,ere is a state transition

to Bus O=! T,e contro##er is %isconnecte% &rom t,e bus b0 settin' it in a state o& ,i',$

resistance! The us O5 state sh"u,d "n,% /e ,e!t /% a s"!tware reset. A!ter s"!tware

reset the CAN /us )"ntr",,er has t" wait !"r 12 4 11 re)essi&e /its t" transmit a

!rame. This is /e)ause "ther n"des ma% +endin' transmissi"n reuests. It is

re)"mmended n"t t" start an hardware reset /e)ause the wait time ru,e wi,, n"t

/e !",,"wed then.

$0. What is Virtua, !un)ti"na, /us?



Mirtua# &unction bus can be %escribe% as a s0stem mo%e#in' an% communication concept! It

is #o'ica# entit0 t,at &aci#itates t,e

concept o& re#ocatabi#it0 wit,in t,e AUTOSAR so&tware arc,itecture b0 provi%in' a virtua#

in&rastructure t,at is in%epen%ent &rom an0 actua# un%er#0in' in&rastructure an% provi%es a##

services re1uire% &or a virtua# interaction between AUTOSAR components!

$2. Intra and Inter ECU )"mmuni)ati"n?

Intra$)CU w,ic, %enotes t,e communication between two so&tware components resi%in' on

t,e same )CU an% Inter$)CU w,ic, %enotes t,e situation w,en two so&tware

components resi%e on %i=erent )CULs t,at are connecte% via a bus network!

$3. What is the di5eren)e /etween ',"/a, and stati) ',"/a, &aria/,es?

F,"/a, &aria/,es are variab#es %e/ne% outsi%e o& an0 &unction! T,eir scope starts at t,e

point w,ere t,e0 are %e/ne% an% #asts to t,e en% o& t,e /#e! T,e0 ,ave e4terna# #inka'e.

w,ic, means t,at in ot,er source /#es. t,e same name re&ers to t,e same #ocation in

memor0!Stati) ',"/a, &aria/,es are private to t,e source /#e w,ere t,e0 are %e/ne% an% %o not

con>ict wit, ot,er variab#es in ot,er source /#es w,ic, wou#% ,ave t,e same name!

*(. "w t" a))ess a F,"/a, &aria/,es in "ther B,es?

Mariab#es %ec#are% outsi%e o& a b#ock are ca##e% ',"/a, &aria/,es! X#oba# variab#es

,ave +r"'ram s)"+e. w,ic, means t,e0 can be accesse% ever0w,ere in t,e pro'ram. an%

t,e0 are on#0 %estro0e% w,en t,e pro'ram en%s!

Here is an e4amp#e o& %ec#arin' a '#oba# variab#e

2-:6<7F8

int 'PnJ @@ '#oba# variab#e int main(* int n_J @@ #oca# variab#e n_

@@ '#oba# vars can be seen ever0w,ere in pro'ram@@ so we can c,an'e t,eir va#ues ,ere

'Pn :JV @@ n_ is %estro0e% ,ere

Because '#oba# variab#es ,ave pro'ram scope. t,e0 can be use% across mu#tip#e /#es! In t,e

section on pro'rams wit, mu#tip#e /#es. 0ou #earne% t,at in or%er to use a &unction %ec#are%

in anot,er /#e. 0ou ,ave to use a &orwar% %ec#aration. or a ,ea%er /#e!

Simi#ar#0. in or%er to use a '#oba# variab#e t,at ,as been %ec#are% in anot,er /#e. 0ou ,ave to

use a &orwar% %ec#aration or a ,ea%er /#e. a#on' wit, t,e e4tern ke0wor%! )4tern te##s t,e

compi#er t,at 0ou are not %ec#arin' a new variab#e. but instea% re&errin' to a variab#e

%ec#are% e#sew,ere!

Here is an e4amp#e o& usin' a &orwar% %ec#aration st0#e e4tern

'#oba#!cpp



2

@@ %ec#aration o& 'PnMa#ueint 'PnMa#ue :J

main!cpp

2-:6<7

@@ e4tern te##s t,e compi#er t,is variab#e is %ec#are% e#sew,eree4tern int 'PnMa#ueJ int main(* 'PnMa#ue <J return 8JV

Here is an e4amp#e o& usin' a ,ea%er /#e e4tern

'#oba#!cpp

2

@@ %ec#aration o& 'PnMa#ueint 'PnMa#ue :J

'#oba#!,

2-:6<

fi&n%e& X9OBA9PH @@ ,ea%er 'uar%sf%e/ne X9OBA9PH @@ e4tern te##s t,e compi#er t,is variab#e is %ec#are% e#sew,eree4tern int 'PnMa#ueJ fen%i&

main!cpp

2

-:6

finc#u%e g'#oba#!,gint main(*

'PnMa#ue <J return 8JV

Xenera##0 speakin'. i& a '#oba# variab#e is 'oin' to be use% in more t,an 2 /#es. itLs better to

use t,e ,ea%er /#e approac,! Some pro'rammers p#ace a## o& a pro'rams '#oba# variab#es in

a /#e ca##e%'#oba#s!cpp. an% create a ,ea%er /#e name% '#oba#s!, to be inc#u%e% b0

ot,er !cpp /#es t,at nee% to use t,em!

9oca# variab#es wit, t,e same name as a '#oba# variab#e ,i%e t,e '#oba# variab#e insi%e t,at

b#ock! However. t,e '#oba# scope operator (* can be use% to te## t,e compi#er 0ou mean t,e

'#oba# version

2-:6<7

int nMa#ue :J int main(* int nMa#ue <J @@ ,i%es t,e '#oba# nMa#ue variab#e nMa#ueJ @@ increments #oca# nMa#ue. not '#oba# nMa#ue nMa#ue$$J @@ %ecrements '#oba# nMa#ue. not #oca# nMa#ue

return 8J



FV @@ #oca# nMa#ue is %estro0e%

However. ,avin' #oca# variab#es wit, t,e same name as '#oba# variab#es is usua##0 a recipe

&or troub#e. an% s,ou#% be avoi%e% w,enever possib#e! Usin' Hun'arian "otation. it is

common to %ec#are '#oba# variab#es wit, a 'P pre/4! T,is is an eas0 wa0 to %i=erentiate

'#oba# variab#e &rom #oca# variab#es. an% avoi% variab#es bein' ,i%%en %ue to namin'

co##isions!

"ew pro'rammers are o&ten tempte% to use #ots o& '#oba# variab#es. because t,e0 are eas0

to work wit,. especia##0 w,en man0 &unctions are invo#ve%! However. t,is is a ver0 ba% i%ea!

In &act. '#oba# variab#es s,ou#% 'enera##0 be avoi%e% comp#ete#0`

Wh% ',"/a, &aria/,es are e&i,

X#oba# variab#es s,ou#% be avoi%e% &or severa# reasons. but t,e primar0 reason is because

t,e0 increase 0our pro'ramLs comp#e4it0 immense#0! 5or e4amp#e. sa0 0ou were e4aminin' a

pro'ram an% 0ou wante% to know w,at a variab#e name% 'PnMa#ue was use% &or! Because

'PnMa#ue is a '#oba#. an% '#oba#s can be use% an0w,ere in t,e entire pro'ram. 0ouL% ,ave toe4amine ever0 sin'#e #ine o& ever0 sin'#e /#e` In a computer pro'ram wit, ,un%re%s o& /#es

an% mi##ions o& #ines o& co%e. 0ou can ima'ine ,ow #on' t,is wou#% take`

Secon%. '#oba# variab#es are %an'erous because t,eir va#ues can be c,an'e% b0 an0

&unction t,at is ca##e%. an% t,ere is no eas0 wa0 &or t,e pro'rammer to know t,at t,is wi##

,appen! Consi%er t,e &o##owin' pro'ram

2-

:6<7F82-:6

<7F282222-2

@@ %ec#are '#oba# variab#eint 'Pn3o%e J

voi% %oSomet,in'(* 'Pn3o%e 2JV int main(* 'Pn3o%e J

%oSomet,in'(*J

@@ ro'rammer e4pects 'Pn3o%e to be @@ But %oSomet,in' c,an'e% it to 2`

i& ('Pn3o%e *

cout dd g"o t,reat %etecte%!g dd en%#J e#se cout dd g9aunc,in' nuc#ear missi#es!!!g dd en%#J

return 8JV



"ote t,at t,e pro'rammer set 'Pn3o%e to . an% t,en ca##e% %oSomet,in'(*! Un#ess t,e

pro'rammer ,a% e4p#icit know#e%'e t,at %oSomet,in'(* was 'oin' to c,an'e t,e va#ue o&

'Pn3o%e. ,e or s,e was probab#0 not e4pectin' %oSomet,in'(* to c,an'e t,e va#ue`

Conse1uent#0. t,e rest o& main(* %oesnLt work #ike t,e pro'rammer e4pects (an% t,e wor#% is

ob#iterate%*!

X#oba# variab#es make ever0 &unction ca## potentia##0 %an'erous. an% t,e pro'rammer ,as no

eas0 wa0 o& knowin' w,ic, ones are %an'erous an% w,ic, ones arenLt` 9oca# variab#es are

muc, sa&er because ot,er &unctions can not a=ect t,em %irect#0! Conse1uent#0. '#oba#

variab#es s,ou#% not be use% un#ess t,ere is a ver0 'oo% reason`

*1. What is the use "! C"m+,e4 8e&i)e 8ri&ers in AUTOSAR?

Since t,e AUTOSAR #a0ere% so&tware arc,itecture restricts %irect access to ,ar%ware &rom

upper #a0ers. an a%%itiona# concept is provi%e% in or%er to b0pass t,at restriction &or

resource critica# an%@or "on$AUTOSAR comp#iant so&tware components! T,e Comp#e4 evice

river provi%es an AUTOSAR Inter&ace to t,e app#ication #a0er an% ,as %irect access tova#ues on t,e p,0sica# #a0er! T,is is usua##0 use% &or t,e imp#ementation o& comp#e4 sensor

or actuator %rivers t,at nee% %irect contro# over t,e un%er#0in' ,ar%ware!

*. "w t" setD ),earD t"'',e and )he)#in' a sin',e /it in C?

Use t,e bitwise OR operator (* to set a bit!

number dd 4J

T,at wi## set bit 4!

C,earin' a /it

Use t,e bitwise A" operator (K* to c#ear a bit!

number K j( dd 4*J

T,at wi## c#ear bit 4! _ou must invert t,e bit strin' wit, t,e bitwise "OT operator (j*. t,en

A" it!

T"'',in' a /it

T,e OR operator (h* can be use% to to''#e a bit!

number h dd 4J

T,at wi## to''#e bit 4!

Che)#in' a /it

_ou %i%nLt ask &or t,is but I mi',t as we## a%% it!



To c,eck a bit. A" it wit, t,e bit 0ou want to c,eck

bit number K ( dd 4*J

T,at wi## put t,e va#ue o& bit 4 into t,e variab#e bit!

*. What is Wat)hd"' timer?

A watc,%o' timer (or computer operatin' proper#0 (CO* timer* is a computer ,ar%ware or

so&tware timer t,at tri''ers a s0stem reset or ot,er corrective action i& t,e main pro'ram.

%ue to some &au#t con%ition. suc, as a ,an'. ne'#ects to re'u#ar#0 service t,e watc,%o'

(writin' a service pu#se to it. a#so re&erre% to as kickin' t,e %o'. pettin' t,e %o'.

&ee%in' t,e watc,%o' or wakin' t,e watc,%o'*! T,e intention is to brin' t,e s0stem

back &rom t,e unresponsive state into norma# operation! Watc,%o' timers can be more

comp#e4. attemptin' to save %ebu' in&ormation onto a persistent me%iumJ i!e! in&ormation

use&u# &or %ebu''in' t,e prob#em t,at cause% t,e &au#t! In t,is case a secon%. simp#er.

watc,%o' timer ensures t,at i& t,e /rst watc,%o' timer %oes not report comp#etion o& its

in&ormation savin' task wit,in a certain amount o& time. t,e s0stem wi## reset wit, or wit,outt,e in&ormation save%! T,e most common use o& watc,%o' timers is in embe%%e% s0stems.

w,ere t,is specia#i?e% timer is o&ten a bui#t$in unit o& a microcontro##er!

*$.What is the di5eren)e /etween 2 /it 1 /it and $ /it +r")ess"r?

i=erent &ami#ies o& micros var0 in t,eir capabi#ities! T,e number o& bits Nust re&ers to t,e

wi%t, o& t,e %ata pipe. w,ic, #imits t,e precision o& mat,. a#t,ou', man0 micros wi## eit,er

emu#ate ,i',er or%er mat, or ,ave specia# HW t,at can per&orm ,i',er precision mat,

&unctions!

T,e ,istoric %i=erence ,as been price 7$bit was c,eapest. -2$bit was e4pensive! T,is is sti##true in 'enera##0. but t,e price o& 6$bit parts ,ave come %own si'ni/cant#0!

3ost 7$bit processors are o#% an% run on o#% arc,itectures. so t,e0 ten% to be s#ower! T,e0

are a#so ma%e more c,eap#0. since t,at is w,ere t,e competition is at t,e 7$bit point. an%

t,is makes t,em ten% towar%s s#owness! T,e0 a#so ten% to ,ave a #ow #imit on supporte%

RA3@ot,er stora'e. but t,e actua# amount %epen%s on t,e &ami#0!



6$bit processors ten% to &ocus on price as we##. but t,ere is a #ar'e ran'e o& parts avai#ab#e.

some o& w,ic, ,ave &air#0 ,i', per&ormance an% #ar'e amounts o& on$c,ip perip,era#s! T,ese

parts usua##0 per&orm &aster t,an 7$bit parts on mat, w,ere t,e precision is 'reater t,an 7

bits. an% ten% to ,ave more a%%ressab#e memor0!

-2$bit c,ips compete primari#0 on per&ormance &or an app#ication! T,ere is a consi%erab#e

ran'e o& -2$bit parts avai#ab#e. eac, tar'ete% at some speci/c app#ication! T,e0 ten% to

come #oa%e% wit, perip,era#s an% compete on &eature comp#eteness! T,e0 ,ave a #ar'e

amount o& a%%ressab#e memor0 an% t,e per&ormance ten%s to be better t,an 6$bit parts!

**. What is a 7un)ti"n @"inter ?

A &unction pointer is a variab#e t,at stores t,e a%%ress o& a &unction t,at can #ater be ca##e%

t,rou', t,at &unction pointer! T,is is use&u# because &unctions encapsu#ate be,avior! 5or

instance. ever0 time 0ou nee% a particu#ar be,avior suc, as %rawin' a #ine. instea% o&

writin' out a bunc, o& co%e. a## 0ou nee% to %o is ca## t,e &unction! But sometimes 0ou wou#%

#ike to c,oose %i=erent be,aviors at %i=erent times in essentia##0 t,e same piece o& co%e!

)4amp#e int ([&p* (int. int*J $ 5unction pointer returnin' an inte'er

*-. Si=e "! 8atat%+es

Name 8es)ri+ti"nSi=eL Ran'eL

c,ar C,aracter or sma## inte'er!b0te

si'ne% $27 to 2<unsi'ne% 8 to 2::

s,ort int (s,ort* S,ort Inte'er!2b0tes

si'ne% $-2<67 to -2<6<unsi'ne% 8 to 6::-:

int Inte'er!b0tes

si'ne% $2<7-67 to2<7-6<unsi'ne% 8 to2FF6<2F:

#on' int (#on'* 9on' inte'er!b0tes

si'ne% $2<7-67 to2<7-6<unsi'ne% 8 to2FF6<2F:

boo#Boo#ean va#ue! It can take one o& twova#ues true or &a#se!

b0te true or &a#se

>oat 5#oatin' point number!b0tes @$ -!e @$ -7 (j< %i'its*

%oub#e oub#e precision >oatin' point number!

7b0t

es

@$ !<e @$ -87 (j:

%i'its*

#on' %oub#e9on' %oub#e precision >oatin' pointnumber!

7b0tes

@$ !<e @$ -87 (j:%i'its*

*. What is the di5eren)e /etween t%+ede! K Ma)r"s?

T0pe%e& is use% to create a new name to an a#rea%0 e4istin' %ata t0pe! Re%e/ne t,e name

creates con>ict wit, t,e previous %ec#aration!



e'

t0pe%e& unsi'ne% int UI"T-2

3acros \f%e/ne] is a %irect substitution o& t,e te4t be&ore comp#in' t,e w,o#e co%e! In t,e

'iven e4amp#e. its Nust a te4tua# substitution! w,ere t,ere is a posibi#it0 o& re%e/nin' t,e

macro

e'

f%e/ne c,ointer c,ar [

fun%e& c,ointer

f%e/ne c,ointer int [

T%+ede! are used !"r de),arati"ns when )"m+are with ma)r"

t0pe%e&s can correct#0 enco%e pointer t0pes!w,ere as f)5I")S are Nust rep#acements

%one b0 t,e preprocessor!

5or e4amp#e.

! t0pe%e& c,ar [Strin'PtJ

2! f%e/ne Strin'P% c,ar [

-! Strin'Pt s. s2J Strin'P% s-. sJ

s. s2. an% s- are a## %ec#are% as c,ar [. but s is %ec#are% as a c,ar. w,ic, is probab#0 not

t,e intention!

*0. What is the di5eren)e /etween a ma)r" and a !un)ti"n?

3acros are essentia##0 s,ort,an% representations o& arbitrar0 sections o& t,e source co%e.

w,ic, makes t,e source co%e. w,i#e its (t,e macro temp#ateLs* e4pansion rep#aces eac, o&

its presence prior to compi#ation! W,atever is t,ere to %o wit, 3acros. it is %one b0 t,e

preprocessor. so t,at t,e source co%e is rea%0 &or compi#ation! 5unction is a ca##in' routine.

w,ence a #ar'e pro'ram is %ivi%e% into separate portions. eac, portion %oin' a separate Nob.

an% proper ca##in' o& t,ese portions in %i=erent p#aces combines t,e works %one b0 t,em

into t,e re1uire% comp#ete output! T,us &unctions ,ave not,in' to %o wit, t,e preprocessin'

perio%. t,e0 are Nust compi#e%! To some e4tent &unction an% macro is simi#ar. &or a macro can

occasiona##0 be invoke% to per&orm a task t,at is 'enera##0 entruste% to a &unction! But t,e

simi#arit0 en%s t,ere!

T,e %i=erences are

! 3acro consumes #ess time! W,en a &unction is ca##e%. ar'uments ,ave to be passe%

to it. t,ose ar'uments are accepte% b0 correspon%in' %umm0 variab#es in t,e

&unction. t,e0 are processe%. an% /na##0 t,e &unction returns a va#ue t,at is assi'ne%

to a variab#e (e4cept &or a voi% &unction*! I& a &unction is invoke% a number o& times.

t,e times a%% up. an% compi#ation is %e#a0e%! On t,e ot,er ,an%. t,e macro



e4pansion ,a% a#rea%0 taken p#ace an% rep#ace% eac, occurrence o& t,e macro in t,e

source co%e be&ore t,e source co%e starts compi#in'. so it re1uires no a%%itiona# time

to e4ecute!

2! 5unction consumes #ess memor0! W,i#e a &unction rep#ete wit, macros ma0 #ook

succinct on sur&ace. prior to compi#ation. a## t,e macro$presences are rep#ace% b0

t,eir correspon%in' macro e4pansions. w,ic, consumes consi%erab#e memor0! Ont,e ot,er ,an%. even i& a &unction is invoke% 88 times. it sti## occupies t,e same

space! Hence &unction is more amenab#e to #ess memor0 re1uirements

*2. What is in,ine !un)ti"n?

In#ine &unction is t,e optimi?ation tec,ni1ue use% b0 t,e compi#ers! One can simp#0 prepen%

in#ine ke0wor% to &unction protot0pe to make a &unction in#ine! In#ine &unction instruct

compi#er to insert comp#ete bo%0 o& t,e &unction w,erever t,at &unction 'ot use% in co%e!

Ad&anta'es :>

* It %oes not re1uire &unction ca##in' over,ea%!

2* It a#so save over,ea% o& variab#es pus,@pop on t,e stack. w,i#e &unction ca##in'!-* It a#so save over,ea% o& return ca## &rom a &unction!

* It increases #oca#it0 o& re&erence b0 uti#i?in' instruction cac,e!

:* A&ter in$#inin' compi#er can a#so app#0 intraproce%ura# optmi?ation i& speci/e%! T,is is t,e

most important one. in t,is wa0 compi#er can now &ocus on %ea% co%e e#imination. can 'ive

more stress on branc, pre%iction. in%uction variab#e e#imination etc!!

8isad&anta'es $

* 3a0 increase &unction si?e so t,at it ma0 not /t on t,e cac,e. causin' #ots o& ca,ce miss!

2* A&ter in$#inin' &unction i& variab#es number w,ic, are 'oin' to use re'ister increases t,an

t,e0 ma0 create over,ea% on re'ister variab#e resource uti#i?ation!

-* It ma0 cause compi#ation over,ea% as i& some bo%0 c,an'es co%e insi%e in#ine &unction

t,an a## ca##in' #ocation wi## a#so be compi#e%!

* I& use% in ,ea%er /#e. it wi## make 0our ,ea%er /#e si?e #ar'e an% ma0 a#so make it

unrea%ab#e!

:* I& somebo%0 use% too man0 in#ine &unction resu#tant in a #ar'er co%e si?e t,an it ma0

cause t,ras,in' in memor0! 3ore an% more number o& pa'e &au#t brin'in' %own 0our

pro'ram per&ormance!

6* Its not use&u# &or embe%e% s0stem w,ere #ar'e binar0 si?e is not pre&erre% at a## %ue to

memor0 si?e constraints

*3. What is the di5eren)e /etween a ma)r" and a in,ine !un)ti"n?

Ma)r"s :

! input ar'ument %atat0pe c,eckin' canLt be %one!2! compi#er ,as no i%ea about macros

-! Co%e is not rea%ab#e

! macros are a#wa0s e4pan%e% or rep#ace% %urin' preprocessin'. ,ence co%e si?e is more!

:! macro canLt return!

In,ine !un)ti"n :

! input ar'ument %atat0pe can be %one!

2! compi#er knows about in#ine &unctions!



-! co%e is rea%ab#e

! in#ine &unctions are ma0 not be e4pan%e% a#wa0s

:! can return!

-(. @re+r")ess"r Statements i!de!D e,seD endi!

T,ese provi%e a rapi% wa0 to c#ip out an% insert co%e!

Consi%erJ

#define FIRST

main()

{

int a, b, c;

#ifdef FIRST

a=2; b=6; c=4;

#else

printf("Enter a:");

scanf("%d", &a);

printf("Enter a:");

scanf("%d", &a);

printf("Enter a:");

scanf("%d", &a);



#endif

additonal code

"ote t,at i& 5IRST is %e/ne% (w,ic, it is in t,e above* t,e va#ues o& a. b an% c are ,ar%co%e%

to va#ues o& 2. 6 an% ! T,is can save a #ot o& time w,en %eve#opin' so&tware as it avoi%s

te%ious#0 t0pin' ever0t,in' in eac, an% ever0time 0ou run 0our routine! W,en 5IRST is

%e/ne%. a## t,at is passe% to t,e compi#er is t,e co%e between t,e fi&%e& an% t,e fe#se! T,e

co%e between t,e fe#se an% t,e fen%i& is not seen b0 t,e compi#er! It is as i& it were a## a

comment!

Once 0ou ,ave 0our routine workin'. an% %esire to insert t,e print& an% scan&s. a## t,at is

re1uire% is to 'o back an% %e#ete t,e t,e f%e/ne 5IRST! "ow. t,e compi#er %oes not see t,eJ

a=2; b=6; c=4;

"w t" )a,)u,ate CRC Seuen)e in a CAN 7rame?

T,e receivers ca#cu#ate t,e CRC in t,e same wa0 as t,e transmitter as &o##ows

! T,e messa'e is re'ar%e% as po#0nom an% is %ivi%e% b0 t,e 'enerator po#0nom

4: 4 48 47 4< 4 4- !

2! T,e %ivision rest o& t,is mo%u#o2 %ivision is t,e CRC se1uence w,ic, is transmitte%

to'et,er wit, t,e messa'e!

-! T,e receiver %ivi%es t,e messa'e inc#usive t,e CRC se1uence b0 t,e 'enerator

po#0nom!

A CRC error ,as to be %etecte%. i& t,e ca#cu#ate% resu#t is not t,e same as t,at receive% in

t,e CRC se1uence! In t,is case t,e receiver %iscar%s t,e messa'e an% transmits an )rror

5rame to re1uest retransmission!

-1. 8i5eren)e /etween stati) and d%nami) RAM?



Static RA3 (SRA3* + Hi', cost K 5ast

! times more e4pensive

2! Mer0 #ow access time

-! Can store as muc,

! In&ormation store% on RS >ip$>ops

:! "o nee% &or re&res,in'

0namic RA3 (RA3* + 9ow cost K s#ow

! 9ow cost

2! Consumes #ess power

-! Can store times as muc,

! In&ormation store% on 5)T transistors

:! "ee%s to be re&res,e%

CAN"e T"", Questi"ns:

What is di5eren)e the /etween IF and F /,")# in CANa,%=erCAN"e t"",?

Answer T,ere are two #imitations to t,e Xenerator b#ock t,at #imit its e=ectiveness in

comp#e4 tasks! T,e b#ock is mis#ea%in' &or some peop#e because it re1uires mu#tip#e

win%ows &or settin' up t,e transmit messa'e #ist! T,e secon% prob#em is t,e b#ock settin's

,ave to be set be&ore t,e CA"a#0?er measurement starts! "o c,an'es can be ma%e i& t,e

measurement is runnin'!

5ortunate#0. CA"a#0?er ,as anot,er transmission b#ock t,at e#iminates bot, practica#

#imitations t,e Interactive Xenerator b#ock (IF*! T,e IF b#ock combines t,e con/'uration

win%ows o& t,e Xenerator b#ock into one win%owJ t,ere&ore. ever0t,in' can be setup in onespot! In a%%ition. c,an'es can be ma%e wit, t,e IF.

Wit,out CA9.can we simu#ate t,e ot,er )CULs CA" 3essa'es e4cept Test )CU in t,e CA"

Simu#ation "etwork in CA"oe too# wit,out usin' IX or X b#ocks!

"w t" )han'e the /aud rate in CAN"e with"ut )han'in' the )"de?

T,e bit rate ma0 be c,an'e% b0 eit,er c,an'in' t,e osci##ator &re1uenc0. w,ic, is usua##0

restricte% b0 t,e processor re1uirements. or b0 speci&0in' t,e #en't, o& t,e bit se'ments in

time 1uantum an% t,e presca#er va#ue!

In Canoe too#. we can c,an'e t,e bus timin' re'ister 8 K va#ues &or correctin' t,e bau%

rate!

In Autosar. we can use post bui#% con/'uration &or CA" bau%rate va#ues!

What is en&ir"nment &aria/,e?



)nvironment variab#es are %ata obNects '#oba# to t,e CA"oe environment an% are use% to

#ink t,e &unctions o& a CA"oe pane# to CA9 pro'rams!

What is I9 and SI9 testin'?

Answer: ardware>in>the>,""+ (HI9* simu#ation is a tec,ni1ue t,at is use% in t,e

%eve#opment an% test o& comp#e4 rea#$time embe%%e% s0stems! HI9 simu#ation provi%es an

e=ective p#at&orm b0 a%%in' t,e comp#e4it0 o& t,e p#ant un%er contro# to t,e test p#at&orm!

T,e comp#e4it0 o& t,e p#ant un%er contro# is inc#u%e% in test an% %eve#opment b0 a%%in'

a mat,ematica# representation o& a## re#ate% %0namic s0stems! T,ese mat,ematica#

representations are re&erre% to as t,e p#ant simu#ation! T,e embe%%e% s0stem to be teste%

interacts wit, t,is p#ant simu#ation!

ardware>In>the>9""+ S%stem is an e=ective p#at&orm &or %eve#opin' an% testin'

comp#e4 rea#$time embe%%e% s0stems! HI9 s0stem provi%es t,e comp#e4it0 o& t,e p#ant

un%er contro# usin' mat,ematica# representation. ca##e% p#ant simu#ation. o& a## re#ate%

%0namic s0stems! It a#so inc#u%es e#ectrica# emu#ation o& sensors an% actuators w,ic, act as

t,e inter&ace between t,e p#ant simu#ation an% t,e embe%%e% s0stem un%er test!Ad&anta'es "! I9 S%stem

rovi%es Cost Savin's b0 S,ortene% eve#opment time

Comp#ete. consistent test covera'e!

Supports automate% testin'

)nab#es testin' t,e ,ar%ware wit,out bui#%in' a p#ant protot0pe

Simu#ator per&orms test outsi%e t,e norma# ran'e o& operation

Supports repro%ucib#e test runs t,at can assist in uncoverin' an% trackin' %own ,ar%

to /n% prob#ems!

)nab#es testin' wit, #ess risk o& %estro0in' t,e s0stem

SI9: SI9 re&ers to t,e kin% o& testin' %one to va#i%ate t,e be,avior o& t,e C$co%e use% in t,e

contro##er! T,at co%e can be auto$'enerate% &rom t,e mo%e# use% in a#'orit,m

%eve#opment! )mmeska0 ,as a %eep un%erstan%in' o& SI9 testin' an% auto$co%e 'eneration

&rom t,e man0 SI9 proNects we ,ave per&orme% &or our customers!

Testin' and Va,idati"n

#ant mo%e# %eve#ope% in ve,ic#e simu#ation environment is importe% to Simu#ink as a

#ibrar0!

Contro##er is teste% in #oop wit, t,e p#ant &or %i=erent routes an% spee% pro/#es!

Contro##er is teste% &or %i=erent &au#t mo%es o& t,e s0stem usin' XUI Misua#Conne4

RTOS Questi"n:

What is RTOS?

Rea#$Time Operatin' S0stem is a mu#titaskin' operatin' s0stem inten%e% &or rea#$timeapp#ications! It is use% on ever0 %evice@s0stem nee%in' rea# time operations t,at means

operations base% not on#0 on correctness but a#so upon t,e time (c#ock c0c#es* in w,ic, t,e0

are per&orme%!

In 'enera#. an operatin' s0stem (OS* is responsib#e &or mana'in' t,e ,ar%ware resources o&

a computer an% ,ostin' app#ications t,at run on t,e computer! An RTOS per&orms t,ese



tasks. but is a#so specia##0 %esi'ne% to run app#ications wit, ver0 precise timin' an% a ,i',

%e'ree o& re#iabi#it0! T,is can be especia##0 important in measurement an% automation

s0stems w,ere %owntime is cost#0 or a pro'ram %e#a0 cou#% cause a sa&et0 ,a?ar%! To be

consi%ere% rea#$time. an operatin' s0stem must ,ave a known ma4imum time &or eac, o&

t,e critica# operations t,at it per&orms (or at #east be ab#e to 'uarantee t,at ma4imum most

o& t,e time*! Some o& t,ese operations inc#u%e OS ca##s an% interrupt ,an%#in'! Operatin's0stems t,at can abso#ute#0 'uarantee a ma4imum time &or t,ese operations are common#0

re&erre% to as ,ar% rea#$time. w,i#e operatin' s0stems t,at can on#0 'uarantee a ma4imum

most o& t,e time are re&erre% to as so&t rea#$time!

E4am+,e: Ima'ine t,at 0ou are %esi'nin' an airba' s0stem &or a new mo%e# o& car! In t,is

case. a sma## error in timin' (causin' t,e airba' to %ep#o0 too ear#0 or too #ate* cou#% be

catastrop,ic an% cause inNur0! T,ere&ore. a ,ar% rea#$time s0stem is nee%e%J 0ou nee%

assurance as t,e s0stem %esi'ner t,at no sin'#e operation wi## e4cee% certain timin'

constraints! On t,e ot,er ,an%. i& 0ou were to %esi'n a mobi#e p,one t,at receive%

streamin' vi%eo. it ma0 be ok to #ose a sma## amount o& %ata occasiona##0 even t,ou', onavera'e it is important to keep up wit, t,e vi%eo stream! 5or t,is app#ication. a so&t rea#$time

operatin' s0stem ma0 suce! An RTOS can 'uarantee t,at a pro'ram wi## run wit, ver0

consistent timin'! Rea#$time operatin' s0stems %o t,is b0 provi%in' pro'rammers wit, a

,i', %e'ree o& contro# over ,ow tasks are prioriti?e%. an% t0pica##0 a#so a##ow c,eckin' to

make sure t,at important %ea%#ines are met!

"w Rea,>Time OSs 8i5er !r"m Fenera,>@ur+"se OSs?

Operatin' s0stems suc, as 3icroso&t Win%ows an% 3ac OS can provi%e an e4ce##ent p#at&orm

&or %eve#opin' an% runnin' 0our non$critica# measurement an% contro# app#ications!

However. t,ese operatin' s0stems are %esi'ne% &or %i=erent use cases t,an rea#$time

operatin' s0stems. an% are not t,e i%ea# p#at&orm &or runnin' app#ications t,at re1uire

precise timin' or e4ten%e% up$time! T,is section wi## i%enti&0 some o& t,e maNor un%er$t,e$

,oo% %i=erences between bot, t0pes o& operatin' s0stems. an% e4p#ain w,at 0ou can e4pect

w,en pro'rammin' a rea#$time app#ication!

Interru+t 9aten)%

Interrupt #atenc0 is measure% as t,e amount o& time between w,en a %evice 'enerates an

interrupt an% w,en t,at %evice is service%! W,i#e 'enera#$purpose operatin' s0stems ma0

take a variab#e amount o& time to respon% to a 'iven interrupt. rea#$time operatin' s0stems

must 'uarantee t,at a## interrupts wi## be service% wit,in a certain ma4imum amount o&

time! In ot,er wor%s. t,e interrupt #atenc0 o& rea#$time operatin' s0stems must be boun%e%

Unanswered Inter&iew Questi"ns :I! %"u #n"w )"mment as re+,%;

What is the use "! @assi&e err"r n"de?

)rror assive receivers can no #on'er interrupt t,e %ata trans&er as a recessive )rror 5#a'

%oes not in>uence t,e bus #eve#s! An )rror assive transmitter can sti## interrupt its own

messa'e b0 sen%in' a passive )rror 5#a'! Attention. i& one Receiver is in error passive mo%e

no %ata consistenc0 is 'uarantee% an0 more!



"w t" Bnd the /u' in )"de usin' de/u''er i! +"inter is +"intin' t" a i,,e'a,

&a,ue?

I! tw" CAN messa'es with same I8 sendin' at a same timeD di5erent data whi)h

)an n"de wi,, 'ain ar/itrati"n? "w t" test it?

Is it +"ssi/,e t" de),are stru)t and uni"n "ne inside "ther? E4+,ain with e4am+,e

! Spi an% I2C %i=erence!2! W,at is US a%vanta'es

-! W,at is cross compi#er

! Unit@inte'ration@a## testin's!

:! Re'ression testin'!

6! Test case t0pes!

<! 3a##oc ca##oc

7! 5unction pointers A%vanta'e w,ere it is use%

How man0 can %atabase /#es are re1uire% &or CA" "etwork simu#ation in CA"oe too#!

w,at is t,e %i=erence between CA"a#0?er.CA"oe an% CA"ape too#s

3ention t,e &ew uses o& t,e CA"oe too#

w,at is a pane# is CA"oe Too# an% its Use

W,0 CA9 scriptin' is use% in CA"oe too#

Is it possib#e to simu#ate ot,er )CULs )4cept Test )CU wit,out CA9 Scriptin' in CA"oe too#

w,at is purpose o& CC protoco# w,ic, is a#so use% in CA"ape too#

Em/edded 8e&e,"+ment 8")uments:

Intro%uctionPtoPpro'Pembe%%e%Ps0stems

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U9 1D (1$ E --7 3

I must Sa0 t,anks &or t,is artice# *

REPLY

2! Vijaisankar

U9 *D (1$ E 6: A3

superb 'enera##0 covere%!an% t,e per&ormance o& a can%ia%ate %epen%s on ,ow ,e

presents an% ,is past e4perience!T,anks a #ot!

REPLY

-! +a&an

AUFUST D (1$ E 7: A3

tru#0 'oo% *

T,anks!

REPLY

! Sonali

AUFUST D (1$ E : A3

T,ank 0ou ver0 muc, &or t,is artica#it is rea##0 ,e#p&u#!

REPLY

:! ajay

AUFUST D (1$ E 28 3

awesome tutoria#`` t,an4 man*

REPLY

6! Robinson Matew

AUFUST 1$D (1$ E :-8 3

ver0 use&u#!t,anks

REPLY

<! !a"aAUFUST (D (1$ E 28: 3

Hi',#0 in&ormative content! T,anks!

REPLY

7! Rajaseker

AUFUST D (1$ E <: A3

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e4ce##ent ver0 use&u# t,anks a#ot!

REPLY

F! #a"$is

AUFUST 2D (1$ E F A3

Rea##0 Use&u# &or Nob seekers to 'et prepare% to answer suc, 1uestions an% t,e 1uestions are

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8! Imran kan

SE@TEMER 1*D (1$ E 8 3

Rea##0 Xoo%

REPLY

! VE%A%RI BABU

SE@TEMER 12D (1$ E 26 3

T,ank 0ou ver0 muc, &or t,is artic#eit is rea##0 ,e#p&u#!

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2! &ari

SE@TEMER 0D (1$ E -8: 3

Super artic#e!!``` T,anks &or s,arin'!!```` *Hope &or more!!``` * * Its rea##0 ver0 muc, ,e#p&u#``````````````

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-! Ravisa"ar

OCTOER $D (1$ E ::7 3

)4ce##ent work !!T,anks a #ottttits ver0 use&u#e &or e4perience% can%i%ates a#so

won%er&u# Nobrea##0 'oo% Nob

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! Busan

OCTOER 1(D (1$ E 7- A3

ra##0 use&u#

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:! Busan

OCTOER 1(D (1$ E 7- A3

rea##0 use&u#

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6! 'atmaraj

OCTOER 10D (1$ E 2: 3

Awesome tutoria#Rea##0 use&u# !t,ank u

REPLY

<! vinot

OCTOER 0D (1$ E 782 A3

rea##0 &antastic tutoria#!!

REPLY

7! satis

NOVEMER 0D (1$ E 26 3

T,ank 0ou

)4ce##ent work

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F! VI#A( )M

8ECEMER 1*D (1$ E :88 A3

T,ank a #ot! *

REPLY

28! Sweta*!

ANUAR $(D (1* E 26 A3

Mer0 Use&u## T,ank 0ou $*

REPLY

2! sin'h,"&esuuu

7ERUAR 1D (1* E 66 A3

"o Wor%s. simp#0 superb!! *

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22! we/site

MARC 1D (1* E 6-7 3



















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s,arin' in %e#icious! An% o& course. t,ank 0ou on 0our

sweat`

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2-! %ines

A@RI9 10D (1* E 2-< 3

Superb b#o'``` &or )mbe%%e% )n'ineers

REPLY

2! sa+in

A@RI9 12D (1* E 78 3

it is t,e rea# s,arin' ;now#e%'e !T,ank u ver0 muc, sir

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2:! #ayakumar,krisna"iri

A@RI9 1D (1* E :6 A3

Xoo% + winNk'

REPLY

26! Ra"u

MA (D (1* E 286 3

rea##0 nice one````````

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2<! Vijay

MA 1D (1* E :6 3

Rea##0 use&u# artic#e

REPLY

27! Babu

UNE D (1* E 2:2 3

HI t,is Babu rea##0 Superb w,en ever0 i went to interview i &ace% A# t,ese 1uestions!i 'o

t,rou', session its rea##0 use&u# &or me! i 'ot answer &or some o& t,e 1uestions

awesome!T,anks &or 0our Ma#uab#e time to spen% an% post t,ese 1uestions!"ice

































REPLY

2F! !am

UNE *D (1* E 2F A3

T,ank 0ou so muc, ̀

REPLY

-8! Anves

U9 D (1* E -8 A3

Xoo% in&ormation T,ank 0ou`

REPLY

-! T"m ard% W"r#"ut

U9 -D (1* E 2 A3

I am in &act %e#i',te% to '#ance at t,is b#o' posts w,ic, inc#u%es tons o& ,e#p&u# &acts.

t,anks &or provi%in' suc, %ata!

REPLY

-2! $ivya

AUFUST 13D (1* E 8-6 A3

T,ank 0ou &or t,e 5AQLs wit, Answers!t,ank 0ou ver0 muc,!

REPLY

--! A$ys,Bernar$ Sasu

AUFUST (D (1* E 6 3

How to /n% t,e bu' in co%e usin' %ebu''er i& pointer is pointin' to a i##e'a# va#ue

Answer

Usua##0 t,is wi## #ea% to a s0stem e4ception! )ver0 core (CU* ,as its own wa0 o& re'isterin'

t,e a%%ress w,ic, cause% t,is e4ception! So to so#ve it. 0ou nee% to %i' a #itt#e in t,e corels

manua#! Its usua##0 some specia#i?e% re'isters (e4 owerC arc,itecture*. or t,e a%%ress is

in t,e stack at a certain #ocation (e4 AR3*! 5o##owin' t,at a%%ress wi## #ea% 0ou to t,e inva#i%

pointer!

REPLY

-! +enna

OCTOER 3D (1* E 27 3

)4ce##ent tutoria#!!Covere% most o& t,e embe%%e% s0stem 1uestions!T,anks a #ot keep it up!








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REPLY

-:! %ananjay

OCTOER 10D (1* E 27 3

T,ank 0ou ver0 muc, &or use&u# in&ormation! I& 0ou Have more in&ormation on CA"a#0?er@

CA"oe @ CA9 p#ease keep postin'

REPLY

-6! +etu

NOVEMER 0D (1* E 8 A3

Rea##0 Use&u# &or Nob seekers

REPLY

-<! Amol

8ECEMER D (1* E 22< 3

t,anku sir &or suc, a va#uab#e in&ormation

REPLY

-7! Barat -anwar

8ECEMER $D (1* E :2 A3

T,ank0ou &or t,is artic#e*

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-F! Maan

8ECEMER -D (1* E 82< A3

Super artic#e. Covere% a#most a## points!! T,anks &or t,e ost*

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8! )rabu

8ECEMER -D (1* E 86 A3

5rien%s.#ease s,are t,is #ink to )mp#o0ee an% not to )mp#o0er````!!Hope 0ou 'u0s un%erstan%

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! Tusar

ANUAR 2D (1- E 28- 3






































t,ank 0ou so muc, &or t,is post *

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2! murali

ANUAR $D (1- E 7: A3

i was preparin' on suc, t,in's &or : mont,s i& t,is %ocument 'ot ear#ier &or me .. i wou#% bemore #uck0!!

t,anks &or %ocument

REPLY

-! Vijay Tilak

7ERUAR *D (1- E 7 A3

T,ank 0ou %u%e Tons o& in&o &or automotive embe%%e% %eve#oper (be'inner*

REPLY

! nive$ita

7ERUAR 1(D (1- E 8< A3

ver0 use&u# post t,ank u so muc, an% ,ats o= to 0our e=ortscovere% ever0t,in' in one

artic#e

REPLY

:! rajat

7ERUAR D (1- E <8- A3

ver0 use&u#

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6! abilas

MARC 1$D (1- E -2< 3

Cross Compi#er Co%e wi## be compi#e% in one mac,ine an% compi#e% co%e wi## run in ot,er

mac,ine!

"ative Compi#er Compi#e% co%e wi## be e4ecute% in t,e same compi#e% mac,ine

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<! mamou$

MARC 1D (1- E 82 3

t,4 a#ot %u%e ver0 ,e#p&u# artic#e

































REPLY

7! A!C

MARC $D (1- E 68 3

IL ve 'ot a %oubt re'ar%in' interna# %ia'nostic messa'e in CA" network ,ow is t,e &rame %o

t,e0 ,ave somet,in' specia# or %o t,e0 work as a remote &rame w,ere 0ou ask &or some%ata

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https://automotivetechis.wordpress.com/2012/06/18/190/

https://automotivetechis.wordpress.com/2012/06/12/can-calibration-protocolccp/


https://automotivetechis.wordpress.com/2012/06/08/uds-general-vehicle-diagnostics/

https://automotivetechis.wordpress.com/2012/06/07/memory-map-in-c/

https://automotivetechis.wordpress.com/2012/06/06/kwp2000-and-uds-difference/

https://automotivetechis.wordpress.com/2012/06/01/can-basics-faq/




https://automotivetechis.wordpress.com/2012/06/18/190/


https://automotivetechis.wordpress.com/2012/06/08/uds-general-vehicle-diagnostics/

https://automotivetechis.wordpress.com/2012/06/07/memory-map-in-c/

https://automotivetechis.wordpress.com/2012/06/06/kwp2000-and-uds-difference/

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