PLD/FPGA

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IP cores

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ASICsApplication Specific Integrated Circuits

ASSPMicroprocessors Microcontrollers

FPGA & CPLD

FPGA

PLDA B C

Flip-flop

SelectEnable

D Q

Clock

AND plane

MUX

1f

SPLD / /

CPLD SPLD

FPGA

FPGA

16-bit SR

flip-flop

clock

muxy

qe

abcd

16x1 RAM

4-inputLUT

clock enable

set/reset

• Xilinx CLB/SLICE• Altera LE• Lattice: LUTs/LCs

» & & DSP

» PLL DLL

» IO DDR

» MAC

» RAM FIFO

» I2C SPI

» ADCs

Altera

FPGA Stratix Arria Cyclone

PLD MAX II MAX V MAX10

Enpirion PowerSoc DC DC

IP Core

NIOS II ColdFire V1 ARM Cortex M

ARM Cortex A9

Quartus II

Altera MAX10

Xilinx

FPGAFabless

FPGA Virtex Kintex ArtixZYNQ SoCPLD CoolRunner 9500

Xilinx ISEVivado Design Suite

Xilinx ZYNQ

Lattice Semi

FPGA PLD

iCE MachXO ECP

Power Manager Platform Manager

ispClock

Lattice Diamond

Actel(MicroSemi)

» IO

DSP

»

»

»

» RAM

»

Lattice MachXO2 FPGA

HDL VHDL, Verilog, C, Simulink)

Synthesis HDL FPGA

Place & Route

(Bit-File)

FPGA

-

(Modelsim)

(Modelsim)

» /

» vs PLL vs DLL

»

» JTAG

» IO

» IP Core IP

»

» TestBench

»

• / • • /

IP Cores

• • •

• • • /

• FAE • • /

MACHXO2

✦ FPGA LCMXO2-1200HC-4MG132✦ USB 5V✦ 25MHz✦ 3 LED LED✦ 2✦ 2 RGB LED✦ I2C✦ SPI✦ JTAG✦ 29 GPIO

LCD (SPI)

FPGA

1 2 3 4

ON

ADC(SPI)

DAC(SPI)

• FPGA

• Verilog

•

• LED LCD

• DDS

• ADC

• SPI I2C

•

• FPGA IP

• ROM FIFO

• 8